5c4637816e
Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm
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llvm-svn: 45453
2007-12-30 20:49:49 +00:00
f3ebc3f3d2
Remove attribution from file headers, per discussion on llvmdev.
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llvm-svn: 45418
2007-12-29 20:36:04 +00:00
a087a8d2ce
remove attribution from lib Makefiles.
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llvm-svn: 45415
2007-12-29 20:09:26 +00:00
84c7325ca1
Setting GlobalDirective in TargetAsmInfo by default rather than
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providing a misleading facility. It's used once in the MIPS backend
and hardcoded as "\t.globl\t" everywhere else.
llvm-svn: 45338
2007-12-23 20:58:16 +00:00
6e68381e02
Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled.
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llvm-svn: 44960
2007-12-12 23:12:09 +00:00
bb26301864
Add a argument to storeRegToStackSlot and storeRegToAddr to specify whether
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the stored register is killed.
llvm-svn: 44600
2007-12-05 03:14:33 +00:00
f45a1d623c
Remove redundant foldMemoryOperand variants and other code clean up.
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llvm-svn: 44517
2007-12-02 08:30:39 +00:00
69fda0a716
Allow some reloads to be folded in multi-use cases. Specifically testl r, r -> cmpl [mem], 0.
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llvm-svn: 44479
2007-12-01 02:07:52 +00:00
7a7085f6d3
Add parameter to getDwarfRegNum to permit targets
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to use different mappings for EH and debug info;
no functional change yet.
Fix warning in X86CodeEmitter.
llvm-svn: 44056
2007-11-13 19:13:01 +00:00
77b13af9a6
Unifacalize the CALLSEQ{START,END} stuff.
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llvm-svn: 44045
2007-11-13 09:19:02 +00:00
f359fed9f9
Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stack
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adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in
the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If
not, then there is the potential for the stack to be changed while the stack's
being used by another instruction (like a call).
This can only result in tears...
llvm-svn: 44037
2007-11-13 00:44:25 +00:00
b439132d16
Added JumpTable support
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Fixed some AsmPrinter issues
Added GLOBAL_OFFSET_TABLE Node handle.
llvm-svn: 44024
2007-11-12 19:49:57 +00:00
4edfea438a
Use TableGen to emit information for dwarf register numbers.
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This makes DwarfRegNum to accept list of numbers instead.
Added three different "flavours", but only slightly tested on x86-32/linux.
Please check another subtargets if possible,
llvm-svn: 43997
2007-11-11 19:50:10 +00:00
87bb032c05
Better processor definition
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llvm-svn: 43749
2007-11-06 03:15:20 +00:00
3e0d030dad
Added support for PIC code with "explicit relocations" *only*.
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Removed all macro code for PIC (goodbye "la").
Support tested with shootout bench.
llvm-svn: 43697
2007-11-05 03:02:32 +00:00
283207a71c
Eliminate the remaining uses of getTypeSize. This
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should only effect x86 when using long double. Now
12/16 bytes are output for long double globals (the
exact amount depends on the alignment). This brings
globals in line with the rest of LLVM: the space
reserved for an object is now always the ABI size.
One tricky point is that only 10 bytes should be
output for long double if it is a field in a packed
struct, which is the reason for the additional
argument to EmitGlobalConstant.
llvm-svn: 43688
2007-11-05 00:04:43 +00:00
18063916b5
clo/clz aren't supported on mips I. Keep them around for when we'll
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want them later (mips32/64).
llvm-svn: 43380
2007-10-26 04:00:13 +00:00
463e2ab0ac
- Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but only returns the opcode of the instruction post unfolding.
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- Fix some copy+paste bugs.
llvm-svn: 43153
2007-10-18 22:40:57 +00:00
aa9a225699
Use SmallVectorImpl instead of SmallVector with hardcoded size in MRegister public interface.
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llvm-svn: 43150
2007-10-18 21:29:24 +00:00
cdf3609130
Revert 42908 for now.
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llvm-svn: 42960
2007-10-14 05:57:21 +00:00
dc35bd79ca
Change the names used for internal labels to use the current
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function symbol name instead of a codegen-assigned function
number.
Thanks Evan! :-)
llvm-svn: 42908
2007-10-12 14:53:36 +00:00
66d9572ced
Position Independent Code (PIC) support [3]
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llvm-svn: 42780
2007-10-09 03:15:11 +00:00
35d86e60b6
Position Independent Code (PIC) support [2]
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- Added a function to hold the stack location
where GP must be stored during LowerCALL
- AsmPrinter now emits directives based on
relocation type
- PIC_ set to default relocation type (same as GCC)
llvm-svn: 42779
2007-10-09 03:01:19 +00:00
5cef9cfd09
Position Independent Code (PIC) support [1]
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- Modified instruction format to handle pseudo instructions
- Added LoadAddr SDNode to load symbols.
llvm-svn: 42778
2007-10-09 02:55:31 +00:00
f4cf5dcdd2
- Added a few target hooks to generate load / store instructions from / to any
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address (not just from / to frameindexes).
- Added target hooks to unfold load / store instructions / SDNodes into separate
load, data processing, store instructions / SDNodes.
llvm-svn: 42621
2007-10-05 01:32:41 +00:00
c1e4e3743b
Allow copyRegToReg to emit cross register classes copies.
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Tested with "make check"!
llvm-svn: 42346
2007-09-26 06:25:56 +00:00
57211c5550
More explicit keywords.
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llvm-svn: 42316
2007-09-25 20:27:06 +00:00
6d5ada23db
Added "LoadEffective" pattern to handle stack locations.
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Fixed some comments
llvm-svn: 42271
2007-09-24 20:15:11 +00:00
3e18e504ae
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.
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llvm-svn: 41863
2007-09-11 19:55:27 +00:00
86e0119822
Fold the adjust_trampoline intrinsic into
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init_trampoline. There is now only one
trampoline intrinsic.
llvm-svn: 41841
2007-09-11 14:10:23 +00:00
e2f23a3abf
Add lengthof and endof templates that hide a lot of sizeof computations.
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Patch by Sterling Stein!
llvm-svn: 41758
2007-09-07 04:06:50 +00:00
9a25d98c86
Add a variant of foldMemoryOperand to fold any load / store, not just load / store from / to stack slots.
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llvm-svn: 41597
2007-08-30 05:52:20 +00:00
43318839c9
Added method to get Mips register numbers
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Changed the stack frame layout, StackGrowsUp fits better to Mips strange stack.
Stack offset calculation bug fixed!
llvm-svn: 41529
2007-08-28 05:13:42 +00:00
14033fb5cb
Changed stack allocation On LowerFORMAL_ARGUMENTS.
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Added comments about new stack allocation.
Expand SelectCC for i32 results
llvm-svn: 41527
2007-08-28 05:08:16 +00:00
cfd1638e2d
Mask directive completed with CalleeSave info
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Comments for Mips directives added.
llvm-svn: 41526
2007-08-28 05:06:17 +00:00
f55a785e56
Added methods to record SPOffsets from LowerFORMAL_ARGUMENTS
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llvm-svn: 41525
2007-08-28 05:04:41 +00:00
b10580ac1e
InlineAsm asm support for integer registers added
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llvm-svn: 41225
2007-08-21 16:09:25 +00:00
d4b9945a21
Instruction Itinerary attribution fixed
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llvm-svn: 41224
2007-08-21 16:06:45 +00:00
9fbef51078
MipsHi now has ouput flag
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MipsAdd SDNode created to add support to an Add opcode which supports input flag
Added an instruction itinerary to all instruction classes
Added branches with zero cond codes
Now call clobbers all non-callee saved registers
Call w/ register support added
Added DelaySlot to branch and load instructions
Added patterns to handle all setcc, brcond/setcc and MipsAdd instructions
llvm-svn: 41161
2007-08-18 02:37:46 +00:00
eabe61b080
Fixed stack frame addressing bug
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llvm-svn: 41160
2007-08-18 02:19:09 +00:00
f3c55807f2
support for Schedule included on Mips.td
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llvm-svn: 41159
2007-08-18 02:18:07 +00:00
4bd7f4db9f
Removed LowerRETURADDR, fixed small bug into LowerRET, LowerGlobalAddress
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fixed to generate instructions (add, lui) glued!
llvm-svn: 41158
2007-08-18 02:16:30 +00:00
833a1f9b55
Couple of small changes. Delay Slot handle header declared.
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Newline added after macros at function init on generated asm!
llvm-svn: 41157
2007-08-18 02:05:24 +00:00
5792189590
Added InstrItinClass support for instruction formats
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llvm-svn: 41156
2007-08-18 02:01:28 +00:00
0c530638c7
Branch Analysis and InsertNoop inserted into header files
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llvm-svn: 41155
2007-08-18 01:59:45 +00:00
a746512fc5
createMipsDelaySlotFillerPass added to mips codegen runtime
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llvm-svn: 41154
2007-08-18 01:58:15 +00:00
7b616f5742
Added Branch Analysis support
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Added InsertNoop support
llvm-svn: 41153
2007-08-18 01:56:48 +00:00
e8d1c52cd4
LowerRETURNADDR removed since it was wrong and does not have utility yet!
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MipsAdd opcode added
llvm-svn: 41152
2007-08-18 01:54:09 +00:00
87beec9afb
InstrItineraryData support on added.
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Added Mips3 ISA feature (needed when supporting R4000 machines)
llvm-svn: 41151
2007-08-18 01:52:27 +00:00
0b97ce752c
A Pass to insert Nops on intructions with DelaySlot
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llvm-svn: 41150
2007-08-18 01:50:47 +00:00
Chris Lattner