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8 Commits

Author SHA1 Message Date
Eric Christopher 1bbc7086ff Rewrite handling of 64-bit palignr intrinsics to be vector shuffles. 
Stop multiplying constant by 8 accordingly in the header and change
intrinsic definition for what types we expect.

Add to existing palignr test to check that we're emitting the correct things.

llvm-svn: 101332
 2010-04-15 01:43:08 +00:00
Chris Lattner 7eac805bb0 fix PR6658: inline isn't a keyword in C89 mode, use __inline__ instead. 
llvm-svn: 99190
 2010-03-22 18:14:12 +00:00
Nate Begeman 67dfd4236a Revert mmx palignr to use an intrinsic, since mmx shuffle patterns are missing. 
llvm-svn: 91269
 2009-12-14 05:15:02 +00:00
Nate Begeman 72ec6bc6f4 Support x86's PALIGNR instruction without the use of a palignr intrinsic. 
llvm-svn: 91264
 2009-12-14 04:57:03 +00:00
Chris Lattner 399df12fb1 minimal fix for PR5743 
llvm-svn: 91032
 2009-12-10 01:38:15 +00:00
Eli Friedman f5f303f92f Fix obvious typo. 
llvm-svn: 72994
 2009-06-06 07:42:17 +00:00
Anders Carlsson 9603143c5d Fix tyop in SSSE3 header (6808876). 
llvm-svn: 69623
 2009-04-20 20:31:10 +00:00
Anders Carlsson b317efdf81 Add SSSE3 header 
llvm-svn: 64735
 2009-02-17 03:05:04 +00:00