Commit Graph

169 Commits

Author SHA1 Message Date
Jim Grosbach 1e7db68774 Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.
llvm-svn: 116421
2010-10-13 19:56:10 +00:00
Jim Grosbach efd5369749 Add the rest of the ARM so_reg encoding options (register shifted register)
and move to a custom operand encoder. Remove the last of the special handling
stuff from ARMMCCodeEmitter::EncodeInstruction.

llvm-svn: 116377
2010-10-12 23:53:58 +00:00
Jim Grosbach 12e493ace4 Move the ARM so_imm encoding into a custom operand encoder and remove the
explicit handling of the instructions referencing it from the MC code
emitter.

llvm-svn: 116367
2010-10-12 23:18:08 +00:00
Jim Grosbach d9d31dafda Add custom encoder for the 's' bit denoting whether an ARM arithmetic
instruction should set the processor status flags or not. Remove the now
unnecessary special handling for the bit from the MCCodeEmitter.

llvm-svn: 116360
2010-10-12 23:00:24 +00:00
Jim Grosbach b770c00610 Reapply 116059, this time without the fatfingered pasto at the top.
''const'ify getMachineOpValue() and associated helpers.'

llvm-svn: 116067
2010-10-08 17:45:54 +00:00
Jim Grosbach 00351b7731 Reverting 116059. Bots are unhappy with it.
llvm-svn: 116064
2010-10-08 17:28:40 +00:00
Jim Grosbach e2d30cd4b5 'const'ify getMachineOpValue() and associated helpers.
llvm-svn: 116059
2010-10-08 16:52:44 +00:00
Jim Grosbach a7b6d58f45 Make <target>CodeEmitter::getBinaryCodeForInstr() a const method.
llvm-svn: 116018
2010-10-08 00:21:28 +00:00
Jim Grosbach 40e85fbf17 move getRegisterNumbering() to out of ARMBaseRegisterInfo into the helper
functions in ARMBaseInfo.h so it can be used in the MC library as well.
For anything bigger than this, we may want a means to have a small support
library for shared helper functions like this. Cross that bridge when we
come to it.

llvm-svn: 114016
2010-09-15 20:26:25 +00:00
Jim Grosbach 789ca9a1e9 Refactor uses of getRegisterNumbering() to not need the isSPVFP argument. Check
if the register is a member of the SPR register class directly instead.

llvm-svn: 114012
2010-09-15 19:44:57 +00:00
Chris Lattner 65b48b5dfc zap dead code.
llvm-svn: 113073
2010-09-04 18:12:00 +00:00
Bob Wilson 13ce07fa92 Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just like
all the other LDM/STM instructions.  This fixes asm printer crashes when
compiling with -O0.  I've changed one of the NEON tests (vst3.ll) to run
with -O0 to check this in the future.

Prior to this change VLDM/VSTM used addressing mode #5, but not really.
The offset field was used to hold a count of the number of registers being
loaded or stored, and the AM5 opcode field was expanded to specify the IA
or DB mode, instead of the standard ADD/SUB specifier.  Much of the backend
was not aware of these special cases.  The crashes occured when rewriting
a frameindex caused the AM5 offset field to be changed so that it did not
have a valid submode.  I don't know exactly what changed to expose this now.
Maybe we've never done much with -O0 and NEON.  Regardless, there's no longer
any reason to keep a count of the VLDM/VSTM registers, so we can use
addressing mode #4 and clean things up in a lot of places.

llvm-svn: 112322
2010-08-27 23:18:17 +00:00
Bob Wilson 942b10f511 Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoid
printing "lsl #0".  This fixes the remaining parts of pr7792.  Make
corresponding changes for encoding/decoding these instructions.

llvm-svn: 111251
2010-08-17 17:23:19 +00:00
Bob Wilson add513112a Move the ARM SSAT and USAT optional shift amount operand out of the
instruction opcode.  This also fixes part of PR7792.

llvm-svn: 110875
2010-08-11 23:10:46 +00:00
Bob Wilson 9664984be8 Add a separate ARM instruction format for Saturate instructions.
(I discovered 2 more copies of the ARM instruction format list, bringing the
total to 4!!  Two of them were already out of sync.  I haven't yet gotten into
the disassembler enough to know the best way to fix this, but something needs
to be done.)  Add support for encoding these instructions.

llvm-svn: 110754
2010-08-11 00:01:18 +00:00
Owen Anderson a7aed18624 Reapply r110396, with fixes to appease the Linux buildbot gods.
llvm-svn: 110460
2010-08-06 18:33:48 +00:00
Owen Anderson bda59bd247 Revert r110396 to fix buildbots.
llvm-svn: 110410
2010-08-06 00:23:35 +00:00
Owen Anderson 755aceb5d0 Don't use PassInfo* as a type identifier for passes. Instead, use the address of the static
ID member as the sole unique type identifier.  Clean up APIs related to this change.

llvm-svn: 110396
2010-08-05 23:42:04 +00:00
Xerxes Ranby ff66cd43c4 ARMv4 JIT forgets to set the lr register when making a indirect function call. Fixes PR7608
llvm-svn: 109125
2010-07-22 17:28:34 +00:00
Bill Wendling 499f797cdd Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission and
thus is a much more meaningful name.

llvm-svn: 108563
2010-07-16 22:20:36 +00:00
Bob Wilson be157b0ea8 Add support for encoding VDUP (ARM core register) instructions.
llvm-svn: 107201
2010-06-29 20:13:29 +00:00
Bob Wilson ab0819e10d Add support for encoding NEON VMOV (from core register to scalar) instructions.
The encoding is the same as VMOV (from scalar to core register) except that
the operands are in different places.

llvm-svn: 107167
2010-06-29 17:34:07 +00:00
Bob Wilson 3d12ff797b Fix Thumb encoding of VMOV (scalar to ARM core register). The encoding is
the same as ARM except that the condition code field is always set to ARMCC::AL.

llvm-svn: 107107
2010-06-29 00:26:13 +00:00
Bob Wilson 4469a892b4 Make the ARMCodeEmitter identify Thumb functions via ARMFunctionInfo instead
of the Subtarget.

llvm-svn: 107086
2010-06-28 22:23:17 +00:00
Bob Wilson 544317dfda Refactor encoding function for NEON 1-register with modified immediate format.
llvm-svn: 107070
2010-06-28 21:16:30 +00:00
Bob Wilson 584387d5e3 Support Thumb mode encoding of NEON instructions.
llvm-svn: 107068
2010-06-28 21:12:19 +00:00
Bob Wilson 0248da9db4 Add support for encoding NEON VMOV (from scalar to core register) instructions.
llvm-svn: 106938
2010-06-26 04:07:15 +00:00
Bob Wilson 2530ca0647 Add support for encoding 3-register NEON instructions, and fix
emitNEON2RegInstruction's handling of 2-address operands.

llvm-svn: 106900
2010-06-25 22:40:46 +00:00
Bob Wilson e70c8b150b Add support for encoding 2-register NEON instructions.
llvm-svn: 106891
2010-06-25 21:17:19 +00:00
Dan Gohman d2d1ae105d Use pre-increment instead of post-increment when the result is not used.
llvm-svn: 106542
2010-06-22 15:08:57 +00:00
Bob Wilson 6eae520de9 Add instruction encoding for the Neon VMOV immediate instruction. This changes
the machine instruction representation of the immediate value to be encoded
into an integer with similar fields as the actual VMOV instruction.  This makes
things easier for the disassembler, since it can just stuff the bits into the
immediate operand, but harder for the asm printer since it has to decode the
value to be printed.  Testcase for the encoding will follow later when MC has
more support for ARM.

llvm-svn: 105836
2010-06-11 21:34:50 +00:00
Jim Grosbach 84511e1526 Clean up 80 column violations. No functional change.
llvm-svn: 105350
2010-06-02 21:53:11 +00:00
Shih-wei Liao c4376b9b1b Coding style change (Adding 1 missing space.)
llvm-svn: 104670
2010-05-26 04:46:50 +00:00
Shih-wei Liao 0568ca0ddc Adding the missing implementation for ARM::SBFX and ARM::UBFX.
Fixing http://llvm.org/bugs/show_bug.cgi?id=7225.

llvm-svn: 104667
2010-05-26 03:21:39 +00:00
Shih-wei Liao b6e0bc9457 Adding the missing implementation of Bitfield's "clear" and "insert".
Fixing http://llvm.org/bugs/show_bug.cgi?id=7222.

llvm-svn: 104653
2010-05-26 00:25:05 +00:00
Shih-wei Liao e22abfa823 To handle s* registers in emitVFPLoadStoreMultipleInstruction().
Fixing http://llvm.org/bugs/show_bug.cgi?id=7221.

llvm-svn: 104652
2010-05-26 00:02:28 +00:00
Zonr Chang a6714e8a43 Add missing implementation to the materialization of VFP misc. instructions (vmrs, vmsr and vmov (immediate))
llvm-svn: 104588
2010-05-25 10:23:52 +00:00
Zonr Chang 2da5aa1b60 Add support to MOVimm32 using movt/movw for ARM JIT
llvm-svn: 104587
2010-05-25 08:42:45 +00:00
Dan Gohman 1f0f2142cc Fix -Wcast-qual warnings.
llvm-svn: 101655
2010-04-17 17:42:52 +00:00
Dan Gohman bcaf681cde Add const qualifiers to CodeGen's use of LLVM IR constructs.
llvm-svn: 101334
2010-04-15 01:51:59 +00:00
Chris Lattner 2104b8d36e rename llvm::llvm_report_error -> llvm::report_fatal_error
llvm-svn: 100709
2010-04-07 22:58:41 +00:00
Bob Wilson a6fe21a79a Clean up whitespace.
llvm-svn: 98769
2010-03-17 21:16:45 +00:00
Bob Wilson 466d1e3dc2 Remove redundant writeback flag in ARM addressing mode 5.
llvm-svn: 98648
2010-03-16 18:38:09 +00:00
Bob Wilson d6243b49d4 Remove the writeback flag from ARM's address mode 4. Now that we have separate
instructions for ld/st with writeback, the flag is completely redundant.

llvm-svn: 98643
2010-03-16 17:46:45 +00:00
Chris Lattner c26f44fb07 change the DBG_LABEL MachineInstr to always be created
with an MCSymbol instead of an immediate.

llvm-svn: 98481
2010-03-14 07:56:48 +00:00
Chris Lattner ee2fbbc978 change the LabelSDNode to be EHLabelSDNode and make it hold
an MCSymbol.  Make the EH_LABEL MachineInstr hold its label
with an MCSymbol instead of ID.  Fix a bug in MMI.cpp which
would return labels named "Label4" instead of "label4".

llvm-svn: 98463
2010-03-14 02:33:54 +00:00
Chris Lattner 34adc8d225 change EH related stuff (other than EH_LABEL) to use MCSymbol
instead of label ID's.  This cleans up and regularizes a bunch 
of code and makes way for future progress.

Unfortunately, this pointed out to me that JITDwarfEmitter.cpp
is largely copy and paste from DwarfException/MachineModuleInfo
and other places.  This is very sad and disturbing. :(

One major change here is that TidyLandingPads moved from being
called in DwarfException::BeginFunction to being called in
DwarfException::EndFunction.  There should not be any 
functionality change from doing this, but I'm not an EH expert.

llvm-svn: 98459
2010-03-14 01:41:15 +00:00
Bob Wilson f1e8f7ff7d Attempt to appease the arm-linux buildbot by fixing the JIT encodings for new
base register updating load/store-multiple instructions.

llvm-svn: 98427
2010-03-13 07:34:35 +00:00
Bob Wilson 1b0e614b10 Fix ARM buildbot breakage.
llvm-svn: 98215
2010-03-11 00:46:22 +00:00
Bob Wilson c4ceb1e2f8 Fix an obvious typo in an assert.
Patch by Sean Callanan.

llvm-svn: 98200
2010-03-10 22:38:45 +00:00