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3315 Commits

Author SHA1 Message Date
Eric Christopher ef83e21b57 Update comment. 
llvm-svn: 116438
 2010-10-13 21:41:51 +00:00
Jim Grosbach 9874b7de58 Add a FIXME. The ADR instruction is a bit odd. 
llvm-svn: 116437
 2010-10-13 21:32:30 +00:00
Jim Grosbach 7e72ec6626 Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern 
and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.

llvm-svn: 116432
 2010-10-13 21:00:04 +00:00
Bill Wendling f106ecfa59 Add MC encodings for VCVT* instrunctions. 
llvm-svn: 116431
 2010-10-13 20:58:46 +00:00
Jim Grosbach fb07ef19cc Add a FIXME. 
llvm-svn: 116428
 2010-10-13 20:38:04 +00:00
Jim Grosbach efc066829b Make a few more bits of some simple instructions explicit. nop, yield, wfe, 
wfi, sel, sev and bkpt. All would disassemble properly before, but more
explicitness is good, especially with the integrated assembler coming in
the future.

llvm-svn: 116427
 2010-10-13 20:30:55 +00:00
Jim Grosbach 1e7db68774 Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions. 
llvm-svn: 116421
 2010-10-13 19:56:10 +00:00
Jim Grosbach 142e3cbb26 Fix encoding for compares. No Rd register. 
llvm-svn: 116414
 2010-10-13 18:05:25 +00:00
Jim Grosbach 651dc7c9e9 Add ARM mode operand encoding information for ADDE/SUBE instructions. 
llvm-svn: 116412
 2010-10-13 18:00:52 +00:00
Eric Christopher dd0821e7ff Start handling more global variables. 
llvm-svn: 116401
 2010-10-13 09:11:46 +00:00
Evan Cheng 3912158997 Limit load / store issues (at least until we have a true multi-issue aware scheduler). 
llvm-svn: 116389
 2010-10-13 01:54:21 +00:00
Bill Wendling 6e27b4f530 Add encodings for VNEG and VSQRT. Also add encodings for VMOV, but not a test 
just yet.

llvm-svn: 116386
 2010-10-13 01:17:33 +00:00
Bill Wendling 576fd0b110 Add encodings for VCVT instructions. 
llvm-svn: 116385
 2010-10-13 00:56:35 +00:00
Jim Grosbach 8c519c0d4b Add ARM encoding information for comparisons, forced-cc-out arithmetics, and 
arithmetic-with-carry-in instructions.

llvm-svn: 116384
 2010-10-13 00:50:27 +00:00
Bill Wendling da4ddf0fcf Add VCMPZ and VABS. 
llvm-svn: 116383
 2010-10-13 00:38:07 +00:00
Bill Wendling f9ca535495 Refactor VCMP instructions. 
llvm-svn: 116379
 2010-10-13 00:04:29 +00:00
Jim Grosbach efd5369749 Add the rest of the ARM so_reg encoding options (register shifted register) 
and move to a custom operand encoder. Remove the last of the special handling
stuff from ARMMCCodeEmitter::EncodeInstruction.

llvm-svn: 116377
 2010-10-12 23:53:58 +00:00
Bill Wendling 7dd8c0b991 Add encodings for VNMUL[SD]. 
llvm-svn: 116375
 2010-10-12 23:47:37 +00:00
Bill Wendling a06aee826c Add encodings for VDIV and VMUL. 
llvm-svn: 116370
 2010-10-12 23:22:27 +00:00
Jim Grosbach 12e493ace4 Move the ARM so_imm encoding into a custom operand encoder and remove the 
explicit handling of the instructions referencing it from the MC code
emitter.

llvm-svn: 116367
 2010-10-12 23:18:08 +00:00
Bill Wendling 42200bcaea Refactor some of the encoding logic into a base class. This keeps us from having 
to add 10+ lines to every instruction.

It may turn out that we can move this base class into it's parent class.

llvm-svn: 116362
 2010-10-12 23:06:54 +00:00
Jim Grosbach d9d31dafda Add custom encoder for the 's' bit denoting whether an ARM arithmetic 
instruction should set the processor status flags or not. Remove the now
unnecessary special handling for the bit from the MCCodeEmitter.

llvm-svn: 116360
 2010-10-12 23:00:24 +00:00
Bill Wendling 646a506724 Add encoding for VSUB and VCMP. 
Fear not! I'm going to try a refactoring right now. :)

llvm-svn: 116359
 2010-10-12 22:55:35 +00:00
Bill Wendling ac6cd00706 Encoding for VADDD. Plus a test for the VFP instructions. 
llvm-svn: 116348
 2010-10-12 22:08:41 +00:00
Bill Wendling 98c29d732d Split out the "size" field from the encoding. The newer documentation has it as 
a separate bit in the coding.

llvm-svn: 116347
 2010-10-12 22:03:19 +00:00
Eric Christopher 22e051eef0 Fix thinko in arm fast isel alloca rewrite. 
llvm-svn: 116339
 2010-10-12 21:23:43 +00:00
Jim Grosbach 576640f0e3 Encoding for ARM-mode VADD.F32 instruction. 
llvm-svn: 116338
 2010-10-12 21:22:40 +00:00
Jim Grosbach 0e57a9f7a9 Add MOVi ARM encoding. 
llvm-svn: 116321
 2010-10-12 18:09:12 +00:00
Jim Grosbach feeae27ad9 Nuke unused wrapper function. 
llvm-svn: 116318
 2010-10-12 17:53:25 +00:00
Jim Grosbach 6fead930af Add encoding information for the remainder of the generic arithmetic 
ARM instructions.

llvm-svn: 116313
 2010-10-12 17:11:26 +00:00
Bob Wilson dd6eb5b5a1 PR8359: The ARM backend may end up allocating registers D16 to D31 when 
"-mattr=+vfp3" is specified. However, this will not work for hardware that
only supports 16 registers.  Add a new flag to support -"mattr=+vfp3,+d16".
Patch by Jan Voung!

llvm-svn: 116310
 2010-10-12 16:22:47 +00:00
Eric Christopher 7cd5cda6bb Rework alloca handling so that we can load or store from casted 
address that we've looked through.

Fixes compilation problems in tramp3d from earlier patch.

llvm-svn: 116296
 2010-10-12 05:39:06 +00:00
Eric Christopher db3bcc9910 Handle a wider arrangement of loads. 
llvm-svn: 116284
 2010-10-12 00:43:21 +00:00
Evan Cheng e790afcbe1 More ARM scheduling itinerary fixes. 
llvm-svn: 116266
 2010-10-11 23:41:41 +00:00
Jim Grosbach b7c2962d20 MC machine encoding for simple aritmetic instructions that use a shifted 
register operand.

llvm-svn: 116259
 2010-10-11 23:16:21 +00:00
Jason W Kim 109ff296c8 Second set of ARM/MC/ELF changes. 
Added ARM specific ELF section types.
Added AttributesSection to ARMElfTargetObject
First step in unifying .cpu assembly tag with ELF/.o
llc now asserts on actual ELF emission on -filetype=obj :-)

llvm-svn: 116257
 2010-10-11 23:01:44 +00:00
Evan Cheng 94ad008beb Proper VST scheduling itineraries. 
llvm-svn: 116251
 2010-10-11 22:03:18 +00:00
Eric Christopher d42340ecfd Use a sane mechanism for that assert. 
llvm-svn: 116249
 2010-10-11 22:01:22 +00:00
Eric Christopher 72b91c1765 We're not going to handle dynamic allocas anywhere else. 
llvm-svn: 116240
 2010-10-11 21:37:35 +00:00
Eric Christopher 71ef1af66b Make sure that the call stack adjustments have default operands. Also 
leave custom lowerings for later.

Fixes some nightly tests.

llvm-svn: 116232
 2010-10-11 21:20:02 +00:00
Eric Christopher e2a0b6841a Found a bug turning this on by default. Disable again for now. 
llvm-svn: 116220
 2010-10-11 20:26:21 +00:00
Eric Christopher 46cc854e5e Fix help text. 
llvm-svn: 116218
 2010-10-11 20:15:02 +00:00
Eric Christopher 5501b7e805 Change flag from Enable to Disable since we're enabled by default. 
Also don't use fast-isel on non-darwin since it's untested.

llvm-svn: 116217
 2010-10-11 20:05:22 +00:00
Jim Grosbach 5476a274c8 More binary encoding stuff, taking advantage of the new "by name" operand 
matching in tblgen to do the predicate operand.

llvm-svn: 116213
 2010-10-11 18:51:51 +00:00
Eric Christopher 2276e87a65 Turn on arm fast isel by default. 
llvm-svn: 116212
 2010-10-11 18:48:18 +00:00
Francois Pichet 0f5bfd27a3 MSVC hangs on compilation of ARMDisassembler.cpp. PR6866 applied to ARM target. 
llvm-svn: 116201
 2010-10-11 11:36:19 +00:00
Eric Christopher e1bcb43bb9 Copy and pasteo. 
llvm-svn: 116198
 2010-10-11 08:40:05 +00:00
Eric Christopher 7ac602bc8e Whitespace cleanup in ARM fast isel. 
llvm-svn: 116197
 2010-10-11 08:38:55 +00:00
Eric Christopher eae1b38550 Add srem libcall support to ARM fast isel. 
llvm-svn: 116196
 2010-10-11 08:37:26 +00:00
Eric Christopher e11017c19e Add i8 sdiv support for ARM fast isel. 
llvm-svn: 116195
 2010-10-11 08:31:54 +00:00