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10 Commits

Author SHA1 Message Date
Craig Topper 6533e40e9d [X86] Fix vector ANDN matching to work correctly when both inputs to the AND are XORs. 
llvm-svn: 293403
 2017-01-28 23:52:09 +00:00
Sanjay Patel a0d8a278a7 [x86] use a single shufps when it can save instructions 
This is a tiny patch with a big pile of test changes.
This partially fixes PR27885:
https://llvm.org/bugs/show_bug.cgi?id=27885

My motivating case looks like this:

  - vpshufd {{.*#+}} xmm1 = xmm1[0,1,0,2]
  - vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
  - vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]

  + vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]

And this happens several times in the diffs. For chips with domain-crossing penalties,
the instruction count and size reduction should usually overcome any potential 
domain-crossing penalty due to using an FP op in a sequence of int ops. For chips such
as recent Intel big cores and Atom, there is no domain-crossing penalty for shufps, so
using shufps is a pure win.

So the test case diffs all appear to be improvements except one test in 
vector-shuffle-combining.ll where we miss an opportunity to use a shift to generate 
zero elements and one test in combine-sra.ll where multiple uses prevent the expected
shuffle combining.

Differential Revision: https://reviews.llvm.org/D27692

llvm-svn: 289837
 2016-12-15 18:03:38 +00:00
Simon Pilgrim fe9fa7314c [X86][SSE] Regenerate vsplit and tests 
To make it more obvious how bad some of that truncation code is....

llvm-svn: 283880
 2016-10-11 13:51:44 +00:00
Paul Redmond 62f840f46a Improve the widening of integral binary vector operations 
- split WidenVecRes_Binary into WidenVecRes_Binary and WidenVecRes_BinaryCanTrap
  - WidenVecRes_BinaryCanTrap preserves the original behaviour for operations
    that can trap
  - WidenVecRes_Binary simply widens the operation and improves codegen for
    3-element vectors by allowing widening and promotion on x86 (matches the
    behaviour of unary and ternary operation widening)
- use WidenVecRes_Binary for operations on integers.

Reviewed by: nrotem

llvm-svn: 188699
 2013-08-19 20:01:35 +00:00
Benjamin Kramer a9f265ee98 Harden test so it's not affected by changes to compare lowering. 
This only failed on hosts that don't have SSE41.

llvm-svn: 171066
 2012-12-25 13:23:23 +00:00
Nadav Rotem 83d1a93cf4 Clean the triple, add check lines. 
llvm-svn: 142183
 2011-10-17 07:07:51 +00:00
Nadav Rotem 053a7358d6 Add tripple and stabalize a few more tests. 
llvm-svn: 142158
 2011-10-16 21:20:54 +00:00
Nadav Rotem 486ff59a9f Enable element promotion type legalization by deafault. 
Changed tests which assumed that vectors are legalized by widening them.

llvm-svn: 142152
 2011-10-16 20:31:33 +00:00
Chris Lattner ff392ab3ed now that generic vector types aren't selected onto MMX registers, these 
tests don't need -disable-mmx.

llvm-svn: 122188
 2010-12-19 20:12:58 +00:00
Mon P Wang 4f45512c23 It seems better to scalarize vectors of size 1 instead of widening them. 
Add support to widen SETCC.

llvm-svn: 94342
 2010-01-24 00:24:43 +00:00