llvm-project

Author	SHA1	Message	Date
Krzysztof Parzyszek	a72fad980c	[Hexagon] Replace instruction definitions with auto-generated ones llvm-svn: 294753	2017-02-10 15:33:13 +00:00
Colin LeMahieu	3c740a3614	[Hexagon] Organizing tests and adding a few missing jump instruction encodings. llvm-svn: 227498	2015-01-29 21:47:15 +00:00
Colin LeMahieu	bc63f42e0d	[Hexagon] Adding missing instruction encodings and tests. llvm-svn: 227495	2015-01-29 21:30:22 +00:00
Colin LeMahieu	377ac65340	[Hexagon] Adding compare byte/halfword reg-reg/reg-imm forms. Adding compare to general register reg-imm form. llvm-svn: 224991	2014-12-30 17:39:24 +00:00
Colin LeMahieu	d7a56fd9ff	[Hexagon] Updating constant extender def, adding alu-not instructions, compare to general register, and inverted compares. llvm-svn: 224989	2014-12-30 15:44:17 +00:00
Colin LeMahieu	b030c254c0	[Hexagon] Fixing broken tests. llvm-svn: 223823	2014-12-09 20:36:53 +00:00
Colin LeMahieu	4af437fee5	[Hexagon] Updating rr/ri 32/64 transfer encodings and adding tests. llvm-svn: 223821	2014-12-09 20:23:30 +00:00
Colin LeMahieu	b580d7d8c8	[Hexagon] Adding word combine dot-new form and replacing old combine opcode. llvm-svn: 223815	2014-12-09 19:23:45 +00:00
Colin LeMahieu	b56e6cd9b9	[Hexagon] Adding combine reg, reg with predicated forms. llvm-svn: 223667	2014-12-08 17:33:06 +00:00
Colin LeMahieu	01785bb063	[Hexagon] Marking several instructions as isCodeGenOnly=0 and adding direct disassembly tests for many instructions. llvm-svn: 223482	2014-12-05 17:27:39 +00:00