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88862 Commits

Author SHA1 Message Date
Evan Cheng 163b624b4e ArchV7M implies HW division instructions. 
llvm-svn: 110797
 2010-08-11 07:00:16 +00:00
Evan Cheng 1c3c0009bd ArchV6T2, V7A, and V7M implies Thumb2; Archv7A implies NEON. 
llvm-svn: 110796
 2010-08-11 06:57:53 +00:00
Evan Cheng 40921a4e62 Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.) 
llvm-svn: 110795
 2010-08-11 06:51:54 +00:00
Daniel Dunbar 188b47b214 MC/ARM: Add basic support for handling predication by parsing it out of the mnemonic into a separate operand form. 
llvm-svn: 110794
 2010-08-11 06:37:20 +00:00
Daniel Dunbar 75d26be81a MC/ARM: Split mnemonic on '.' characters. 
llvm-svn: 110793
 2010-08-11 06:37:16 +00:00
Daniel Dunbar 4a863e6cf7 MC/ARM: Fill in ARMOperand::dump a bit. 
llvm-svn: 110792
 2010-08-11 06:37:12 +00:00
Daniel Dunbar 2eca0252c3 llvm-mc: Add -show-inst-operands, for dumping the parsed instruction representation before matching. 
llvm-svn: 110791
 2010-08-11 06:37:09 +00:00
Daniel Dunbar ebace2248f MCAsmParser: Add dump() hook to MCParsedAsmOperand. 
llvm-svn: 110790
 2010-08-11 06:37:04 +00:00
Daniel Dunbar 69f024b855 tblgen/AsmMatcher: Treat '.' in assembly strings as a token separator. 
llvm-svn: 110789
 2010-08-11 06:36:59 +00:00
Daniel Dunbar d8042b7bd7 MC/ARM: Add an ARMOperand class for condition codes. 
llvm-svn: 110788
 2010-08-11 06:36:53 +00:00
Evan Cheng 91033bed94 Really control isel of barrier instructions with cpu feature. 
llvm-svn: 110787
 2010-08-11 06:36:31 +00:00
Evan Cheng 49e02fc414 Add Cortex-M0 support. It's a ARMv6m device (no ARM mode) with some 32-bit 
instructions: dmb, dsb, isb, msr, and mrs.

llvm-svn: 110786
 2010-08-11 06:30:38 +00:00
Evan Cheng 6e809de90c - Add subtarget feature -mattr=+db which determine whether an ARM cpu has the 
memory and synchronization barrier dmb and dsb instructions.
- Change instruction names to something more sensible (matching name of actual
  instructions).
- Added tests for memory barrier codegen.

llvm-svn: 110785
 2010-08-11 06:22:01 +00:00
Zhongxing Xu 8de0a3d8c3 MemRegion can refer to ASTContext without external help. 
llvm-svn: 110784
 2010-08-11 06:10:55 +00:00
Daniel Dunbar 5cd4d0f9ac MC/ARM: Switch to using the generated match functions instead of stub implementations. 
llvm-svn: 110783
 2010-08-11 05:24:50 +00:00
Daniel Dunbar 56e77c409b MC/ARM: Enable generation of the ARM asm matcher, not that it can do much. 
llvm-svn: 110782
 2010-08-11 05:09:20 +00:00
Daniel Dunbar 07cc87438f ARM: Mark some disassembler only instructions as not available for matching -- 
for some reason they have a very odd MCInst form where the operands overlap, but
I haven't dug in to find out why yet.

llvm-svn: 110781
 2010-08-11 04:46:13 +00:00
Daniel Dunbar 740c50385c ARM: Quote $p in an asm string. 
llvm-svn: 110780
 2010-08-11 04:46:10 +00:00
Daniel Dunbar 1326056108 tblgen/AsmMatcher: Downgrade instructions with tied operands to a debug-only warning, for now. 
llvm-svn: 110779
 2010-08-11 04:46:08 +00:00
Owen Anderson 0bd61240e9 Improve indentation. 
llvm-svn: 110778
 2010-08-11 04:24:25 +00:00
Sean Callanan 2235f32bbd Added support for persistent variables to the 
expression parser.  It is now possible to type:

(lldb) expr int $i = 5; $i + 1
(int) 6
(lldb) expr $i + 2
(int) 7

The skeleton for automatic result variables is
also implemented.  The changes affect:

- the process, which now contains a 
  ClangPersistentVariables object that holds
  persistent variables associated with it
- the expression parser, which now uses
  the persistent variables during variable
  lookup
- TaggedASTType, where I loaded some commonly
  used tags into a header so that they are
  interchangeable between different clients of
  the class

llvm-svn: 110777
 2010-08-11 03:57:18 +00:00
Daniel Dunbar 00012c869f tests: Add a missing -Xclang. 
llvm-svn: 110776
 2010-08-11 02:32:03 +00:00
Daniel Dunbar 9034aa36c7 ARM: Recognize single precision float register names. 
- We don't recognize double or NEON register names yet -- we don't have the
   infrastructure to generate the right clobbers for them.

llvm-svn: 110775
 2010-08-11 02:17:20 +00:00
Daniel Dunbar 256e1f3ad0 ARM: Swap which registers we consider real / aliases to match LLVM and llvm-gcc. 
llvm-svn: 110774
 2010-08-11 02:17:11 +00:00
Douglas Gregor 836a7e8468 Improve our handling of user-defined conversions when computing 
implicit conversion sequences. In particular, model the "standard
conversion" from a class to its own type (or a base type) directly as
a standard conversion in the normal path *without* trying to determine
if there is a valid copy constructor. This appears to match the intent
of C++ [over.best.ics]p6 and more closely matches GCC and EDG.

As part of this, model non-lvalue reference initialization via
user-defined conversion in overloading the same way we handle it in
InitializationSequence, separating the "general user-defined
conversion" and "conversion to compatible class type" cases.

The churn in the overload-call-copycon.cpp test case is because the
test case was originally wrong; it assumed that we should do more
checking for copy constructors that we actually should, which affected
overload resolution.

Fixes PR7055. Bootstrapped okay.

llvm-svn: 110773
 2010-08-11 02:15:33 +00:00
Bruno Cardoso Lopes 8c9c9c77c8 Remove AVX 256-bit cast intrinsics now that clang is using __builtin_shufflevector for those 
llvm-svn: 110772
 2010-08-11 02:15:33 +00:00
Bruno Cardoso Lopes 65954ffc69 Remove 256-bit cast built-ins and make the AVX intrinsic call llvm __builtin_shufflevector with the appropriate arguments 
llvm-svn: 110771
 2010-08-11 02:14:38 +00:00
John McCall ca7993f572 Make this test a little less dependent on exact optimizer results. 
llvm-svn: 110770
 2010-08-11 02:06:44 +00:00
Bruno Cardoso Lopes 4134f97e56 Remove AVX 256-bit unpack and interleave intrinsics now that clang is using __builtin_shufflevector for those 
llvm-svn: 110769
 2010-08-11 01:44:11 +00:00
Bruno Cardoso Lopes a4f1930b75 Remove 256-bit unpack built-ins and make the AVX intrinsic call llvm __builtin_shufflevector with the appropriate arguments 
llvm-svn: 110768
 2010-08-11 01:43:24 +00:00
Bruno Cardoso Lopes 90b238c68b Remove AVX 256-bit shuffle intrinsics now that clang is using __builtin_shufflevector for those 
llvm-svn: 110767
 2010-08-11 01:18:26 +00:00
Bruno Cardoso Lopes e712a135b7 Remove 256-bit shuffle built-ins and make the AVX intrinsic call llvm __builtin_shufflevector with the appropriate arguments 
llvm-svn: 110766
 2010-08-11 01:17:34 +00:00
Bill Wendling 79937dfc5b Update test to match output of optimize compares for ARM. 
llvm-svn: 110765
 2010-08-11 01:05:02 +00:00
John Thompson 46667afccd Fix for pr7869, inline asm mult-alt constraints. 
llvm-svn: 110764
 2010-08-11 00:58:20 +00:00
Oscar Fuentes 945f64ebac CMake: corrections on LLVM.cmake external services. 
llvm-svn: 110763
 2010-08-11 00:51:32 +00:00
Bill Wendling 79553bad50 Handle ARM compares as well as converting for ARM adds, subs, and thumb2's adds. 
llvm-svn: 110762
 2010-08-11 00:23:00 +00:00
Bill Wendling 920f74aaab Mark ARM compare instructions as isCompare. 
llvm-svn: 110761
 2010-08-11 00:22:27 +00:00
John McCall cebe0ca75e Fix a bug in @finally emission in both the fragile and non-fragile EH schemes 
where we weren't accounting for the possibility that a @finally block might
have internal cleanups and therefore might write to the cleanup destination slot.

Fixes <rdar://problem/8293901>.

llvm-svn: 110760
 2010-08-11 00:16:14 +00:00
Rafael Espindola ccab1dddd1 Make it possible to set the cpu used for codegen. 
llvm-svn: 110759
 2010-08-11 00:15:13 +00:00
Dan Gohman f7495f286a When analyzing loop exit conditions combined with and and or, don't 
make any assumptions about when the two conditions will agree on when
to permit the loop to exit. This fixes PR7845.

llvm-svn: 110758
 2010-08-11 00:12:36 +00:00
Daniel Dunbar a8272596bc lto: Fix an inverted conditional which prevented the addition of symbols scraped 
from inline assembly, except in cases where they had already been seen (in which
case they would get added twice).
 - I can't see how this ever worked...

llvm-svn: 110757
 2010-08-11 00:11:19 +00:00
Daniel Dunbar 4493c7e550 lto: Fix gratuitous memory leaks. 
llvm-svn: 110756
 2010-08-11 00:11:17 +00:00
Ted Kremenek 2b4adffa16 Have GRCoreEngine record the blocks where analysis was aborted because we visited a block too many times along a given path. This is to support the unreachable code analysis. 
llvm-svn: 110755
 2010-08-11 00:03:02 +00:00
Bob Wilson 9664984be8 Add a separate ARM instruction format for Saturate instructions. 
(I discovered 2 more copies of the ARM instruction format list, bringing the
total to 4!!  Two of them were already out of sync.  I haven't yet gotten into
the disassembler enough to know the best way to fix this, but something needs
to be done.)  Add support for encoding these instructions.

llvm-svn: 110754
 2010-08-11 00:01:18 +00:00
Oscar Fuentes daf5881128 Avoid multiple definition warnings when both config.h and 
llvm-config.h are included.

This is the cmake counterpart of r110547. See bug #7809.

llvm-svn: 110753
 2010-08-10 23:48:22 +00:00
Daniel Dunbar 919660b2ed lto: Reduce nesting. 
llvm-svn: 110752
 2010-08-10 23:46:46 +00:00
Daniel Dunbar 5657e7b667 LTOModule.cpp: Fix numerous style issues. 
llvm-svn: 110751
 2010-08-10 23:46:39 +00:00
Dan Gohman e18c2d6f99 Rename and reorder the arguments to isImpliedCond, for consistency and clarity. 
llvm-svn: 110750
 2010-08-10 23:46:30 +00:00
Eric Christopher e264e092bf We already have this as OperandNode. 
llvm-svn: 110748
 2010-08-10 23:46:20 +00:00
Evan Cheng 5415713d9a CBZ and CBNZ are implemented. 
llvm-svn: 110745
 2010-08-10 23:27:11 +00:00