d2e2f56c36
Teach ARM/MC/ELF to handle R_ARM_JUMP24 relocation type for conditional jumps.
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(yes, this is different from R_ARM_CALL)
- Adds a new method getARMBranchTargetOpValue() which handles the
necessary distinction between the conditional and unconditional br/bl
needed for ARM/ELF
At least for ARM mode, the needed fixup for conditional versus unconditional
br/bl is identical, but the ARM docs and existing ARM tools expect this
reloc type...
Added a few FIXME's for future naming fixups in ARMInstrInfo.td
llvm-svn: 124895
2011-02-04 19:47:15 +00:00
d4a5c05c97
Completed :lower16: / :upper16: support for movw / movt pairs on Darwin.
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- Fixed :upper16: fix up routine. It should be shifting down the top 16 bits first.
- Added support for Thumb2 :lower16: and :upper16: fix up.
- Added :upper16: and :lower16: relocation support to mach-o object writer.
llvm-svn: 123424
2011-01-14 02:38:49 +00:00
1455842275
Added clarifying comment
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llvm-svn: 123341
2011-01-12 23:25:02 +00:00
9c5b65d289
1. Support ELF pcrel relocations for movw/movt:
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R_ARM_MOVT_PREL and R_ARM_MOVW_PREL_NC.
2. Fix minor bug in ARMAsmPrinter - treat bitfield flag as a bitfield, not an enum.
3. Add support for 3 new elf section types (no-ops)
llvm-svn: 123294
2011-01-12 00:19:25 +00:00
9613a09e5c
Remove fixup_arm_thumb_ldst. The code was never calling the "fixup" stuff for
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it. I.e., it was always an immediate value.
llvm-svn: 121932
2010-12-16 00:50:33 +00:00
03e7576dee
Add fixups for Thumb LDR/STR instructions.
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llvm-svn: 121858
2010-12-15 08:51:02 +00:00
509dc2a700
Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755
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llvm-svn: 121798
2010-12-14 22:28:03 +00:00
6ea3053824
Fix comment.
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llvm-svn: 121797
2010-12-14 22:26:49 +00:00
d96bd53d04
trailing whitespace
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llvm-svn: 121792
2010-12-14 21:28:29 +00:00
6d375e5637
Second attempt at make Thumb2 LEAs pseudos. This time, perform the lowering much later, which makes the entire
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process cleaner.
llvm-svn: 121735
2010-12-14 00:36:49 +00:00
9a4d42855d
Revert r121721, which broke buildbots.
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llvm-svn: 121726
2010-12-13 22:51:08 +00:00
4efa445f3c
Make Thumb2 LEA-like instruction into pseudos, which map down to ADR. Provide correct fixups for Thumb2 ADR,
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which is _of course_ different from ARM ADR fixups, or any other Thumb2 fixup.
llvm-svn: 121721
2010-12-13 22:29:52 +00:00
578074b2f3
In Thumb2, direct branches can be encoded as either a "short" conditional branch with a null predicate, or
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as a "long" direct branch. While the mnemonics are the same, they encode the branch offset differently, and
the Darwin assembler appears to prefer the "long" form for direct branches. Thus, in the name of bitwise
equivalence, provide encoding and fixup support for it.
llvm-svn: 121710
2010-12-13 19:31:11 +00:00
e119da1146
Thumb unconditional branch binary encoding. rdar://8754994
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llvm-svn: 121496
2010-12-10 18:21:33 +00:00
78485ad65e
Thumb conditional branch binary encodings. rdar://8745367
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llvm-svn: 121493
2010-12-10 17:13:40 +00:00
68b27eb9d1
Rename CB/CBZ specific fixup accordingly.
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llvm-svn: 121404
2010-12-09 19:50:12 +00:00
3e6ee1db3e
Fix Thumb2 fixups for ldr.
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llvm-svn: 121350
2010-12-09 01:51:07 +00:00
3392bfc8f3
The BLX instruction is encoded differently than the BL, because why not? In
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particular, the immediate has 20-bits of value instead of 21. And bit 0 is '0'
always. Going through the BL fixup encoding was trashing the "bit 0 is '0'"
invariant.
Attempt to get the encoding at slightly more correct with this.
llvm-svn: 121336
2010-12-09 00:39:08 +00:00
302d5fd0d8
Fix Thumb2 BCC encoding and fixups.
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llvm-svn: 121329
2010-12-09 00:27:41 +00:00
a7d6aa902a
Support the "target" encodings for the CB[N]Z instructions.
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llvm-svn: 121308
2010-12-08 23:01:43 +00:00
8a6449c46e
Add support for loading from a constant pool.
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llvm-svn: 121226
2010-12-08 01:57:09 +00:00
0f7142d808
VLDR fixups need special handling under Thumb. While the encoding is the same,
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the order of the bytes in the data stream is flipped around.
llvm-svn: 121215
2010-12-08 00:18:36 +00:00
9e1994698d
Add fixup for Thumb1 BL/BLX instructions.
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llvm-svn: 121072
2010-12-06 23:57:07 +00:00
ce2bd8d05f
Add support for binary encoding of ARM 'adr' instructions referencing constant
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pool entries (LEApcrel pseudo). Ongoing saga of rdar://8542291.
llvm-svn: 120635
2010-12-02 00:28:45 +00:00
943fb60b1f
Add correct encodings for STRD and LDRD, including fixup support. Additionally, update these to unified syntax.
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llvm-svn: 120589
2010-12-01 19:18:46 +00:00
7f5b475852
10 bits, not 12.
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llvm-svn: 120584
2010-12-01 18:51:32 +00:00
5a97bd873e
Fix .o emission of ARM movt/movw. MCSymbolRefExpr::VK_ARM_(HI||LO)16 for the .o path now works for ARM.
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Note: lo16AllZero remains in ARMInstrInfo.td - It can be factored out when Thumb movt is repaired.
Existing tests cover this update.
llvm-svn: 119760
2010-11-18 23:37:15 +00:00
9d6d77a9f4
Encoding of destination fixup for ARM branch and conditional branch
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instructions.
llvm-svn: 118801
2010-11-11 18:04:49 +00:00
0fb841fd19
Add ARM fixup info for load/store label references. Probably will need a bit of
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tweaking when we start using it for object file emission or JIT, but it's a
start.
llvm-svn: 118221
2010-11-04 01:12:30 +00:00
Jason W Kim