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93 Commits

Author SHA1 Message Date
Chris Lattner 1ea55cf816 This commit changes: 
1. Legalize now always promotes truncstore of i1 to i8. 
2. Remove patterns and gunk related to truncstore i1 from targets.
3. Rename the StoreXAction stuff to TruncStoreAction in TLI.
4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions.
5. Mark a wide variety of invalid truncstores as such in various targets, e.g.
   X86 currently doesn't support truncstore of any of its integer types.
6. Add legalize support for truncstores with invalid value input types.
7. Add a dag combine transform to turn store(truncate) into truncstore when
   safe.

The later allows us to compile CodeGen/X86/storetrunc-fp.ll to:

_foo:
	fldt	20(%esp)
	fldt	4(%esp)
	faddp	%st(1)
	movl	36(%esp), %eax
	fstps	(%eax)
	ret

instead of:

_foo:
	subl	$4, %esp
	fldt	24(%esp)
	fldt	8(%esp)
	faddp	%st(1)
	fstps	(%esp)
	movl	40(%esp), %eax
	movss	(%esp), %xmm0
	movss	%xmm0, (%eax)
	addl	$4, %esp
	ret

llvm-svn: 46140
 2008-01-17 19:59:44 +00:00
Chris Lattner 9a249b0ce5 rename SDTRet -> SDTNone. 
Move definition of 'trap' sdnode up from x86 instrinfo to targetselectiondag.td.

llvm-svn: 46017
 2008-01-15 22:02:54 +00:00
Chris Lattner 520d4adad3 add SDNPSideEffect node property declaration 
llvm-svn: 45825
 2008-01-10 05:48:23 +00:00
Chris Lattner c72335878d add SDNPMayLoad to the 'load' sdnode definition. This is enough to get all the x86 
instructions (with patterns) that load memory marked, for example.

llvm-svn: 45818
 2008-01-10 04:44:32 +00:00
Chris Lattner 10324d0175 rename isStore -> mayStore to more accurately reflect what it captures. 
llvm-svn: 45656
 2008-01-06 08:36:04 +00:00
Chris Lattner a348f55ec6 Change the 'isStore' inferrer to look for 'SDNPMayStore' 
instead of "ISD::STORE".  This allows us to mark target-specific dag
nodes as storing (such as ppc byteswap stores).  This allows us to remove
more explicit isStore flags from the .td files.

Finally, add a warning for when a .td file contains an explicit 
isStore and tblgen is able to infer it.

llvm-svn: 45654
 2008-01-06 06:44:58 +00:00
Chris Lattner f3ebc3f3d2 Remove attribution from file headers, per discussion on llvmdev. 
llvm-svn: 45418
 2007-12-29 20:36:04 +00:00
Chris Lattner 6a49593aa5 add a immAllZerosV_bc pattern fragment for consistency with others. 
llvm-svn: 44303
 2007-11-24 19:02:07 +00:00
Bill Wendling 77b13af9a6 Unifacalize the CALLSEQ{START,END} stuff. 
llvm-svn: 44045
 2007-11-13 09:19:02 +00:00
Evan Cheng 43686dad3d Rename keyword "modify" -> "implicit". 
llvm-svn: 42282
 2007-09-25 01:48:59 +00:00
Evan Cheng 59c39dc197 Initial support for multi-result patterns: 
1.
[(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
 (modify EFLAGS)]
This indicates the source pattern expects the instruction would produce 2 values. The first is the result of the addition. The second is an implicit definition in register EFLAGS.
2.
def : Pat<(parallel (addc GR32:$src1, GR32:$src2), (modify EFLAGS)), ()>
Similar to #1 except this is used for def : Pat patterns.

llvm-svn: 41897
 2007-09-12 23:30:14 +00:00
Dale Johannesen b1888e73ad Long double patch 4 of N: initial x87 implementation. 
Lots of problems yet but some simple things work.

llvm-svn: 40847
 2007-08-05 18:49:15 +00:00
Christopher Lamb a8fc0e527b Add selection DAG nodes for subreg insert/extract. PR1350 
llvm-svn: 40516
 2007-07-26 07:34:40 +00:00
Dan Gohman 06c60b6032 Fix comments about vectors to use the current wording. 
llvm-svn: 39921
 2007-07-16 14:29:03 +00:00
Lauro Ramos Venancio 2518889872 Implement "general dynamic", "initial exec" and "local exec" TLS models for 
X86 32 bits.

llvm-svn: 36283
 2007-04-20 21:38:10 +00:00
Jim Laskey f9e5445ed4 Make LABEL a builtin opcode. 
llvm-svn: 33537
 2007-01-26 14:34:52 +00:00
Chris Lattner 58e8bed48e Fix predicates for unindexed stores so they don't accidentally match indexed 
stores.

llvm-svn: 31735
 2006-11-14 19:13:39 +00:00
Evan Cheng c034f14fbe Rename ISD::MemOpAddrMode to ISD::MemIndexedMode 
llvm-svn: 31596
 2006-11-09 18:44:21 +00:00
Evan Cheng c9a4cdc9c9 Added indexed store node and patfrag's. 
llvm-svn: 31576
 2006-11-08 23:02:11 +00:00
Evan Cheng f53ae69365 Change load PatFrag to ignore indexed load. 
llvm-svn: 31210
 2006-10-26 21:55:50 +00:00
Evan Cheng ab51cf2e78 Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode. 
llvm-svn: 30945
 2006-10-13 21:14:26 +00:00
Evan Cheng 577ef7694e Add properties to ComplexPattern. 
llvm-svn: 30891
 2006-10-11 21:03:53 +00:00
Evan Cheng d35734bd1f Naming consistency. 
llvm-svn: 30878
 2006-10-11 07:10:22 +00:00
Evan Cheng e71fe34d75 Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes. 
llvm-svn: 30844
 2006-10-09 20:57:25 +00:00
Evan Cheng 5d9fd977d3 Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an 
extra operand to LOADX to specify the exact value extension type.

llvm-svn: 30714
 2006-10-04 00:56:09 +00:00
Evan Cheng 66f0e09313 Vector extract / insert index operand should have ptr type. 
llvm-svn: 28798
 2006-06-15 08:19:05 +00:00
Nate Begeman 4ca2ea5b43 JumpTable support! What this represents is working asm and jit support for 
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.

llvm-svn: 27947
 2006-04-22 18:53:45 +00:00
Evan Cheng 52df74000a Renamed AddedCost to AddedComplexity. 
llvm-svn: 27843
 2006-04-19 20:38:28 +00:00
Evan Cheng aa3325e925 Allow "let AddedCost = n in" to increase pattern complexity. 
llvm-svn: 27834
 2006-04-19 18:07:24 +00:00
Chris Lattner 41df12ff4c Add a new vnot_conv predicate for matching vnot's where the allones vector is 
bitconverted from some other type.

llvm-svn: 27724
 2006-04-15 23:39:14 +00:00
Evan Cheng 3296f297d5 Add vector_extract and vector_insert nodes. 
llvm-svn: 27303
 2006-03-31 19:21:16 +00:00
Chris Lattner e55d171ccd Tblgen doesn't like multiple SDNode<> definitions that map to the sameenum value. Split them into separate enums. 
llvm-svn: 27201
 2006-03-28 00:40:33 +00:00
Evan Cheng a74792fa9d Changed isBuildVectorAllOnesInteger to isBuildVectorAllOnes. 
llvm-svn: 27166
 2006-03-27 06:59:32 +00:00
Evan Cheng 5562f2092f Add immAllZerosV helper 
llvm-svn: 27148
 2006-03-26 09:51:39 +00:00
Chris Lattner 3de9286e09 add a vnot helper node for matching 'not' on vectors 
llvm-svn: 27132
 2006-03-25 23:00:08 +00:00
Chris Lattner 9dc2d17ae6 Add new intrinsic node definitions for tblgen use 
llvm-svn: 27100
 2006-03-25 02:29:35 +00:00
Chris Lattner c6b13e21cc Shuffle some includes around 
llvm-svn: 27073
 2006-03-24 18:52:35 +00:00
Chris Lattner 58a9622957 expose intrinsic info to the targets. 
llvm-svn: 27070
 2006-03-24 18:44:11 +00:00
Evan Cheng e4d1416239 x86 ISD::SCALAR_TO_VECTOR support. 
llvm-svn: 26911
 2006-03-21 00:33:35 +00:00
Chris Lattner 80b6bd2746 Add a build_vector node 
llvm-svn: 26895
 2006-03-20 06:18:01 +00:00
Chris Lattner e4e1ac37ba add vector_shuffle 
llvm-svn: 26891
 2006-03-20 05:40:45 +00:00
Chris Lattner 4b41e40621 add support for the bitconvert node 
llvm-svn: 26789
 2006-03-16 01:29:53 +00:00
Andrew Lenharth ebfd94fa1d relax fcopysign 
llvm-svn: 26649
 2006-03-09 17:47:22 +00:00
Andrew Lenharth b8a06a7c6c fcopysign support 
llvm-svn: 26640
 2006-03-09 14:57:36 +00:00
Chris Lattner ad3c974a77 remove the read/write port/io intrinsics. 
llvm-svn: 26479
 2006-03-03 00:19:58 +00:00
Nate Begeman 5965bd19f8 kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC 
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.

llvm-svn: 26255
 2006-02-17 05:43:56 +00:00
Nate Begeman 3920ce4d8d Whoops, didn't mean to check this in yet. 
llvm-svn: 26250
 2006-02-17 00:56:19 +00:00
Nate Begeman 4a0dc0c8f6 Add a missing and useful pat frag 
llvm-svn: 26249
 2006-02-17 00:51:06 +00:00
Chris Lattner 61c9a8e942 Targets all now request ConstantFP to be legalized into TargetConstantFP. 
'fpimm' in .td files is now TargetConstantFP.

llvm-svn: 25771
 2006-01-29 06:26:08 +00:00
Nate Begeman 2fba8a3aaa bswap implementation 
llvm-svn: 25312
 2006-01-14 03:14:10 +00:00