Commit Graph

13685 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes a8e3673816 Add v4f64 -> v2f32 fp_round support. Also add a testcase to exercise
the legalizer. This commit together with the two previous ones fixes
PR10495.

llvm-svn: 136654
2011-08-01 21:54:09 +00:00
Bruno Cardoso Lopes 7513939ddd Since vectors with all ones can't be created with a 256-bit instruction,
avoid returning early for v8i32 types, which would only be valid for
vector with all zeros. Also split the handling of zeros and ones into separate
checking logic since they are handled differently. This fixes PR10547

llvm-svn: 136642
2011-08-01 19:51:53 +00:00
Richard Osborne 0cc000ef29 Fix crash with varargs function with no named parameters.
llvm-svn: 136623
2011-08-01 16:45:59 +00:00
Rafael Espindola a3a44f3fc3 Add a small gep optimization I noticed was missing while reading some IL.
llvm-svn: 136585
2011-07-31 04:43:41 +00:00
Benjamin Kramer 99d53ff456 Remove InvalidateStructLayoutInfo from the ocaml bindings.
llvm-svn: 136582
2011-07-31 01:12:39 +00:00
Bill Wendling ad088e6724 Revert r136253, r136263, r136269, r136313, r136325, r136326, r136329, r136338,
r136339, r136341, r136369, r136387, r136392, r136396, r136429, r136430, r136444,
r136445, r136446, r136253 pending review.

llvm-svn: 136556
2011-07-30 05:42:50 +00:00
Jakob Stoklund Olesen 5670f850c6 Revert "Don't check liveness of unallocatable registers."
The ARM target depends on CPSR liveness being tracked after register
allocation.

llvm-svn: 136548
2011-07-30 00:57:25 +00:00
Jakob Stoklund Olesen 95cc5440e9 Don't check liveness of unallocatable registers.
This includes registers like EFLAGS and ST0-ST7. We don't check for
liveness issues in the verifier and scavenger because registers will
never be allocated from these classes.

While in SSA form, we do care about the liveness of unallocatable
unreserved registers. Liveness of EFLAGS and ST0 neds to be correct for
MachineDCE and MachineSinking.

llvm-svn: 136541
2011-07-29 23:36:21 +00:00
Eric Christopher aa5030066f Add support for the 'Q' constraint.
Fixes rdar://9866494

llvm-svn: 136523
2011-07-29 21:18:58 +00:00
Jim Grosbach 51726e2147 ARM SRS instruction parsing, diassembly and encoding support.
Fix the instruction encoding for operands. Refactor mode to use explicit
instruction definitions per FIXME to be more consistent with loads/stores.
Fix disassembler accordingly. Add tests.

llvm-svn: 136509
2011-07-29 20:26:09 +00:00
Devang Patel 3e02522fee Clean up debug info after reassociation.
llvm-svn: 136480
2011-07-29 19:00:35 +00:00
Jim Grosbach c4dc52cd52 ARM assembly parsing and encoding for RFE instruction.
Fill in the missing fixed bits and the register operand bits of the instruction
encoding. Refactor the definition to make the mode explicit, which is
consistent with how loads and stores are normally represented and makes
parsing much easier. Add parsing aliases for pseudo-instruction variants.
Update the disassembler for the new representations. Add tests for parsing and
encoding.

llvm-svn: 136479
2011-07-29 18:47:24 +00:00
Jim Grosbach 1c1d2438aa ARM update tests for CPS instruction.
llvm-svn: 136472
2011-07-29 17:39:27 +00:00
Bruno Cardoso Lopes 65ce5ea3ba Fix two tests that I crashed in the previous commits. The mask elts
on the second half must be reindexed.

llvm-svn: 136454
2011-07-29 02:05:28 +00:00
Bruno Cardoso Lopes 81eb193f2e Match VPERMIL masks more strictly and update the target specific mask
generation to always catch the weird cases.

llvm-svn: 136453
2011-07-29 01:31:15 +00:00
Bruno Cardoso Lopes d23709b18c Add v8i32 and v4i64 vpermil patterns
llvm-svn: 136451
2011-07-29 01:31:07 +00:00
Jakob Stoklund Olesen b28ee4115d Transfer implicit operands in NEONMoveFixPass.
Later passes /are/ using this information when running the register
scavenger.

This fixes the second problem in PR10520.

llvm-svn: 136440
2011-07-29 00:27:35 +00:00
Jakob Stoklund Olesen 9c3badceba Add -verify-arm-pseudo-expand.
This hidden llc option runs the machine code verifier after expanding
ARM pseudo-instructions, but before if-conversion.

The machine code verifier is much better at pointing out liveness errors
that can trip up the register scavenger.

llvm-svn: 136439
2011-07-29 00:27:32 +00:00
Eli Friedman 530341d748 Make sure to correctly clear the exact/nuw/nsw flags off of shifts when they are combined together. <rdar://problem/9859829>
llvm-svn: 136435
2011-07-29 00:18:19 +00:00
Jim Grosbach b9bebc1b03 CBZ/CBNZ are Thumb2 only. No need for ARM mode tests for them.
llvm-svn: 136408
2011-07-28 21:59:38 +00:00
Jim Grosbach a03ab0e3dc ARM assembly parsing and encoding for BLX (immediate).
Add parsing support for BLX (immediate). Since the register operand version is
predicated and the label operand version is not, we have to use some special
handling to get the operand list right for matching.

llvm-svn: 136406
2011-07-28 21:57:55 +00:00
Jakob Stoklund Olesen b16081ce8c Handle REG_SEQUENCE with implicitly defined operands.
Code like that would only be produced by bugpoint, but we should still
handle it correctly.

When a register is defined by a REG_SEQUENCE of undefs, the register
itself is undef. Previously, we would create a register with uses but no
defs.

Fixes part of PR10520.

llvm-svn: 136401
2011-07-28 21:38:51 +00:00
Jim Grosbach 7f45559e86 Remove obsolete FIXME reference in comment.
llvm-svn: 136400
2011-07-28 21:37:05 +00:00
Jim Grosbach 864b609491 ARM assembly parsing and encoding for BFC and BFI.
Add parsing support that handles converting the lsb+width source into the
odd way we represent the instruction (an inverted bitfield mask).

llvm-svn: 136399
2011-07-28 21:34:26 +00:00
Jim Grosbach 8b3184e540 ARM parsing and encoding for ADR.
The label does not have a '#' prefix. Add parsing and encoding tests.

llvm-svn: 136360
2011-07-28 16:33:54 +00:00
Jim Grosbach 4356636fc0 Update ARM tests for parsing and encoding of WFE, WFI and YIELD.
llvm-svn: 136358
2011-07-28 16:00:41 +00:00
Duncan Sands 483354758f Due to changes coming from the new LLVM type system, you now get
bitcasts in this test rather than getelementptr instructions;
llvm-gcc produces two bitcasts, clang produces one.

llvm-svn: 136349
2011-07-28 12:21:47 +00:00
Bruno Cardoso Lopes 76bc28bac6 Add patterns to generate copies for extract_subvector instead of
using vextractf128. This will reduce the number of issued instruction
for several avx codes.

llvm-svn: 136323
2011-07-28 01:26:50 +00:00
Bruno Cardoso Lopes eca99c4b5a Add a few patterns to match allzeros without having to use the fp unit.
Take advantage that the 128-bit vpxor zeros the higher part and use it.
This also fixes PR10491

llvm-svn: 136321
2011-07-28 01:26:43 +00:00
Bruno Cardoso Lopes 9e2a301216 Add SINT_TO_FP and FP_TO_SINT support for v8i32 types. Also move
a convert pattern close to the instruction definition.

llvm-svn: 136320
2011-07-28 01:26:39 +00:00
Jim Grosbach 4059137f56 ARM parsing and encoding tests.
UXTAB, UXTAB16, UXTAH, UXTB, UXTB16, and UXTH.

llvm-svn: 136312
2011-07-28 00:37:03 +00:00
Evan Cheng eda1d4f3ba Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil.
This can happen in cases where TableGen generated asm matcher cannot check
whether a register operand is in the right register class. e.g. mem operands.

rdar://8204588

llvm-svn: 136292
2011-07-27 23:22:03 +00:00
Jim Grosbach e37f7dc349 ARM assembly parsing and encoding for USUB16 and USUB8.
llvm-svn: 136289
2011-07-27 23:10:05 +00:00
Jim Grosbach 05f80d3add ARM assembly parsing and encoding for USAX.
llvm-svn: 136288
2011-07-27 23:07:00 +00:00
Kevin Enderby 5ef6c453a6 Fix llvm-mc handing of x86 instructions that take 8-bit unsigned immediates.
llvm-mc gives an "invalid operand" error for instructions that take an unsigned
immediate which have the high bit set such as:
    pblendw $0xc5, %xmm2, %xmm1
llvm-mc treats all x86 immediates as signed values and range checks them.
A small number of x86 instructions use the imm8 field as a set of bits.
This change only changes those instructions and where the high bit is not
ignored.  The others remain unchanged.

llvm-svn: 136287
2011-07-27 23:01:50 +00:00
Jim Grosbach 16dd4adcbe Clean up tabs.
llvm-svn: 136286
2011-07-27 22:35:06 +00:00
Jim Grosbach 57e2d3cb84 ARM assembly parsing and encoding support for USAT and USAT16.
Use range checked immediate operands for instructions. Add tests.

llvm-svn: 136285
2011-07-27 22:34:17 +00:00
Jim Grosbach fea7a44a9b ARM assembly parsing and encoding tests for USAD8 and USADA8.
llvm-svn: 136284
2011-07-27 22:23:02 +00:00
Jim Grosbach 1644409b47 ARM assembly parsing and encoding tests for UQSUB16 and UQSUB8.
llvm-svn: 136282
2011-07-27 22:13:08 +00:00
Jim Grosbach 1a3ddffc1c Fix comment copy/paste-o.
llvm-svn: 136281
2011-07-27 22:11:41 +00:00
Jim Grosbach 84ecab228a ARM assembly parsing and encoding tests for UQASX and UQSAX.
llvm-svn: 136280
2011-07-27 22:09:30 +00:00
Jim Grosbach 928f4175c0 ARM assembly parsing and encoding tests for UQADD16 and UQADD8.
llvm-svn: 136279
2011-07-27 22:08:14 +00:00
Jim Grosbach 39b062bfaa ARM assembly parsing and encoding for UMULL.
Fix parsing of the 's' suffix for the mnemonic. Add tests.

llvm-svn: 136277
2011-07-27 22:01:42 +00:00
Jim Grosbach 0c398b9c7e ARM assembly parsing and encoding for UMLAL.
Fix parsing of the 's' suffix for the mnemonic. Add tests.

llvm-svn: 136274
2011-07-27 21:58:11 +00:00
Jim Grosbach 121c21aba9 ARM assembly parsing and encoding tests for UMAAL.
llvm-svn: 136272
2011-07-27 21:53:42 +00:00
Jim Grosbach 7cfd32a006 ARM assembly parsing and encoding tests for UHSUB16 and UHSUB8.
llvm-svn: 136267
2011-07-27 21:21:59 +00:00
Jim Grosbach 3f45383ef5 ARM assembly parsing and encoding tests for UHADD16, UHADD8 and UHASX.
llvm-svn: 136266
2011-07-27 21:20:45 +00:00
Jim Grosbach 03f56d9de6 ARM parsing and encoding of SBFX and UBFX.
Encode the width operand as it encodes in the instruction, which simplifies
the disassembler and the encoder, by using the imm1_32 operand def. Add a
diagnostic for the context-sensitive constraint that the width must be in
the range [1,32-lsb].

llvm-svn: 136264
2011-07-27 21:09:25 +00:00
Jim Grosbach 36ce7492a6 ARM assembly parsing and encoding tests for UADD16, UADD8 and UASX.
llvm-svn: 136261
2011-07-27 20:43:44 +00:00
Jim Grosbach 542333ea05 ARM assembly parsing and encoding tests for TST instruction.
llvm-svn: 136260
2011-07-27 20:38:58 +00:00