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5 Commits

Author SHA1 Message Date
Simon Pilgrim d7518896ff [X86][SSE] Fix domains for VZEXT_LOAD type instructions 
Add the missing domain equivalences for movss, movsd, movd and movq zero extending loading instructions.

Differential Revision: https://reviews.llvm.org/D27684

llvm-svn: 289825
 2016-12-15 16:05:29 +00:00
Simon Pilgrim 41e31ff6bd [X86][SSE] Regenerated the vec_set tests. 
Replaced lots of dodgy greps with actual codegen

llvm-svn: 265163
 2016-04-01 17:40:25 +00:00
Michael Liao bc793a775e More rewrites of x86 codegen regression tests with FileCheck 
llvm-svn: 180837
 2013-05-01 05:34:30 +00:00
Dan Gohman 40503396da Eliminate more uses of llvm-as and llvm-dis. 
llvm-svn: 81290
 2009-09-08 23:54:48 +00:00
Evan Cheng 78af38c392 Handle vector move / load which zero the destination register top bits (i.e. movd, movq, movss (addr), movsd (addr)) with X86 specific dag combine. 
llvm-svn: 50838
 2008-05-08 00:57:18 +00:00