7ac602bc8e
Whitespace cleanup in ARM fast isel.
...
llvm-svn: 116197
2010-10-11 08:38:55 +00:00
eae1b38550
Add srem libcall support to ARM fast isel.
...
llvm-svn: 116196
2010-10-11 08:37:26 +00:00
e11017c19e
Add i8 sdiv support for ARM fast isel.
...
llvm-svn: 116195
2010-10-11 08:31:54 +00:00
511aa31965
Implement select handling for ARM fast-isel.
...
llvm-svn: 116194
2010-10-11 08:27:59 +00:00
1ef5e84c31
Per discussion with Sanjiv, remove the PIC16 target from mainline. When/if
...
it comes back, it will be largely a rewrite, so keeping the old codebase
in tree isn't helping anyone.
llvm-svn: 116190
2010-10-11 05:44:40 +00:00
8dedb62019
X86: Call ulldiv and ftol2 on Windows instead of their libgcc eqivilents.
...
llvm-svn: 116188
2010-10-11 05:29:15 +00:00
00765e5be0
X86: MinGW should always use libgcc on Windows.
...
llvm-svn: 116177
2010-10-10 23:11:06 +00:00
7a573a5e1f
X86: Call _alldiv instead of __divdi3 on Windows (excluding cygwin).
...
llvm-svn: 116174
2010-10-10 22:04:34 +00:00
bee1f7f5ba
Fix Whitespace.
...
llvm-svn: 116173
2010-10-10 22:04:20 +00:00
d10babfd65
fix the expansion of va_arg instruction on PPC to know the arg
...
alignment for PPC32/64, avoiding some masking operations.
llvm-gcc expands vaarg inline instead of using the instruction
so it has never hit this.
llvm-svn: 116168
2010-10-10 18:34:00 +00:00
530ce85b3e
Fix Whitespace.
...
llvm-svn: 116149
2010-10-09 11:00:50 +00:00
d7a404d85f
Add VLD4 scheduling itineraries.
...
llvm-svn: 116143
2010-10-09 04:07:58 +00:00
a762400bed
Finish vld3 and vld4.
...
llvm-svn: 116140
2010-10-09 01:45:34 +00:00
4187f4942e
Complete vld2 instruction itineries.
...
llvm-svn: 116136
2010-10-09 01:26:12 +00:00
1c7fa43e6f
Multiply instructions are issued on pipeline 0. They do not need to reserve pipeline 1.
...
llvm-svn: 116135
2010-10-09 01:15:04 +00:00
05f13e94bf
Correct some load / store instruction itinerary mistakes:
...
1. Cortex-A8 load / store multiplies can only issue on ALU0.
2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues.
3. Correctly model all vld1 and vld2 variants.
llvm-svn: 116134
2010-10-09 01:03:04 +00:00
59ebe44049
Check to make sure that the iterator isn't at the beginning of the basic block
...
before decrementing. <rdar://problem/8529919>
llvm-svn: 116126
2010-10-09 00:03:48 +00:00
c951cfe6a0
add jit support for the new psuedo instructions I added for
...
the add/or xform. The JIT isn't mcized yet, boo.
This fixes Olden/voronoi, bh and a ton of other stuff that
uses the jit.
llvm-svn: 116125
2010-10-08 23:59:27 +00:00
8eeb5013cd
machine a mutable machineinstr down into emitInstruction.
...
llvm-svn: 116124
2010-10-08 23:54:01 +00:00
548587c31c
Fix the store part of this as well. Fixes smg2000.
...
llvm-svn: 116123
2010-10-08 23:52:16 +00:00
c43c930690
Implement a few more binary encoding bits. Still very early stage proof-of-
...
concept level stuff at this point, but it is generally working for those
instructions that know how to map the operands.
This patch fills in the register operands for add/sub/or/etc instructions
and adds the conditional execution predicate encoding.
llvm-svn: 116112
2010-10-08 21:45:55 +00:00
d57f9ecd4a
Recommit 116056, now with the missing file...
...
llvm-svn: 116083
2010-10-08 19:24:18 +00:00
b770c00610
Reapply 116059, this time without the fatfingered pasto at the top.
...
''const'ify getMachineOpValue() and associated helpers.'
llvm-svn: 116067
2010-10-08 17:45:54 +00:00
00351b7731
Reverting 116059. Bots are unhappy with it.
...
llvm-svn: 116064
2010-10-08 17:28:40 +00:00
cf97db2402
reverting 116056: win64_params.ll may need to be conditionalized?
...
llvm-svn: 116063
2010-10-08 17:22:42 +00:00
e2d30cd4b5
'const'ify getMachineOpValue() and associated helpers.
...
llvm-svn: 116059
2010-10-08 16:52:44 +00:00
a07b5c291d
Small patch to restore home register stack space allocation for the Win64 case. Add test case. This code eventually needs to be tighter, since it's always allocating it, even in leaf routines.
...
llvm-svn: 116056
2010-10-08 10:31:30 +00:00
056b694de1
Change register allocation order for ARM VFP and NEON registers to put the
...
callee-saved registers at the end of the lists. Also prefer to avoid using
the low registers that are in register subclasses required by certain
instructions, so that those registers will more likely be available when needed.
This change makes a huge improvement in spilling in some cases. Thanks to
Jakob for helping me realize the problem.
Most of this patch is fixing the testsuite. There are quite a few places
where we're checking for specific registers. I changed those to wildcards
in places where that doesn't weaken the tests. The spill-q.ll and
thumb2-spill-q.ll tests stopped spilling with this change, so I added a bunch
of live values to force spills on those tests.
llvm-svn: 116055
2010-10-08 06:15:13 +00:00
35e6ce479c
fix a subtle bug I introduced in my refactoring, where we stopped preferring
...
the i8 versions of instructions in some cases. In test6, we started
generating:
cmpq $0, -8(%rsp) ## encoding: [0x48,0x81,0x7c,0x24,0xf8,0x00,0x00,0x00,0x00]
## <MCInst #478 CMP64mi32
## <MCOperand Reg:114>
## <MCOperand Imm:1>
## <MCOperand Reg:0>
## <MCOperand Imm:-8>
## <MCOperand Reg:0>
## <MCOperand Imm:0>>
instead of:
cmpq $0, -8(%rsp) ## encoding: [0x48,0x83,0x7c,0x24,0xf8,0x00]
## <MCInst #479 CMP64mi8
## <MCOperand Reg:114>
## <MCOperand Imm:1>
## <MCOperand Reg:0>
## <MCOperand Imm:-8>
## <MCOperand Reg:0>
## <MCOperand Imm:0>>
Fix this and add some comments.
llvm-svn: 116053
2010-10-08 05:12:14 +00:00
dd77477690
reapply: Use the new TB_NOT_REVERSABLE flag instead of special
...
reapply: reimplement the second half of the or/add optimization. We should now
with no changes. Turns out that one missing "Defs = [EFLAGS]" can upset things
a bit.
llvm-svn: 116040
2010-10-08 03:57:25 +00:00
626656a562
reapply the patch reverted in r116033:
...
"Reimplement (part of) the or -> add optimization. Matching 'or' into 'add'"
With a critical fix: the add pseudos clobber EFLAGS.
llvm-svn: 116039
2010-10-08 03:54:52 +00:00
8f21f9c1fb
Revert "Reimplement (part of) the or -> add optimization. Matching 'or' into
...
'add'", which seems to have broken just about everything.
llvm-svn: 116033
2010-10-08 02:07:32 +00:00
5b2a411c77
Revert "Use the new TB_NOT_REVERSABLE flag instead of special ", which depends
...
on r116007, which I am about to revert.
llvm-svn: 116032
2010-10-08 02:07:29 +00:00
efdf08b5b8
Revert "reimplement the second half of the or/add optimization. We should now",
...
which depends on r116007, which I am about to revert.
llvm-svn: 116031
2010-10-08 02:07:26 +00:00
15bc2438d9
Move to thumb2 loads, fixes a problem with incoming registers
...
as thumb1.
Fixes lencod.
llvm-svn: 116027
2010-10-08 01:13:17 +00:00
134f415bf8
reimplement the second half of the or/add optimization. We should now
...
only end up emitting LEA instead of OR. If we aren't able to promote
something into an LEA, we should never be emitting it as an ADD.
Add some testcases that we emit "or" in cases where we used to produce
an "add".
llvm-svn: 116026
2010-10-08 01:05:10 +00:00
0bb2f9afa9
Enable binary encoding of some simple instructions.
...
llvm-svn: 116022
2010-10-08 00:39:21 +00:00
a7b6d58f45
Make <target>CodeEmitter::getBinaryCodeForInstr() a const method.
...
llvm-svn: 116018
2010-10-08 00:21:28 +00:00
e2245542ce
Use the new TB_NOT_REVERSABLE flag instead of special
...
casing FsMOVAPDrr/FsMOVAPSrr.
llvm-svn: 116016
2010-10-08 00:03:02 +00:00
0921bfdf36
simplify some map operations.
...
llvm-svn: 116014
2010-10-07 23:57:02 +00:00
4fb38d3cd3
Reimplement (part of) the or -> add optimization. Matching 'or' into 'add'
...
is general goodness because it allows ORs to be converted to LEA to avoid
inserting copies. However, this is bad because it makes the generated .s
file less obvious and gives valgrind heartburn (tons of false positives in
bitfield code).
While the general fix should be in valgrind, we can at least try to avoid
emitting ADD instructions that *don't* get promoted to LEA. This is more
work because it requires introducing pseudo instructions to represents
"add that knows the bits are disjoint", but hey, people really love valgrind.
This fixes this testcase:
https://bugs.kde.org/show_bug.cgi?id=242137#c20
the add r/i cases are coming next.
llvm-svn: 116007
2010-10-07 23:36:18 +00:00
412e37bd34
Code refactoring.
...
llvm-svn: 116002
2010-10-07 23:12:15 +00:00
1c090c00bc
Reduce casting in various tables by defining the table
...
with the right types.
llvm-svn: 116001
2010-10-07 23:08:41 +00:00
70a7b54f97
simplify code: don't build up vector only to assert it is empty.
...
llvm-svn: 115997
2010-10-07 22:26:19 +00:00
df7a4f2515
Now with fewer extraneous semicolons!
...
llvm-svn: 115996
2010-10-07 22:25:06 +00:00
91029094e0
Trivial MC code emitter shell. No instruction forms actually handled yet.
...
llvm-svn: 115993
2010-10-07 22:12:50 +00:00
8aed386d82
Include the auto-generated bits for machine encoding.
...
llvm-svn: 115987
2010-10-07 21:57:55 +00:00
3e1e447ca2
Remember to promote load/store types for stack to register size.
...
llvm-svn: 115984
2010-10-07 21:40:18 +00:00
f5c60d8156
convert test to use the existing classes that the multipatterns
...
use. Since TEST is completely different than all other binops,
don't define a multipattern for it.
This completes factorization of binops.
llvm-svn: 115982
2010-10-07 21:31:03 +00:00
ae8d67d3bb
convert cmp to use a multipattern
...
llvm-svn: 115978
2010-10-07 20:56:25 +00:00
5c31bf0619
Canonicalize X86ISD::MOVDDUP nodes to v2f64 to make sure all cases match. Also eliminate unneeded isel patterns. rdar://8520311
...
llvm-svn: 115977
2010-10-07 20:50:20 +00:00
07b5b1802e
ARM instruction don't have instruction prefixes, so remove the helper functions
...
for them from the MCCodeEmitter.
llvm-svn: 115975
2010-10-07 20:41:30 +00:00
a8c0bbb869
reduce redundancy between pattern copies.
...
llvm-svn: 115968
2010-10-07 20:14:23 +00:00
9fece2bea2
the opcode for BinOpMI/BinOpMI8 is always the same, remove the argument.
...
llvm-svn: 115967
2010-10-07 20:06:24 +00:00
546c11c72f
Improve comment.
...
llvm-svn: 115966
2010-10-07 20:05:18 +00:00
752b60bc01
convert adc/sbb to a multipattern. Because the adde/sube nodes
...
are not defined as returning EFLAGS (like add_flag and friends),
the entire multipattern and several of the subclasses need to be
cloned.
This could be handled through better instantiation support in tblgen,
but it isn't meta enough.
llvm-svn: 115964
2010-10-07 20:01:55 +00:00
e9d5d0736c
Add initialization routines for Target.
...
llvm-svn: 115957
2010-10-07 18:50:11 +00:00
c6a6e9ba7c
Fix obvious mistake pointed out by Michael Spencer.
...
llvm-svn: 115952
2010-10-07 18:47:10 +00:00
ac1ffa27b6
Add the missing cases to the type->registerclass conversion function.
...
llvm-svn: 115921
2010-10-07 16:32:42 +00:00
a845022ddd
Implement two virtual functions in SPUTargetLowering.
...
Before the implementation of isLegalAddressingMode, some rare cases
of code were miscompiled if optimized with the LoopStrengthReduce pass.
It is unclear (to me) if LSR is "allowed" to produce wrong code with a
bad TargetLowering, or if the bug is elsewhere and this patch just
hides it.
llvm-svn: 115919
2010-10-07 16:24:35 +00:00
a2583ea9f2
Use the correct register class for load instructions - fixes
...
compilation of MultiSource/Benchmarks/Bullet.
llvm-svn: 115907
2010-10-07 05:50:44 +00:00
76a9752d45
Use the correct register class here.
...
llvm-svn: 115906
2010-10-07 05:39:19 +00:00
a98be90efe
Use the thumb2 conditional move instruction.
...
llvm-svn: 115905
2010-10-07 05:31:49 +00:00
6d74673366
Remove in-progress assertion, add TODO.
...
llvm-svn: 115904
2010-10-07 05:14:08 +00:00
1958cefd69
Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vldr / vstr, etc.
...
llvm-svn: 115898
2010-10-07 01:50:48 +00:00
67677515ac
add support for isConvertibleToThreeAddress to ArithBinOpEFLAGS,
...
allowing us to convert ADD over. deletes 160 lines of .td file.
llvm-svn: 115897
2010-10-07 01:37:01 +00:00
4fc52f6fa0
Fix a few issues in ArithBinOpEFLAGS that made it specific to and.
...
Start using ArithBinOpEFLAGS for OR, XOR, and SUB.
This removes 500 lines from the .td file. Now AND/OR/XOR/SUB are all
defined exactly the same way instead of being close relatives.
llvm-svn: 115896
2010-10-07 01:26:27 +00:00
26d6a0449a
Convert 'and' to single instance of a multipattern
...
which instantiates the 34 versions of and all in one
swoop. The BaseOpc/BaseOpc2/BaseOpc4 stuff should not
be required, but tblgen's feeble brain explodes when I
use Or4<BaseOpc>.V in the multipattern.
No change in the generated .inc files.
llvm-svn: 115893
2010-10-07 01:10:20 +00:00
5b255c2dd6
Allow use of the 16-bit literal move instruction in CMOVs for Thumb2 mode.
...
llvm-svn: 115890
2010-10-07 00:53:56 +00:00
b71a77d7b8
add a new BinOpAI class to represent the immediate form that directly acts on EAX.
...
This does change the generated .inc files to include the implicit use/def of eax.
Since these instructions are only generated by the assembler and disassembler it
doesn't actually matter though.
llvm-svn: 115885
2010-10-07 00:43:39 +00:00
742adc328a
Allow use of the 16-bit literal move instruction in CMOVs for ARM mode.
...
llvm-svn: 115884
2010-10-07 00:42:42 +00:00
894d2e6146
add a bunch of classes for other common patterns.
...
As usual, no change in generated .inc files.
llvm-svn: 115882
2010-10-07 00:35:28 +00:00
e17d7212f1
Define a new BinOpRI8 class and use it to define the imm8 versions of and.
...
llvm-svn: 115880
2010-10-07 00:12:45 +00:00
b19bae4e3e
Constrain the offset register to a *_NOSP register class when inserting LEA
...
instructions.
This unbreaks the machine code verifier and fixes PR8317.
llvm-svn: 115879
2010-10-07 00:07:26 +00:00
356f16c142
add the pattern operator to match to X86TypeInfo, use this to
...
convert AND64ri32 to use BinOpRI.
llvm-svn: 115878
2010-10-07 00:01:39 +00:00
b2dd88db6b
Properly handle GR32_NOSP in X86RegisterInfo::getMatchingSuperRegClass.
...
This function looks like it is about ready to be generated by TebleGen.
llvm-svn: 115876
2010-10-06 23:56:46 +00:00
25cd3bfbd7
remove trailing whitespace
...
llvm-svn: 115860
2010-10-06 22:46:47 +00:00
bff84d418f
First in a sequence of ARM/MC/*ELF* specific work.
...
Lifted the EmitRawText calls to ARMAsmPrinter::emitAttribute()
Added ARMAsmPrinter::emitAttributes() (plural s).
TODO:
.cpu attribute needs to be refactored
llvm-svn: 115859
2010-10-06 22:36:46 +00:00
24ab1ce8c2
Clean up MOVi32imm and t2MOVi32imm pseudo instruction definitions.
...
llvm-svn: 115853
2010-10-06 22:01:26 +00:00
f49540cb4f
Kill of the vestiges of the 'call' Modifier (no longer needed for PLT).
...
llvm-svn: 115845
2010-10-06 21:36:43 +00:00
2c95027258
Now that VDUPfqf and VDUPfdfare properly pseudos, kill the no-longer-needed
...
"lane" operand modifier.
llvm-svn: 115843
2010-10-06 21:22:32 +00:00
2e3e2a006b
Change the NEON VDUPfdf and VDUPfqf pseudo-instructions to actually be
...
pseudo instructions.
llvm-svn: 115840
2010-10-06 21:16:16 +00:00
233b3a2f95
Add a 'pattern' arg to the ARM PseudoNeonI class.
...
llvm-svn: 115831
2010-10-06 20:36:55 +00:00
8025f89860
target operand flag values aren't a bitmask
...
llvm-svn: 115798
2010-10-06 16:51:55 +00:00
49d4c0bd18
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This
...
allow target to correctly compute latency for cases where static scheduling
itineraries isn't sufficient. e.g. variable_ops instructions such as
ARM::ldm.
This also allows target without scheduling itineraries to compute operand
latencies. e.g. X86 can return (approximated) latencies for high latency
instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
e.g. ldm and those used by store multiple instructions, e.g. stm.
llvm-svn: 115755
2010-10-06 06:27:31 +00:00
6e85be2ecf
enhance X86TypeInfo to include information about the encoding and
...
operand kind for immediates. Use these to define a new BinOpRI
class and switch AND8/16/32ri over to it. AND64ri32 needs some
more refactoring before it can make the switcheroo.
llvm-svn: 115752
2010-10-06 05:55:42 +00:00
94eff91dc0
add a class for _REV nodes.
...
llvm-svn: 115748
2010-10-06 05:35:22 +00:00
a46073b56b
sink more intelligence into the ITy base class. Now it knows
...
that i8 operations are even and i16,i32,i64 operations have a
low opcode bit set (they are odd).
llvm-svn: 115747
2010-10-06 05:28:38 +00:00
b6da2be7e8
refactor things a bit, now the REX_W and OpSize prefix bytes are inferred from the type info.
...
llvm-svn: 115745
2010-10-06 05:20:57 +00:00
7bbd809b6c
with tblgen suitably extended, we can now get the load node from typeinfo.
...
llvm-svn: 115744
2010-10-06 04:58:43 +00:00
1fc81e90f7
lets go all meta and define new X86 type wrappers that declare the associated
...
gunk that goes along with an MVT (e.g. reg class, preferred load operation,
memory operand)
llvm-svn: 115727
2010-10-06 00:45:24 +00:00
eadaeaab93
introduce a new BinOpRM class and use it to factor AND*rm. This points out
...
that I need a heavier handed approach to get ultimate factorization.
llvm-svn: 115726
2010-10-06 00:30:49 +00:00
9402633637
remove the !nameconcat tblgen feature. It "shorthand" and only used in 4 places
...
where !cast is just as short.
llvm-svn: 115722
2010-10-06 00:19:21 +00:00
04c342ea20
replace stuff like:
...
let AsmString = !strconcat(
!strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)),
!strconcat("\t", asm));
with:
let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
:)
llvm-svn: 115720
2010-10-06 00:05:18 +00:00
61ea00b494
allow !strconcat to take more than two operands to eliminate
...
!strconcat(!strconcat(!strconcat(!strconcat
Simplify some x86 td files to use it.
llvm-svn: 115719
2010-10-05 23:58:18 +00:00
b9f2d50d5f
Comment out fastisel debugging message.
...
llvm-svn: 115717
2010-10-05 23:50:58 +00:00
97b1368ae3
associate the instruction suffix letter with the integer gpr
...
register class, and use this to simplify use of BinOpRR.
llvm-svn: 115716
2010-10-05 23:43:04 +00:00
7359194b63
introduce a new BinOpRR class, and convert 4 and instructions to use it.
...
llvm-svn: 115715
2010-10-05 23:32:05 +00:00
8cfc459274
Random cleanup and make the intermediate register in fptosi a
...
32-bit fp reg, not 64-bit.
Fixes SingleSource.
llvm-svn: 115711
2010-10-05 23:13:24 +00:00
cff5b0ea36
Move cmov pseudo instructions to InstrCompiler,
...
convert all the rest of the cmovs to the multiclass,
with good results:
X86InstrCMovSetCC.td | 598 +--------------------------------------------------
X86InstrCompiler.td | 61 +++++
2 files changed, 77 insertions(+), 582 deletions(-)
llvm-svn: 115707
2010-10-05 23:09:10 +00:00
1a1c600110
Use #NAME# to have the CMOV multiclass define things with the same names as before
...
(e.g. CMOVBE16rr instead of CMOVBErr16).
llvm-svn: 115705
2010-10-05 23:00:14 +00:00
7538ed80a9
enhance tblgen to support anonymous defm's, use this to
...
simplify the X86 CMOVmr's.
llvm-svn: 115702
2010-10-05 22:51:56 +00:00
fa25dd9548
convert cmov mr patterns to use a multipattern. Death to redundancy
...
and verbosity
llvm-svn: 115701
2010-10-05 22:42:54 +00:00
0067ee02f9
switch CMOVBE to the multipattern:
...
21 insertions(+), 53 deletions(-)
Moar change coming before I switch the rest.
llvm-svn: 115697
2010-10-05 22:23:58 +00:00
907d86db22
fix a bug I introduced in r115669, which ended up with MOV64mr_TC
...
not getting marked as mayStore. This fixes llvm-gcc bootstrap.
llvm-svn: 115693
2010-10-05 22:16:48 +00:00
c3a767e9b0
add a multiclass for cmov's, but don't start using it yet.
...
llvm-svn: 115692
2010-10-05 22:01:02 +00:00
aa02c1c91d
use a multipattern to define setcc instructions:
...
X86InstrCMovSetCC.td | 200 ++++++---------------------------------------------
1 file changed, 27 insertions(+), 173 deletions(-)
llvm-svn: 115689
2010-10-05 21:34:29 +00:00
8f4f1d1136
move SETB pseudos into the same place in InstrCompiler.td
...
llvm-svn: 115686
2010-10-05 21:18:04 +00:00
13111b08fb
Replace a gross hack (the MOV64ri_alt instruction) with a slightly less
...
gross hack (having the asmmatcher handle the alias).
llvm-svn: 115685
2010-10-05 21:09:45 +00:00
ab85ef9e55
distribute the rest of the contents of X86Instr64bit.td out to
...
the right places. X86Instr64bit.td now dies, long live x86-64!
llvm-svn: 115669
2010-10-05 20:49:15 +00:00
27c763d342
move the rest of the simple 64-bit arithmetic into InstrArithmetic.td
...
llvm-svn: 115663
2010-10-05 20:35:37 +00:00
c2f5e5764f
continue moving 64-bit stuff into X86InstrArithmetic.td
...
llvm-svn: 115660
2010-10-05 20:23:31 +00:00
e929899a3f
Increase the number of bits used internally by the ARM target to represent the
...
addressing mode from four to five.
llvm-svn: 115645
2010-10-05 18:14:55 +00:00
7552d15d19
move 64-bit add and adc to InstrArithmetic.
...
llvm-svn: 115632
2010-10-05 16:59:08 +00:00
182e87caaf
rewrote two addr constraints so that they are only set, not set and then nestedly cleared.
...
llvm-svn: 115631
2010-10-05 16:52:25 +00:00
39c70f4833
split the 32-bit integer arithmetic instructions out to their own file.
...
llvm-svn: 115627
2010-10-05 16:39:12 +00:00
1818dd510e
integrate the 64-bit shifts into X86InstrShiftRotate.td. Enough for tonight.
...
llvm-svn: 115608
2010-10-05 07:13:35 +00:00
1b3aa8678e
move 32-bit shift and rotates out to their own file.
...
llvm-svn: 115607
2010-10-05 07:00:12 +00:00
89497a990e
add new file
...
llvm-svn: 115606
2010-10-05 06:52:35 +00:00
a68466c202
move sign and zero extensions out to their own file.
...
llvm-svn: 115605
2010-10-05 06:52:26 +00:00
84571a1581
move some instructions from Instr64Bit -> InstrInfo.
...
bswap32 doesn't read eflags.
llvm-svn: 115604
2010-10-05 06:47:35 +00:00
da8c94ef44
move CMOV_FR32 and friends to InstrCompiler, since they are
...
pseudo instructions.
Move POPCNT to InstrSSE since they are SSE4 instructions.
llvm-svn: 115603
2010-10-05 06:41:40 +00:00
44a5a2b569
move various pattern matching support goop out of X86Instr64Bit, to live
...
with the 32-bit stuff.
llvm-svn: 115602
2010-10-05 06:37:31 +00:00
fa9b058eef
split conditional moves and setcc's out to their own file.
...
llvm-svn: 115601
2010-10-05 06:33:16 +00:00
f9594ba4e7
move string pseudo instructions to InstrCompiler consolidate 64-bit and 32-bit together.
...
llvm-svn: 115600
2010-10-05 06:27:48 +00:00
c184a57e98
move the atomic pseudo instructions out to X86InstrCompiler.td
...
llvm-svn: 115599
2010-10-05 06:22:35 +00:00
c793f8bca6
move more pseudo instructions out to X86InstrCompiler.td
...
llvm-svn: 115598
2010-10-05 06:10:16 +00:00
52d3935dfe
move VMX instructions out to their own file.
...
llvm-svn: 115597
2010-10-05 06:06:53 +00:00
ae33f5d93b
continue moving stuff out to X86InstrSystem.td. Move
...
control flow stuff out to X86InstrControl.td. Move
some compiler pseudo instructions and Pat<> patterns
out to X86InstrCompiler.td
llvm-svn: 115596
2010-10-05 06:04:14 +00:00
70ac5fa42c
fix MSVC 2010 build.
...
llvm-svn: 115594
2010-10-05 06:00:43 +00:00
e7f00cbb7c
Cleanup Whitespace.
...
llvm-svn: 115593
2010-10-05 06:00:33 +00:00
dec85b8c64
refactor .td files a bit, moving system instructions out to X86InstrSystem.td
...
llvm-svn: 115591
2010-10-05 05:32:15 +00:00
a85a4e21c9
Re-apply r115363 and r115366 now that r115525 has removed the un-needed header
...
that caused the circular dependencies on Linux.
Built OK for me on OSX and Linux (Ubuntu) with configure/make and CMake. Will
keep an eye on the bots....
llvm-svn: 115582
2010-10-05 00:34:11 +00:00
402e54822b
The pshufw instruction came about in MMX2 when SSE was introduced. Don't place
...
it in with the SSSE3 instructions.
Steward! Could you place this chair by the aft sun deck? I'm trying to get away
from the Astors. They are such boors!
llvm-svn: 115552
2010-10-04 20:24:01 +00:00
0807d0065f
Remove unneeded header
...
llvm-svn: 115525
2010-10-04 17:53:40 +00:00
87f77b5f9a
Add hook in MCSection to decide when to use "optimized nops", for each
...
section kind. Previously, optimized nops were only used for MachO.
Also added tests for ELF and COFF.
llvm-svn: 115523
2010-10-04 17:32:41 +00:00
d77a443631
va_args support for Win64.
...
Patch by Cameron!
llvm-svn: 115480
2010-10-03 22:52:07 +00:00
ff85688559
Properly emit stack probe on win64 (for non-mingw targets).
...
Based on the patch by Cameron Esfahani!
llvm-svn: 115479
2010-10-03 22:02:38 +00:00
bb48e26732
Add 3DNowA instructions.
...
llvm-svn: 115477
2010-10-03 20:23:13 +00:00
d3593c3a8e
the immediate field of pshufw is actually an 8-bit field, not a 8-bit field that is sign extended. This fixes PR8288
...
llvm-svn: 115473
2010-10-03 19:09:13 +00:00
66e08d43d2
Jim Asked us to move DataLayout on ARM back to the most specialized classes. Do
...
so and also change X86 for consistency.
Investigating if this can be improved a bit.
llvm-svn: 115469
2010-10-03 18:59:45 +00:00
b44b202d66
add support for the prefetch/prefetchw instructions, move femms into
...
the right file. The assembler supports all the 3dnow instructions now,
but not the "3dnowa" ones.
llvm-svn: 115468
2010-10-03 18:42:30 +00:00
3a0a620c2e
what the heck, add support for the rest of the 3dNow! binary operations.
...
llvm-svn: 115467
2010-10-03 18:24:18 +00:00
45270db916
Implement support for the bizarre 3DNow! encoding (which is unlike anything
...
else in X86), and add support for pavgusb. This is apparently the
only instruction (other than movsx) that is preventing ffmpeg from building
with clang.
If someone else is interested in banging out the rest of the 3DNow!
instructions, it should be quite easy now.
llvm-svn: 115466
2010-10-03 18:08:05 +00:00
73eac2aadf
Major changes to Cortex-A9 itinerary.
...
1. Model dual issues as two FUs.
2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a
dependent pipeline on ALU0.
The changes do not have much impact on codegen right now. But I plan to make
pre-RA scheduler multi-issue aware which should take good advantage of the
changes.
llvm-svn: 115457
2010-10-03 02:03:59 +00:00
ae1a9de083
stub out a header to put 3dNow! instructions into.
...
llvm-svn: 115429
2010-10-02 23:06:23 +00:00
4756bbeba0
fix a regression introduced in r115243, in which the instruction
...
backing int_x86_ssse3_pshuf_w got removed. This caused PR8280.
llvm-svn: 115422
2010-10-02 21:32:15 +00:00
306084e9b7
Wind these directories back too. File adds and removes are properly represented
...
in patches. :-(
llvm-svn: 115396
2010-10-02 01:16:59 +00:00
0aee161c69
Continue reverting r115363.
...
llvm-svn: 115395
2010-10-02 01:08:17 +00:00
c18b735552
Revert patches r115363 r115367 r115391 due to build breakage:
...
llvm[2]: Updated LibDeps.txt because dependencies changed
llvm[2]: Checking for cyclic dependencies between LLVM libraries.
find-cycles.pl: Circular dependency between *.a files:
find-cycles.pl: libLLVMMSP430AsmPrinter.a libLLVMMSP430CodeGen.a
llvm-svn: 115393
2010-10-02 01:06:42 +00:00
aaf9c32d9f
Update CMake files for recent AsmPrinter->InstPrinter changes. Can someone who
...
is more familiar with CMake please review?
llvm-svn: 115391
2010-10-02 00:39:56 +00:00
7787f79f21
Start on lowering global addresses.
...
llvm-svn: 115390
2010-10-02 00:32:44 +00:00
ff1751c0a6
PrintSpecial() can go away now.
...
llvm-svn: 115376
2010-10-01 23:27:48 +00:00
83a5ec8fe0
Stub out constant GV handling, fixes C++ eh tests.
...
llvm-svn: 115375
2010-10-01 23:24:42 +00:00
fae8305e2b
Nuke the rest of the :comment references
...
llvm-svn: 115373
2010-10-01 23:21:38 +00:00
c13194254b
Nuke a bunch of no-longer-needed comment-only asm strings.
...
llvm-svn: 115370
2010-10-01 23:09:33 +00:00
111c550dea
Now that the asmprinter itself isn't in the subdir, rename 'AsmPrinter' to
...
'InstPrinter' to fall into line with the other MC-ized assembly printer
using targets.
llvm-svn: 115367
2010-10-01 22:57:18 +00:00
a317815463
Fix r115332: correctly model AGU / NEON mux.
...
llvm-svn: 115365
2010-10-01 22:52:29 +00:00
f31f33ea89
Thread the determination of branch prediction hit rates back through the if-conversion heuristic APIs. For now,
...
stick with a constant estimate of 90% (branch predictors are good!), but we might find that we want to provide
more nuanced estimates in the future.
llvm-svn: 115364
2010-10-01 22:45:50 +00:00
517abb44a2
Move the asmprinter and MC lowering out of the AsmPrinter (soon to be
...
InstPrinter) subdir
llvm-svn: 115363
2010-10-01 22:45:38 +00:00
0e854f3d43
Rename the AsmPrinter directory to InstPrinter for those targets that have
...
been MC-ized for assembly printing. MSP430 is mostly so, but still has the
asm printer and lowering code in the printer subdir for the moment.
llvm-svn: 115360
2010-10-01 22:39:28 +00:00
1969887fc6
Fix scheduling infor for vmovn and vshrn which I broke accidentially.
...
llvm-svn: 115354
2010-10-01 21:48:06 +00:00
f3179567de
Add operand cycles for vldr / vstr.
...
llvm-svn: 115353
2010-10-01 21:40:30 +00:00
9d0136274b
Direct calls only for arm fast isel for now.
...
llvm-svn: 115350
2010-10-01 21:33:12 +00:00
2a5d764858
NEON scheduling info fix. vmov reg, reg are single cycle instructions.
...
llvm-svn: 115344
2010-10-01 20:50:58 +00:00
6080da7a79
Fix thinko on store instructions. Fixes test_indvars failure.
...
llvm-svn: 115342
2010-10-01 20:46:04 +00:00
2ecba4a07e
Make the spelling of the flags for old-style if-conversion heuristics consistent between ARM and Thumb2.
...
llvm-svn: 115341
2010-10-01 20:33:47 +00:00
671d57865e
Provide an option to restore old-style if-conversion heuristics for Thumb2.
...
llvm-svn: 115339
2010-10-01 20:28:06 +00:00
89e6f6759f
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly.
...
llvm-svn: 115332
2010-10-01 19:41:46 +00:00
05ed521a88
grammar
...
llvm-svn: 115314
2010-10-01 14:57:48 +00:00
14e909a942
Delete token *after* reading from it.
...
llvm-svn: 115311
2010-10-01 12:25:27 +00:00
56f7cd255b
Zap some redundant 'ori $?, $?, 0' from SPU.
...
Also remove some code that died in the process.
One now non-existant ori is checked for.
llvm-svn: 115306
2010-10-01 09:20:01 +00:00
c1e209d40e
Implement double return values in calls. Fixes
...
SingleSource/Regression/C/casts.c.
llvm-svn: 115246
2010-10-01 00:00:11 +00:00
dd224d2333
Massive rewrite of MMX:
...
The x86_mmx type is used for MMX intrinsics, parameters and
return values where these use MMX registers, and is also
supported in load, store, and bitcast.
Only the above operations generate MMX instructions, and optimizations
do not operate on or produce MMX intrinsics.
MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into
smaller pieces. Optimizations may occur on these forms and the
result casted back to x86_mmx, provided the result feeds into a
previous existing x86_mmx operation.
The point of all this is prevent optimizations from introducing
MMX operations, which is unsafe due to the EMMS problem.
llvm-svn: 115243
2010-09-30 23:57:10 +00:00
b9b63ee031
Temporarily add a flag to make it easier to compare the new-style ARM if
...
conversion heuristics to the old-style ones.
llvm-svn: 115239
2010-09-30 23:48:38 +00:00
c6e13f7383
Clean up asm writer usage for x86 and msp430 to flag that the writer should
...
use MC instructions in the printInstruction() method via the tablegen flag
for it rather than a #define prior to including the autogenerated bits.
llvm-svn: 115238
2010-09-30 23:40:25 +00:00
56094ff402
Movement and cleanup.
...
llvm-svn: 115225
2010-09-30 22:34:19 +00:00
78f8d4eaf0
Start of generalized call support for ARM fast isel.
...
llvm-svn: 115203
2010-09-30 20:49:44 +00:00
c8e2e9d830
Nuke a few more unused asm strings
...
llvm-svn: 115193
2010-09-30 19:53:58 +00:00
7e872969ce
Move getPointerSize() to the base class since it's not dependent on MachO
...
vs. ELF
llvm-svn: 115180
2010-09-30 17:45:51 +00:00
5a5ddc402e
Remove extraneous ';'
...
llvm-svn: 115176
2010-09-30 17:19:17 +00:00
73a7caee4b
preemptively add the rest of the non-n fpstack instructions.
...
llvm-svn: 115168
2010-09-30 17:11:29 +00:00
b9429179f9
The asm strings are never used at all, so just nuke 'em entirely.
...
llvm-svn: 115160
2010-09-30 16:56:53 +00:00
4373badcdf
implement support for finit, PR8258
...
llvm-svn: 115156
2010-09-30 16:42:53 +00:00
adc0dbe470
add support for fstcw, PR8259
...
llvm-svn: 115154
2010-09-30 16:39:29 +00:00
bad267fa05
Adds getPointerSize() to the AsmBackend which will be needed by the final patch
...
for the dwarf .loc support to emit dwarf line number tables.
llvm-svn: 115153
2010-09-30 16:38:07 +00:00
136ed51b08
80 column fix
...
llvm-svn: 115149
2010-09-30 15:25:22 +00:00
6c233c141e
Fix two tiny issues (ARM does not need COFF) and comment sanity.
...
llvm-svn: 115147
2010-09-30 14:58:19 +00:00
689651c767
trailing whitespace
...
llvm-svn: 115136
2010-09-30 03:21:00 +00:00
58bce99385
Remove misplaced ';'. Make buildbots happy, hopefully.
...
llvm-svn: 115135
2010-09-30 03:20:34 +00:00
70d6e0e0ff
Correctly produce R_X86_64_32 or R_X86_64_32S.
...
With this patch in
movq $foo, foo(%rip)
foo:
.long foo
We produce a R_X86_64_32S for the first relocation and R_X86_64_32 for the
second one.
llvm-svn: 115134
2010-09-30 03:11:42 +00:00
645f6c2bef
Tiny patch for proof-of-concept cleanup of ARMAsmPrinter::EmitStartOfAsmFile()
...
Small test for sanity check of resulting ARM .s file.
Tested against -r115129.
llvm-svn: 115133
2010-09-30 02:45:56 +00:00
4a9cb8f10e
Go ahead and jump!
...
Now that the MC lowering handles the expansion of the pseudos, kill the horrible
blobs of text.
llvm-svn: 115130
2010-09-30 02:18:06 +00:00
b32124545b
I added a new file ARMAsmBackend which stubs out in similar ways to
...
the eqv X86 class.
For now, I split the ELFARMAsmBackend from the DarwinARMAsmBackend
(also mimicking X86)
Tested against -r115126
llvm-svn: 115129
2010-09-30 02:17:26 +00:00
2ff7de0264
Now that the pseudos that needed this are all custom lowered, we can go back
...
to an empty PrintSpecial()
llvm-svn: 115128
2010-09-30 02:02:22 +00:00
080fdf4609
Nuke it from orbit. It's the only way to be sure.
...
(Kill the dead non-MC asm printer for the ARM target.)
llvm-svn: 115127
2010-09-30 01:57:53 +00:00
2fb20b1d37
ARM instruction itinerary fixes:
...
1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones.
2. Cortex-a9 is out-of-order so model all read cycles as cycle 1.
3. Lots of other random fixes for A8 and A9.
llvm-svn: 115121
2010-09-30 01:08:25 +00:00
2b76c66fd6
Add constant folding for strspn and strcspn to SimplifyLibCalls.
...
llvm-svn: 115116
2010-09-30 00:58:35 +00:00
7939806ecc
Refactor arm fast isel libcall handling so that pieces can be used
...
for generic call handling.
llvm-svn: 115105
2010-09-29 23:11:09 +00:00
0574cc556a
Noticed by inspection when looking for other cmov bits.
...
llvm-svn: 115100
2010-09-29 23:00:29 +00:00
Eric Christopher