9f6c622f88
Fixed handling of immediate operand sizes, which
...
weren't properly reflecting the OperandSize attribute
of the instruction leading to improper decoding of
certain instructions with the 66H prefix. Also added
a test case for this.
llvm-svn: 117084
2010-10-22 01:24:11 +00:00
28418de7ee
Add tests for NEON encoding of vmull.
...
llvm-svn: 117077
2010-10-21 22:19:53 +00:00
a97becfaac
ARM binary encodings for MVN variants.
...
llvm-svn: 117076
2010-10-21 22:19:32 +00:00
22c940c9ab
Add tests for NEON encoding of vqdmulh and vqrdmulh.
...
llvm-svn: 117074
2010-10-21 22:05:33 +00:00
5edb03ee57
ARM Binary encoding information for BFC/BFI instructions.
...
llvm-svn: 117072
2010-10-21 22:03:21 +00:00
eff79f13a6
Add tests for NEON vmul encoding.
...
llvm-svn: 117069
2010-10-21 21:51:58 +00:00
6e1cf114f9
Rename this test to better reflect its contents.
...
llvm-svn: 117067
2010-10-21 21:40:15 +00:00
c47913acd2
Add tests for NEON encodings of vaddhn and vraddhn.
...
llvm-svn: 117064
2010-10-21 20:56:57 +00:00
d8be664273
Add tests for NEON encodings of vqadd, which was already correctly encoded.
...
llvm-svn: 117059
2010-10-21 20:42:04 +00:00
6b7e401049
Add correct NEON encodings for vhadd and vrhadd.
...
llvm-svn: 117047
2010-10-21 18:55:04 +00:00
9561084188
Add correct encodings for NEON vaddw.s* and vaddw.u*.
...
llvm-svn: 117040
2010-10-21 18:20:25 +00:00
15c97706e8
Provide correct NEON encodings for vaddl.u* and vaddl.s*.
...
llvm-svn: 117039
2010-10-21 18:09:17 +00:00
8ba86f801d
Do not recurse into symbol refs that have a variant kind. This prevents us
...
from losing the variant when producing a relocation on an alias.
llvm-svn: 117037
2010-10-21 18:00:20 +00:00
0138a05557
More tweaks to X86 instructions to allow the 'w' suffix in places it makes
...
sense, when the instruction takes the 16-bit ax register or m16 memory
location. These changes to llvm-mc matches what the darwin assembler allows
for these instructions. Also added the missing flex (without the wait prefix)
and ud2a as an alias to ud2 (still to add ud2b).
llvm-svn: 117031
2010-10-21 17:16:46 +00:00
2a7d269a2b
Fix whitespace.
...
llvm-svn: 117002
2010-10-21 06:25:08 +00:00
f4ebec03e0
putback r116983 and fix simple-fp-encoding.ll tests
...
llvm-svn: 116992
2010-10-21 03:40:16 +00:00
6083502848
Implement correct encodings for NEON vadd, both integer and floating point.
...
llvm-svn: 116981
2010-10-21 00:48:00 +00:00
a65f914bb0
Add encoding for moving a value between two ARM core registers and a doublework
...
extension register.
llvm-svn: 116970
2010-10-20 23:37:40 +00:00
058190507b
Add encodings for movement between ARM core registers and single-precision
...
registers.
llvm-svn: 116961
2010-10-20 22:44:54 +00:00
89f6613e76
Handle _GLOBAL_OFFSET_TABLE_ correctly.
...
llvm-svn: 116932
2010-10-20 16:46:08 +00:00
e8b3711ae9
Fixing r116753 r116756 r116777
...
The failures in r116753 r116756 were caused by a python issue -
Python likes to append 'L' suffix to stringified numbers if the number
is larger than a machine int. Unfortunately, this causes a divergence of
behavior between 32 and 64 bit python versions.
I re-crafted elf-dump/common_dump to take care of these issues by:
1. always printing 0x (makes for easy sed/regex)
2. always print fixed length (exactly 2 + numBits/4 digits long)
by mod ((2^numBits) - 1)
3. left-padded with '0'
There is a residual common routine that is also used by
macho-dump (dataToHex) , so I left the 'section_data' test values alone.
llvm-svn: 116823
2010-10-19 17:39:10 +00:00
eac5e381cc
Speculatively revert 116753 and 116756 to attempt to fix the bots.
...
llvm-svn: 116777
2010-10-19 00:19:49 +00:00
49843c0162
Added a few tweaks to the Intel Descriptor-table support instructions to allow
...
word forms and suffixed versions to match the darwin assembler in 32-bit and
64-bit modes. This is again for use just with assembly source for llvm-mc .
llvm-svn: 116773
2010-10-19 00:01:44 +00:00
eae048885d
Changed elf-dump to output hex format by default.
...
Also updated tests.
llvm-svn: 116753
2010-10-18 21:32:41 +00:00
fba9f74932
Implement R_386_GOT32.
...
llvm-svn: 116744
2010-10-18 20:47:21 +00:00
0a5314fdb3
Relocate with .bss instead of using the symbol. Matches gas behavior.
...
llvm-svn: 116741
2010-10-18 20:25:33 +00:00
e3dc9e2ea1
Produce ELF::R_386_GOTPC relocations.
...
llvm-svn: 116728
2010-10-18 18:36:12 +00:00
b9783dd9bc
Added a handful of x86-32 instructions that were missing so that llvm-mc would
...
be more complete. These are only expected to be used by llvm-mc with assembly
source so there is no pattern, [], in the .td files. Most are being added to
X86InstrInfo.td as Chris suggested and only comments about register uses are
added. Suggestions welcome on the .td changes as I'm not sure on every detail
of the x86 records. More missing instructions will be coming.
llvm-svn: 116716
2010-10-18 17:04:36 +00:00
3521f8467d
Produce a R_386_PLT32 when needed. Moved the default cases of switches to the
...
start for consistency.
llvm-svn: 116715
2010-10-18 16:58:03 +00:00
4464e0858f
Handle GOTOFF correctly on i386.
...
llvm-svn: 116711
2010-10-18 16:38:04 +00:00
4262a22225
Add a MCObjectFormat class so that code common to all targets that use a
...
single object format can be shared.
This also adds support for
mov zed+(bar-foo), %eax
on ELF and COFF targets.
llvm-svn: 116675
2010-10-16 18:23:53 +00:00
0d14b5b0fa
Unbreak test on non-COFF targets.
...
llvm-svn: 116669
2010-10-16 11:27:13 +00:00
17990d5690
MC-COFF: Add support for default-null weak externals.
...
llvm-svn: 116666
2010-10-16 08:25:57 +00:00
68a335e185
ARM mode encoding information for UBFX and SBFX instructions.
...
llvm-svn: 116588
2010-10-15 17:15:16 +00:00
fbcf0db7ee
Refactor code a bit and avoid creating unnecessary entries in the string
...
map.
llvm-svn: 116579
2010-10-15 15:39:06 +00:00
59351844e1
ARM instructions that are both predicated and set the condition codes
...
have been printed with the "S" modifier after the predicate. With ARM's
unified syntax, they are supposed to go in the other order. We fixed this
for Thumb when we switched to unified syntax but missed changing it for
ARM. Apparently we don't generate these instructions often because no one
noticed until now. Thanks to Bill Wendling for the testcase!
llvm-svn: 116563
2010-10-15 03:23:44 +00:00
0b5c743811
Simplify test file a bit.
...
llvm-svn: 116540
2010-10-14 23:32:44 +00:00
89efff3763
Add testcase for RRX and ASRS (which effectively tests MOVs, since those
...
are just forms of that instruction).
llvm-svn: 116538
2010-10-14 23:29:18 +00:00
eafcb27ded
MOVi16 and MOVT ARM mode encodings.
...
llvm-svn: 116498
2010-10-14 18:54:27 +00:00
bee6e9f8e0
Remove some code duplication.
...
llvm-svn: 116484
2010-10-14 16:34:44 +00:00
6f52f8a87d
Add support for vmov.f64/.f32 encoding. There's a bit of a hack going on
...
here. The f32 in FCONSTS is handled as a double instead of a float in the
code. So the encoding of the immediate into the instruction isn't exactly in
line with the documentation in that regard. But given that we know it's handled
as a double, it doesn't cause any harm.
llvm-svn: 116471
2010-10-14 02:33:26 +00:00
0441c6cba0
Add encoding for 'fmstat'.
...
llvm-svn: 116466
2010-10-14 01:19:34 +00:00
0825f3e441
- Add encodings for multiply add/subtract instructions in all their glory.
...
- Add missing patterns for some multiply add/subtract instructions.
- Add encodings for VMRS and VMSR.
llvm-svn: 116464
2010-10-14 01:02:08 +00:00
7e72ec6626
Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern
...
and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.
llvm-svn: 116432
2010-10-13 21:00:04 +00:00
f106ecfa59
Add MC encodings for VCVT* instrunctions.
...
llvm-svn: 116431
2010-10-13 20:58:46 +00:00
1e7db68774
Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.
...
llvm-svn: 116421
2010-10-13 19:56:10 +00:00
651dc7c9e9
Add ARM mode operand encoding information for ADDE/SUBE instructions.
...
llvm-svn: 116412
2010-10-13 18:00:52 +00:00
6e27b4f530
Add encodings for VNEG and VSQRT. Also add encodings for VMOV, but not a test
...
just yet.
llvm-svn: 116386
2010-10-13 01:17:33 +00:00
576fd0b110
Add encodings for VCVT instructions.
...
llvm-svn: 116385
2010-10-13 00:56:35 +00:00
8c519c0d4b
Add ARM encoding information for comparisons, forced-cc-out arithmetics, and
...
arithmetic-with-carry-in instructions.
llvm-svn: 116384
2010-10-13 00:50:27 +00:00
da4ddf0fcf
Add VCMPZ and VABS.
...
llvm-svn: 116383
2010-10-13 00:38:07 +00:00
f9ca535495
Refactor VCMP instructions.
...
llvm-svn: 116379
2010-10-13 00:04:29 +00:00
7dd8c0b991
Add encodings for VNMUL[SD].
...
llvm-svn: 116375
2010-10-12 23:47:37 +00:00
a06aee826c
Add encodings for VDIV and VMUL.
...
llvm-svn: 116370
2010-10-12 23:22:27 +00:00
d5f8c3350d
Be nitpicky and line up the comments.
...
llvm-svn: 116365
2010-10-12 23:14:03 +00:00
646a506724
Add encoding for VSUB and VCMP.
...
Fear not! I'm going to try a refactoring right now. :)
llvm-svn: 116359
2010-10-12 22:55:35 +00:00
9513a7e87f
Don't need to specify calling convention. Add 'readnone' to functions.
...
llvm-svn: 116354
2010-10-12 22:24:10 +00:00
ac6cd00706
Encoding for VADDD. Plus a test for the VFP instructions.
...
llvm-svn: 116348
2010-10-12 22:08:41 +00:00
6fead930af
Add encoding information for the remainder of the generic arithmetic
...
ARM instructions.
llvm-svn: 116313
2010-10-12 17:11:26 +00:00
b7c2962d20
MC machine encoding for simple aritmetic instructions that use a shifted
...
register operand.
llvm-svn: 116259
2010-10-11 23:16:21 +00:00
a6a984bd96
MC-COFF: Fix .bss section size. Fixes PR8335. Patch by NAKAMUTA Takumi!
...
llvm-svn: 116155
2010-10-09 16:04:45 +00:00
86bbd71088
MC-COFF: Implement InitSections. Fixes PR8335.
...
llvm-svn: 116151
2010-10-09 15:44:27 +00:00
c8dbdfd4ba
MC-COFF: Add COFFAsmParser. Completes PR8343.
...
llvm-svn: 116150
2010-10-09 11:01:07 +00:00
c43c930690
Implement a few more binary encoding bits. Still very early stage proof-of-
...
concept level stuff at this point, but it is generally working for those
instructions that know how to map the operands.
This patch fills in the register operands for add/sub/or/etc instructions
and adds the conditional execution predicate encoding.
llvm-svn: 116112
2010-10-08 21:45:55 +00:00
af8b4871a8
Call InitSections in llc and clang so that the binaries produced by them
...
are easier to diff with those produced by llvm-mc.
llvm-svn: 116095
2010-10-08 19:37:38 +00:00
42a07e8545
Add test file for simple ARM binary encodings with MC
...
llvm-svn: 116024
2010-10-08 00:47:59 +00:00
00be34d009
MC-COFF: Add test for my last commit.
...
llvm-svn: 116015
2010-10-08 00:00:28 +00:00
1666b61357
MC-COFF: Fix symbol aliases. Fixes PR8251.
...
llvm-svn: 115909
2010-10-07 06:29:33 +00:00
5f2d6a5cd9
Get binding and visibility info from the the alias, but Type from the symbol
...
being aliased.
llvm-svn: 115836
2010-10-06 21:02:29 +00:00
d444577382
If a symbol is global, reloc against it even if it is in a mergeable section.
...
llvm-svn: 115817
2010-10-06 19:27:21 +00:00
83b2a3337f
Make sure weak symbols are listed after the local ones.
...
llvm-svn: 115795
2010-10-06 16:47:31 +00:00
8f3d2c9058
Correctly handle GOTPCREL relocations.
...
llvm-svn: 115793
2010-10-06 16:23:36 +00:00
d7565c3a06
Use a relocation against the symbol if it is a PLT and the symbol is in another
...
section. Common because of linkonce sections.
llvm-svn: 115718
2010-10-05 23:57:26 +00:00
0ad137e98e
Implement more alias cases.
...
llvm-svn: 115699
2010-10-05 22:26:43 +00:00
13111b08fb
Replace a gross hack (the MOV64ri_alt instruction) with a slightly less
...
gross hack (having the asmmatcher handle the alias).
llvm-svn: 115685
2010-10-05 21:09:45 +00:00
c58a37ea51
Don't crash in a strange .size directive.
...
llvm-svn: 115684
2010-10-05 21:02:45 +00:00
a3b34ed2df
MC-COFF: Fix (PR8278) temporary symbol relocations.
...
llvm-svn: 115656
2010-10-05 19:48:03 +00:00
b91bac6c96
Add support for a fill value in the .zero directive.
...
llvm-svn: 115655
2010-10-05 19:42:57 +00:00
b1d0789357
Implement a simple alias case and refactor the code a bit so that the
...
isInSymtab and isLocal logic in the two loops don't get easily out of sync.
llvm-svn: 115643
2010-10-05 18:01:23 +00:00
8ccdd25fbd
test/COFF: Fix symbol indexes and names. Update tests to match.
...
llvm-svn: 115642
2010-10-05 17:57:08 +00:00
f6230d1d4b
test/COFF: Remove temp file usage.
...
llvm-svn: 115641
2010-10-05 17:56:56 +00:00
868aaf3c3d
Cleanup Whitespace.
...
llvm-svn: 115639
2010-10-05 17:56:37 +00:00
d03e81dba8
Produce a undefined reference to _GLOBAL_OFFSET_TABLE_ when needed.
...
llvm-svn: 115623
2010-10-05 15:48:37 +00:00
259bcdad06
Tests that now pass.
...
llvm-svn: 115622
2010-10-05 15:43:32 +00:00
6296bbbb65
Added a testcase for the ENTER instruction.
...
llvm-svn: 115580
2010-10-05 00:21:40 +00:00
fd1fff8b19
Implement ELF::R_X86_64_GOTPCREL.
...
llvm-svn: 115547
2010-10-04 19:51:39 +00:00
baadbd554a
Produce a R_X86_64_PLT32 when needed.
...
llvm-svn: 115541
2010-10-04 19:04:13 +00:00
b2c4ca6433
Produce a R_X86_64_GOT32 when needed.
...
llvm-svn: 115537
2010-10-04 18:44:25 +00:00
87f77b5f9a
Add hook in MCSection to decide when to use "optimized nops", for each
...
section kind. Previously, optimized nops were only used for MachO.
Also added tests for ELF and COFF.
llvm-svn: 115523
2010-10-04 17:32:41 +00:00
da0e3d07b2
Include the section address in the computation of the relocation.
...
llvm-svn: 115509
2010-10-04 15:59:01 +00:00
7c48b06930
Correctly compute the relocation when it is not in the first fragment.
...
llvm-svn: 115506
2010-10-04 15:28:43 +00:00
bb48e26732
Add 3DNowA instructions.
...
llvm-svn: 115477
2010-10-03 20:23:13 +00:00
d3593c3a8e
the immediate field of pshufw is actually an 8-bit field, not a 8-bit field that is sign extended. This fixes PR8288
...
llvm-svn: 115473
2010-10-03 19:09:13 +00:00
b44b202d66
add support for the prefetch/prefetchw instructions, move femms into
...
the right file. The assembler supports all the 3dnow instructions now,
but not the "3dnowa" ones.
llvm-svn: 115468
2010-10-03 18:42:30 +00:00
3a0a620c2e
what the heck, add support for the rest of the 3dNow! binary operations.
...
llvm-svn: 115467
2010-10-03 18:24:18 +00:00
45270db916
Implement support for the bizarre 3DNow! encoding (which is unlike anything
...
else in X86), and add support for pavgusb. This is apparently the
only instruction (other than movsx) that is preventing ffmpeg from building
with clang.
If someone else is interested in banging out the rest of the 3DNow!
instructions, it should be quite easy now.
llvm-svn: 115466
2010-10-03 18:08:05 +00:00
f70b4e0c2e
Implement a very basic PIC case.
...
llvm-svn: 115454
2010-10-03 00:46:57 +00:00
4756bbeba0
fix a regression introduced in r115243, in which the instruction
...
backing int_x86_ssse3_pshuf_w got removed. This caused PR8280.
llvm-svn: 115422
2010-10-02 21:32:15 +00:00
a2f2c27b20
actually, move the elf tests into the existing elf dir.
...
llvm-svn: 115416
2010-10-02 18:53:48 +00:00
7b1638b40b
consolidate ELF tests into asmparser tests.
...
llvm-svn: 115415
2010-10-02 18:52:57 +00:00
fbae9435c9
move ARM MC tests up one level.
...
llvm-svn: 115414
2010-10-02 18:52:05 +00:00
4ca7bb52d0
move X86 subdir up a level
...
llvm-svn: 115292
2010-10-01 04:32:20 +00:00
f987d5ea1c
Factor some logic into ShouldRelocOnSymbol. This simplifies the code and
...
fixes some cases where we were producing relocations with at symbol that
should use a section instead.
llvm-svn: 115194
2010-09-30 20:18:35 +00:00
1dee57fb7d
more cleanups.
...
llvm-svn: 115178
2010-09-30 17:29:05 +00:00
288a5f9652
merge and clean up tests.
...
llvm-svn: 115177
2010-09-30 17:24:05 +00:00
60217e765e
merge two tests.
...
llvm-svn: 115175
2010-09-30 17:18:22 +00:00
41a0cd14b7
rename test
...
llvm-svn: 115174
2010-09-30 17:16:49 +00:00
ea226b24ff
generalize test.
...
llvm-svn: 115172
2010-09-30 17:15:42 +00:00
28307d1a1e
rename test.
...
llvm-svn: 115171
2010-09-30 17:14:55 +00:00
45a52f3c34
merge two tests.
...
llvm-svn: 115170
2010-09-30 17:14:30 +00:00
73a7caee4b
preemptively add the rest of the non-n fpstack instructions.
...
llvm-svn: 115168
2010-09-30 17:11:29 +00:00
28b3b43fb4
merge two tests.
...
llvm-svn: 115165
2010-09-30 17:05:37 +00:00
1e9e49f421
fix this to not be completely broken.
...
llvm-svn: 115164
2010-09-30 17:04:59 +00:00
c8f0e29b5e
update, unxfail, fix bogus encodings.
...
llvm-svn: 115163
2010-09-30 17:03:20 +00:00
a9e913e139
update and unxfail
...
llvm-svn: 115162
2010-09-30 17:00:53 +00:00
ccf2c765f0
unxfail this by fixing syntactic differences.
...
llvm-svn: 115161
2010-09-30 16:59:28 +00:00
4373badcdf
implement support for finit, PR8258
...
llvm-svn: 115156
2010-09-30 16:42:53 +00:00
adc0dbe470
add support for fstcw, PR8259
...
llvm-svn: 115154
2010-09-30 16:39:29 +00:00
efbdbe5565
Move logic of determining ELF entsize from the .s printer to initialization
...
time. That way, the EntrySize field is initialized for other code paths,
namely, the .ll -> .o code path.
llvm-svn: 115141
2010-09-30 05:59:22 +00:00
9d98ac645e
Add another test that now passes.
...
llvm-svn: 115137
2010-09-30 04:22:07 +00:00
70d6e0e0ff
Correctly produce R_X86_64_32 or R_X86_64_32S.
...
With this patch in
movq $foo, foo(%rip)
foo:
.long foo
We produce a R_X86_64_32S for the first relocation and R_X86_64_32 for the
second one.
llvm-svn: 115134
2010-09-30 03:11:42 +00:00
b96b2d8e4d
Have ELFAsmParser.cpp use the already parsed "Size" (entry size) when
...
constructing a section. Test for a few cases also included.
llvm-svn: 115132
2010-09-30 02:41:46 +00:00
2ebaee9c75
Make it possible for the MCObjectWriter to decide if a given fixup is fully
...
resolved or not. Different object files have different restrictions and
different native assemblers have different idiosyncrasies we want to emulate
for now.
Move the existing MachO logic to the new place and implement an ELF one that
gets fixups to globals right.
llvm-svn: 115131
2010-09-30 02:22:20 +00:00
2b43c1cf42
implement rdar://8491845 - Gas supports commuted forms of non-commutable instructions.
...
llvm-svn: 115061
2010-09-29 18:39:16 +00:00
53f0bf194a
Move "local commons" to the end of .bss to match the gnu as behavior.
...
llvm-svn: 115037
2010-09-29 14:52:01 +00:00
68e05d404a
Add a test that I forgot to add with a previous commit.
...
llvm-svn: 115036
2010-09-29 14:40:49 +00:00
8f7851d2b4
fix rdar://8490728 - llvm-mc rejects gpr64 form of 'movmskpd'
...
llvm-svn: 115029
2010-09-29 05:05:03 +00:00
52e6020883
add assembler support for the cvtsd2sil/cvtsd2siq mnemonics, rdar://8456382
...
llvm-svn: 115027
2010-09-29 04:55:40 +00:00
822dc48c3a
MC-COFF: Fix test. IMAGE_SYM_CLASS_LABEL should never have been emitted.
...
llvm-svn: 115024
2010-09-29 03:59:25 +00:00
5da7f9fcfd
make the x86 mccode emitter emit the 0x67 and 0x66 prefix bytes in the same
...
order as cctools for diffability.
llvm-svn: 115022
2010-09-29 03:43:43 +00:00
a4e1c74947
implement support for 32-bit address operands in 64-bit mode, which
...
are defined to emit the 0x67 prefix byte. rdar://8482675
llvm-svn: 115021
2010-09-29 03:33:25 +00:00
f60062fd55
add basic avx support to the disassembler, also teach it about ssmem/sdmem
...
operands.
With this done, we can remove the _Int suffixes from the round instructions
without the disassembler blowing up. This allows the assembler to support
them, implementing rdar://8456376 - llvm-mc rejects 'roundss'
llvm-svn: 115019
2010-09-29 02:57:56 +00:00
ff3a3930a0
add asmparser support for cvttpd2dq by removing some Int_ prefixes.
...
Clean up cvttps2dq by removing some redundant implementations of the
same instruction. rdar://8456382
llvm-svn: 115018
2010-09-29 02:36:32 +00:00
ef1c2fc305
implement rdar://8456382 - cvtsd2si support, by removing some Int_ prefixes.
...
llvm-svn: 115017
2010-09-29 02:24:57 +00:00
a63292a3ca
implement rdar://8456378 and PR7557 - support for the fstsw,
...
an instruction that requires a WHOLE NEW wonderful kind of alias.
llvm-svn: 115015
2010-09-29 01:50:45 +00:00
01d20a76fe
On elf, undefined symbols can start with .L.
...
llvm-svn: 114958
2010-09-28 16:19:11 +00:00
96bfb50c03
Write relocations in the end of the file. This matches what gas does and
...
makes files easier to diff.
llvm-svn: 114898
2010-09-27 22:04:54 +00:00
9ca41113f6
Make sure .text doesn't produce extra alignment.
...
llvm-svn: 114895
2010-09-27 21:40:27 +00:00
d116d8a4e9
MC/AsmParser: Handle exponents in floating point literals.
...
llvm-svn: 114861
2010-09-27 20:12:52 +00:00
d628377a2d
MC-COFF: Drop empty sections, and label symbols. Convert relocations
...
targeted at symbols into relocations relative to the containing section.
Patch by Nathan Jeffords!
llvm-svn: 114823
2010-09-27 08:58:26 +00:00
b6a7f97c88
yet more aliases.
...
llvm-svn: 114822
2010-09-27 07:24:57 +00:00
882626cd5b
add a couple more aliases, rdar://8456378
...
llvm-svn: 114821
2010-09-27 07:21:41 +00:00
972c60d821
fix rdar://8470918 - llvm-mc can't assemble smovl
...
llvm-svn: 114819
2010-09-27 07:11:53 +00:00
ff0062af62
Fix rdar://8468087 - llvm-mc commutes fmul (and friend) operands.
...
My previous fix for rdar://8456371 should only apply to fmulp/faddp,
not to fmul/fadd. Instruction set orthogonality is overrated or
something.
llvm-svn: 114818
2010-09-27 07:08:21 +00:00
4f59cbfb66
implement support for 'clr' alias. This is part of rdar://8416805,
...
but balrog was wanting it on irc.
llvm-svn: 114809
2010-09-27 04:23:03 +00:00
75d65b9a03
Move ELF to HasReliableSymbolDifference=true. Also take the opportunity to put
...
symbols defined in merge sections in independent atoms.
llvm-svn: 114786
2010-09-25 05:42:19 +00:00
cf1f985838
Reapply 114678 and 114667. Reverting them did not fix the bot:
...
http://google1.osuosl.org:8011/builders/llvm-gcc-i386-linux-selfhost/builds/69
llvm-svn: 114761
2010-09-24 21:19:03 +00:00
3843bb9d2c
Revert 114678 and 114667 to see if
...
http://google1.osuosl.org:8011/builders/llvm-gcc-i386-linux-selfhost
gets happy.
llvm-svn: 114742
2010-09-24 18:48:08 +00:00
ce17f72c38
MC/AsmParser: Handle a missed case of floating literals in the lexer.
...
llvm-svn: 114733
2010-09-24 17:10:26 +00:00
2af1653032
MC/AsmParser: Support .single and .double for embedding floating point literals.
...
- I believe more modern 'gas' supports a more enhanced set of arithmetic on
them, but for now the only thing we can do is emit them as data.
llvm-svn: 114719
2010-09-24 01:59:56 +00:00
f458f04eb1
Correctly handle weak undefined symbols. Before we would get a invalid binding
...
(2 == STB_WEAK | STB_GLOBAL).
llvm-svn: 114690
2010-09-23 19:55:14 +00:00
48e108753b
Represent relocations against local symbols as relocations against the section
...
they are in. Both ways should be equivalent, but gas produces relocations
against the section.
Roman wrote the patch, I added the test.
llvm-svn: 114667
2010-09-23 17:25:18 +00:00
dee12d8110
Avoid some Mach-O specific alignment being done on ELF.
...
llvm-svn: 114594
2010-09-22 22:27:05 +00:00
9bac6cb544
Correctly align bss.
...
llvm-svn: 114556
2010-09-22 17:43:04 +00:00
415624cf3f
fix rdar://8456371 - Handle commutable instructions written backward.
...
llvm-svn: 114536
2010-09-22 06:26:39 +00:00
bd85725341
Fix an inconsistency in the x86 backend that led it to reject "calll foo" on
...
x86-32: 32-bit calls were named "call" not "calll". 64-bit calls were correctly
named "callq", so this only impacted x86-32.
This fixes rdar://8456370 - llvm-mc rejects 'calll'
This also exposes that mingw/64 is generating a 32-bit call instead of a 64-bit call,
I will file a bugzilla.
llvm-svn: 114534
2010-09-22 05:49:14 +00:00
37fc469f88
fix rdar://8456412 - llvm-mc crash in encoder on "mov %rdx, %cr8"
...
Teaching the code generator about CR8-15, how to rex them up, etc.
llvm-svn: 114533
2010-09-22 05:29:50 +00:00
2bb9504d1a
fix rdar://8456417 - llvm-mc can't do basic math
...
llvm-svn: 114532
2010-09-22 05:05:16 +00:00
9dfd2e354e
add the missing aliases for fp stack cmovs, rdar://8456391
...
llvm-svn: 114531
2010-09-22 04:56:20 +00:00
1261b81e82
Fix rdar://8456364 - llvm-mc rejects '%CS'
...
llvm-svn: 114528
2010-09-22 04:11:10 +00:00
39cf8deded
fix rdar://8456389 - llvm-mc mismatch with 'as' on 'fstp'
...
-This line, and those below, will be ignored--
M test/MC/AsmParser/X86/x86_instructions.s
M lib/Target/X86/AsmParser/X86AsmParser.cpp
llvm-svn: 114527
2010-09-22 04:04:03 +00:00
a91e510f94
fix rdar://8456361 - llvm-mc rejects 'rep movsd'
...
llvm-svn: 114526
2010-09-22 03:50:32 +00:00
f0591c1642
Implement support for .local and its "interesting" interactions with .comm.
...
llvm-svn: 114382
2010-09-21 00:24:38 +00:00
32ab4558fe
Produce a R_X86_64_32 when the value is >=0.
...
llvm-svn: 114339
2010-09-20 19:20:47 +00:00
57e599a82a
Make sure the STT_FILE symbol is the first one in the symbol table.
...
llvm-svn: 114285
2010-09-18 15:03:21 +00:00
15829c6c4c
Add test that was missing in my previous commit.
...
llvm-svn: 114248
2010-09-18 00:37:27 +00:00
de636ca9a8
Fix vmov.f64 disassembly on targets where sizeof(long) != 8.
...
llvm-svn: 114240
2010-09-17 23:48:07 +00:00
cea0a8d7ae
fix rdar://8444631 - encoder crash on 'enter'
...
What a weird instruction.
llvm-svn: 114190
2010-09-17 18:02:29 +00:00
35a7a0ee2e
MC/Mach-O/i386: Fix a crash in relocation handling.
...
llvm-svn: 114176
2010-09-17 15:21:50 +00:00
55f16678e4
MC/AsmParser: Add support for 'a + 4@GOTPCREL' and friends, by reconsing the
...
expression to include the modifier.
- Gross, but this a corner case we don't expect to see often in practice, but
it is worth accepting.
- Also improves diagnostics on invalid modifiers.
llvm-svn: 114154
2010-09-17 02:47:07 +00:00
74d320db97
fix rdar://8438816 - unrecognized 'fildq' instruction
...
llvm-svn: 114116
2010-09-16 20:46:38 +00:00
44bf266111
Print the address of sections as 0 and create the metadata sections in the
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same order as gnu as.
llvm-svn: 114109
2010-09-16 19:46:31 +00:00
f7f433200b
Make sure that names like .note.GNU-stack are accepted as valid section names.
...
llvm-svn: 114091
2010-09-16 17:05:55 +00:00
922e3f454b
Add support for the .zero directive.
...
llvm-svn: 114077
2010-09-16 15:03:59 +00:00
196841144d
add a test of an edge case value for the FP immediate (needs all digits of
...
precision)
llvm-svn: 114028
2010-09-15 21:52:13 +00:00
f667d929ce
Add a InitSections method to the streamer interface.
...
The ELF implementation now creates text, data and bss to match the gnu as
behavior.
The text streamer still has the old MachO specific behavior since
the testsuite checks that it will error when a directive is given
before a setting the current section for example.
A nice benefit is that -n is not required anymore when producing
ELF files.
llvm-svn: 114027
2010-09-15 21:48:40 +00:00
27ab5fbd2b
Teach the MC disassembler to handle vmov.f32 and vmov.f64 immediate to register
...
moves. Previously, the immediate was printed as the encoded integer value,
which is incorrect.
llvm-svn: 114021
2010-09-15 21:04:54 +00:00
ee7e6f42f8
lcall and ljmp always default to lcalll and ljmpl. This finally
...
wraps up r8418316
llvm-svn: 113949
2010-09-15 05:30:20 +00:00
09bfe645f6
apparently jmpl $1,$2 is an alias for ljmpl, similiarly
...
for call. Add this.
llvm-svn: 113948
2010-09-15 05:25:21 +00:00
6757eae45e
Disambiguate lcall/ljmp to the 32-bit version. This happens
...
even in 64-bit mode apparently.
llvm-svn: 113945
2010-09-15 05:14:54 +00:00
5be87c619b
fix the encoding of sldt GR16 to have the 0x66 prefix, and
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add sldt GR32, which isn't documented in the intel manual
but which gas accepts. Part of rdar://8418316
llvm-svn: 113938
2010-09-15 04:45:10 +00:00
6b40b0def1
implement aliases for shld/shrd, part of rdar://8418316
...
llvm-svn: 113937
2010-09-15 04:37:18 +00:00
4bd21710b6
fix rdar://8431880 - rcl/rcr with no shift amount not recognized
...
llvm-svn: 113936
2010-09-15 04:33:27 +00:00
81ce173860
add various broken forms of fnstsw. I didn't add the %rax
...
version because it adds a prefix and makes even less sense
than the other broken forms. This wraps up rdar://8431422
llvm-svn: 113932
2010-09-15 04:15:16 +00:00
7df35dbd19
add some aliases for f[u]comi, part of rdar://8431422
...
llvm-svn: 113930
2010-09-15 04:08:38 +00:00
4dbcba0082
add a bunch of aliases for fp operations with no operand,
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rdar://8431422
llvm-svn: 113929
2010-09-15 04:04:33 +00:00
46d4cc2ef7
test: Fix coff-dump section array indicies to 1 based to match file format.
...
llvm-svn: 113928
2010-09-15 03:58:51 +00:00
c7cf42d80b
Reapply r113875 with additional cleanups.
...
"The register specified for a dregpair is the corresponding Q register, so to
get the pair, we need to look up the sub-regs based on the qreg. Create a
lookup function since we don't have access to TargetRegisterInfo here to
be able to use getSubReg(ARM::dsub_[01])."
Additionaly, fix the NEON VLD1* and VST1* instruction patterns not to use
the dregpair modifier for the 2xdreg versions. Explicitly specifying the two
registers as operands is more correct and more consistent with the other
instruction patterns. This enables further cleanup of special case code in the
disassembler as a nice side-effect.
llvm-svn: 113903
2010-09-14 23:54:06 +00:00
5f2311dc29
add a terrible hack to allow out with dx is parens, a gas bug.
...
This fixes PR8114
llvm-svn: 113894
2010-09-14 23:34:29 +00:00
1bbb14ab8f
add a missed cmov alias, part of rdar://8416805
...
llvm-svn: 113693
2010-09-11 17:08:22 +00:00
3340c3e86c
add support for all the setCC aliases. Part of rdar://8416805
...
llvm-svn: 113692
2010-09-11 17:06:05 +00:00
12d73d1f18
Add support for leb128 of absolute expressions.
...
llvm-svn: 113691
2010-09-11 16:45:15 +00:00
b47c042e09
add support for pushfd/popfd which are aliases for pushfl/popfl.
...
This fixes rdar://8408129 - pushfd and popfd get invalid instruction mnemonic errors
llvm-svn: 113690
2010-09-11 16:39:16 +00:00
30561aba20
implement rdar://8407928 - support for in/out with a missing "a" register.
...
llvm-svn: 113689
2010-09-11 16:32:12 +00:00
2833e392ab
Change section_data dumping to print hex numbers instead of using
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python's %r.
llvm-svn: 113685
2010-09-11 15:25:58 +00:00
e5444a88cd
llvm-mc: Don't crash when using -n and we see a directive before the initial section.
...
- This is annoying, because we have to scatter this check everywhere that could emit real data, but I see no better solution.
llvm-svn: 113552
2010-09-09 22:42:59 +00:00
43325c4a68
llvm-mc: Make sure we exit != 0 if any errors are encountered.
...
llvm-svn: 113551
2010-09-09 22:42:56 +00:00
0a96578ac0
Add an elf-dumper utility.
...
- Output format and some of the code stolen from macho-dump.
- Somewhat incomplete and probably buggy.
- Comes with a very basic test.
llvm-svn: 113488
2010-09-09 15:00:41 +00:00
28a9c2f89a
fix rdar://8407548, I missed the commuted form of xchg/test without a suffix.
...
llvm-svn: 113427
2010-09-08 22:27:05 +00:00
8ead237758
fix bugs in push/pop segment support, rdar://8407242
...
llvm-svn: 113422
2010-09-08 22:13:08 +00:00
2907d2e419
add support for the commuted form of the test instruction, rdar://8018260.
...
llvm-svn: 113352
2010-09-08 05:51:12 +00:00
a9ca7837e4
implement proper support for sysret{,l,q}, rdar://8403907
...
llvm-svn: 113350
2010-09-08 05:45:34 +00:00
063363fa80
implement the iret suite of instructions properly,
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fixing rdar://8403974
llvm-svn: 113349
2010-09-08 05:38:31 +00:00
086a83afb1
add support for instruction prefixes on the same line as the instruction,
...
implementing rdar://8033482 and PR7254.
llvm-svn: 113348
2010-09-08 05:17:37 +00:00
8caea68a4f
gas accepts xchg <mem>, <reg> as a synonym for xchg <reg>, <mem>.
...
Add this to the mc assembler, fixing PR8061
llvm-svn: 113346
2010-09-08 04:53:27 +00:00
4703cb4a96
fix the encoding of the "jump on *cx" family of instructions,
...
rdar://8061602
llvm-svn: 113343
2010-09-08 04:30:51 +00:00
30bb384944
add missing cmov aliases, this resolves rdar://8208499
...
llvm-svn: 113189
2010-09-07 00:05:45 +00:00
7ece716da2
"sldt <mem>" is ambiguous in 64-bit mode, but should
...
always be disambiguated as sldtw. sldtw and sldtq with
a mem operands have the same effect, but sldtw is more
compact. Force it to sldtw, resolving rdar://8017530
llvm-svn: 113186
2010-09-06 23:51:44 +00:00
415e04fad2
fix rdar://8017621 - llvm-mc can't guess encoding for "push $(1000)"
...
llvm-svn: 113184
2010-09-06 23:40:56 +00:00
34e366b45c
fix the operand constraints of the immediate form of in/out,
...
allowing unsigned 8-bit operands. This fixes rdar://8208481
llvm-svn: 113182
2010-09-06 23:29:05 +00:00
e39017cb97
Add AsmParser support for the ELF .previous directive. Patch by Roman Divacky.
...
llvm-svn: 112849
2010-09-02 18:53:37 +00:00
d8e5dfccc1
COFF: Update tests to reflect changes in last commit.
...
llvm-svn: 112704
2010-09-01 14:15:31 +00:00
112b6ee3f2
fixme accomplished
...
llvm-svn: 112386
2010-08-28 20:40:28 +00:00
3d148ac089
X86: Fix misencode of RI64mi8. This fixes OpenSSL / x86_64-apple-darwin10 / clang -O3.
...
llvm-svn: 112089
2010-08-25 21:11:02 +00:00
ccd28d0665
Fix COFF x86-64 relocations. PR7960.
...
Multiple symbol reloc handling part of the patch by Cameron Esfahani.
llvm-svn: 111963
2010-08-24 21:04:52 +00:00
1c8d777c93
MC/X86: Tweak imul recognition, previous hack only applies for the imul form
...
taking immediates.
llvm-svn: 111950
2010-08-24 19:37:56 +00:00
09392785b4
MC/X86: Add custom hack for recognizing "imul $12, %eax" and friends.
...
llvm-svn: 111947
2010-08-24 19:24:18 +00:00
2476432639
MC/AsmParser: Change ParseExpression to use ParseIdentifier(), to support
...
dollars in identifiers.
llvm-svn: 111946
2010-08-24 19:13:42 +00:00
94b84a19b9
MC/X86: Warn on scale factors > 1 without index register, instead of erroring,
...
for 'as' compatibility.
llvm-svn: 111945
2010-08-24 19:13:38 +00:00
3b96ffdac1
MC/Parser: Accept leading dollar signs in identifiers.
...
- Implemented by manually splicing the tokens. If this turns out to be
problematically platform specific, a more elegant solution would be to
implement some context dependent lexing support.
llvm-svn: 111934
2010-08-24 18:12:12 +00:00
02db8f6415
fix rdar://7997827 - Accept and ignore LL and ULL suffixes on integer literals.
...
Also fix 0b010 syntax to actually work while we're at it :-)
llvm-svn: 111876
2010-08-24 00:43:25 +00:00
f547740d3f
fix PR7465, mishandling of lcall and ljmp: intersegment long
...
call and jumps.
llvm-svn: 111496
2010-08-19 01:18:43 +00:00
8e92d9b68d
MC/ELF: Allow null values in virtual sections, ELF doesn't use special
...
directives for putting contents in .bss, for example.
llvm-svn: 111376
2010-08-18 18:22:37 +00:00
942b10f511
Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoid
...
printing "lsl #0". This fixes the remaining parts of pr7792. Make
corresponding changes for encoding/decoding these instructions.
llvm-svn: 111251
2010-08-17 17:23:19 +00:00
4577f37d49
Add a Thumb2 t2RSBrr instruction for disassembly only.
...
This fixes another part of PR7792.
llvm-svn: 111057
2010-08-13 23:24:25 +00:00
15b3c3d0ac
Move the Thumb2 SSAT and USAT optional shift operator out of the
...
instruction opcode. This fixes part of PR7792.
llvm-svn: 111047
2010-08-13 21:48:10 +00:00
8e8f1c133a
Cleaned up the for-disassembly-only entries in the arm instruction table so that
...
the memory barrier variants (other than 'SY' full system domain read and write)
are treated as one instruction with option operand.
llvm-svn: 110951
2010-08-12 20:46:17 +00:00
74491bb52c
The autogened decoder was confusing the ARM STRBT for ARM USAT, because the .td
...
entry for ARM STRBT is actually a super-instruction for A8.6.199 STRBT A1 & A2.
Recover by looking for ARM:USAT encoding pattern before delegating to the auto-
gened decoder.
Added a "usat" test case to arm-tests.txt.
llvm-svn: 110894
2010-08-12 01:40:54 +00:00
7d7b4d1b0f
MC/X86/AsmParser: Give an explicit error message when we reject an instruction
...
because it could have an ambiguous suffix.
llvm-svn: 110890
2010-08-12 00:55:42 +00:00
d59c73f998
Changed the format of DMBsy, DSBsy, and friends from Pseudo to MiscFrm.
...
Added two test cases to arm-tests.txt.
llvm-svn: 110880
2010-08-11 23:35:12 +00:00
add513112a
Move the ARM SSAT and USAT optional shift amount operand out of the
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instruction opcode. This also fixes part of PR7792.
llvm-svn: 110875
2010-08-11 23:10:46 +00:00
188b47b214
MC/ARM: Add basic support for handling predication by parsing it out of the mnemonic into a separate operand form.
...
llvm-svn: 110794
2010-08-11 06:37:20 +00:00
d215976208
MC/AsmParser: Fix a bug in macro argument parsing, which was dropping
...
parentheses from argument lists.
llvm-svn: 110692
2010-08-10 17:38:52 +00:00
72de307116
Add an ARM RSCrr instruction for disassembly only.
...
Partial fix for PR7792.
llvm-svn: 110361
2010-08-05 18:59:36 +00:00
adb93e56a3
Add an ARM RSBrr instruction for disassembly only.
...
Partial fix for PR7792.
llvm-svn: 110358
2010-08-05 18:23:43 +00:00
57e3f71538
tests: Mark MC/AsmParser tests as requiring x86 for now -- almost all of them
...
rely on using a specific x86 triple to test what they want to test.
llvm-svn: 110337
2010-08-05 15:44:15 +00:00
97886d59d1
ARM "rrx" shift operands do not have an immediate. PR7790.
...
llvm-svn: 110292
2010-08-05 00:34:42 +00:00
54cfd42c33
MC: Fix symbol fragment offsets in COFF.
...
Patch by Cameron Esfahani!
llvm-svn: 110104
2010-08-03 05:02:46 +00:00
cd5fc7bef1
Add support for disassembling VMVN (immediate) instructions. PR7747.
...
llvm-svn: 109946
2010-07-31 05:57:44 +00:00
f8270bdb2d
Make MC use Windows COFF on Windows and add tests.
...
llvm-svn: 109494
2010-07-27 06:46:15 +00:00
306a1f9721
Support x86 "eiz" and "riz" pseudo index registers in the assembler.
...
llvm-svn: 109295
2010-07-24 00:06:39 +00:00
fbd7f65248
Consolidate the ELF section directive tests into a single file as
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suggested by Chris Lattner.
llvm-svn: 109290
2010-07-23 23:40:41 +00:00
6f38011196
Move AVX encoding tests to different files
...
llvm-svn: 109269
2010-07-23 21:25:26 +00:00
ea0e05a3ce
Add AVX version of CLMUL instructions
...
llvm-svn: 109248
2010-07-23 18:41:12 +00:00
acd9230b1b
Add complete assembler support for FMA3 instructions, with descriptions and encodings taken from the AVX manual
...
llvm-svn: 109204
2010-07-23 00:54:35 +00:00
0710c74f29
Add remaining AVX instructions (most of them dealing with GR64 destinations. This complete the assembler support for the general AVX ISA. But we still miss instructions from FMA3 and CLMUL specific feature flags, which are now the next step
...
llvm-svn: 109168
2010-07-22 21:18:49 +00:00
e3acfd4d58
Add more 256-bit forms for a bunch of regular AVX instructions
...
Add 64-bit (GR64) versions of some instructions (which are not
described in their SSE forms, but are described in AVX)
llvm-svn: 109063
2010-07-21 23:53:50 +00:00
6238c1d102
Add missing AVX convert instructions. Those instructions are not described in their SSE forms (although they exist), but add the AVX forms anyway, so the assembler can benefit from it
...
llvm-svn: 109039
2010-07-21 21:37:59 +00:00
cdbec62510
Add AVX only vzeroall and vzeroupper instructions
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llvm-svn: 109002
2010-07-21 08:56:24 +00:00
3499934da6
Add new AVX vpermilps, vpermilpd and vperm2f128 instructions
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llvm-svn: 108984
2010-07-21 03:07:42 +00:00
3ceaf7a0a2
Add new AVX vmaskmov instructions, and also fix the VEX encoding bits to support it
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llvm-svn: 108983
2010-07-21 02:46:58 +00:00
e706501975
Add new AVX vextractf128 instructions
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llvm-svn: 108964
2010-07-20 23:19:02 +00:00
c3eb5e3d4b
Include some tests for the recently committed ELF section directive
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handlers.
llvm-svn: 108938
2010-07-20 21:37:30 +00:00
3b505848fd
Add new AVX instruction vinsertf128
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llvm-svn: 108892
2010-07-20 19:44:51 +00:00
6c8041ea34
x86_32 tests for vbroadcast
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llvm-svn: 108789
2010-07-20 00:11:50 +00:00
14c5fd437c
Add AVX vbroadcast new instruction
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llvm-svn: 108788
2010-07-20 00:11:13 +00:00
9de0ca73d4
Add 256-bit vaddsub, vhadd, vhsub, vblend and vdpp instructions!
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llvm-svn: 108769
2010-07-19 23:32:44 +00:00
9db7d0addd
X86: Mark JMP{32,64}[mr] as requires 32-bit/64-bit mode. They are the same
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instruction, we only want to allow the one for the current subtarget.
- This also fixes suffix matching for jmp instructions, because it eliminates
the ambiguity between 'jmpl' and 'jmpq'.
llvm-svn: 108746
2010-07-19 20:44:16 +00:00
9aefb8ee4c
X86-64: Mark WINCALL and more tail call instructions as code gen only.
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llvm-svn: 108685
2010-07-19 07:21:07 +00:00
b82cd9319b
MC/X86: We now match instructions like "incl %eax" correctly for the arch we are
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assembling; remove crufty custom cleanup code.
llvm-svn: 108681
2010-07-19 06:14:54 +00:00
af75e1923c
tests: Force another triple.
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llvm-svn: 108666
2010-07-19 00:43:58 +00:00
3b4621103a
tests: Force triples.
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llvm-svn: 108658
2010-07-18 21:16:10 +00:00
40a564f09f
MC/AsmParser: Fix .abort and .secure_log_unique to accept arbitrary token
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sequences, not just strings.
llvm-svn: 108655
2010-07-18 20:15:59 +00:00
6fb1c3ad8a
MC/AsmParser: Add macro argument substitution support.
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llvm-svn: 108654
2010-07-18 19:00:10 +00:00
4323571efb
MC/AsmParser: Add basic support for macro instantiation.
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llvm-svn: 108653
2010-07-18 18:54:11 +00:00
c1f58ec83c
MC/AsmParser: Add basic parsing support for .macro definitions.
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llvm-svn: 108652
2010-07-18 18:47:21 +00:00
828984ff4e
MC/AsmParser: Add .macros_{off,on} support, not that makes sense since we don't
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support macros.
llvm-svn: 108649
2010-07-18 18:38:02 +00:00
ceb16a5ce9
Test for ELF .size directive.
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llvm-svn: 108607
2010-07-17 03:15:24 +00:00
6c6c14a55c
Add AVX 256-bit compare instructions and a bunch of testcases
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llvm-svn: 108286
2010-07-13 22:06:38 +00:00
fd8bfcd6e1
AVX 256-bit conversion instructions
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Add the x86 VEX_L form to handle special cases where VEX_L must be set.
llvm-svn: 108274
2010-07-13 21:07:28 +00:00
55595fb291
my work on adding segment registers to LEA missed the
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disassembler. Remove some code from the disassembler to
compensate, unbreaking disassembly of lea's.
llvm-svn: 108226
2010-07-13 04:23:55 +00:00
dff283e146
Add AVX 256-bit packed logical forms
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llvm-svn: 108224
2010-07-13 02:38:35 +00:00
36b32aeaa5
Add AVX 256-bit unop arithmetic instructions
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llvm-svn: 108223
2010-07-13 01:53:31 +00:00
8e67a0482e
Add AVX 256 binary arithmetic instructions
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llvm-svn: 108207
2010-07-12 23:04:15 +00:00
f9bcaad76d
Add AVX 256-bit MOVMSK forms
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llvm-svn: 108184
2010-07-12 20:06:32 +00:00
d388c93f87
MC/AsmParser: Move .tbss and .zerofill parsing to Darwin specific parser.
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llvm-svn: 108180
2010-07-12 19:37:35 +00:00
63a379dd5c
MC/AsmParser: Move .desc parsing to Darwin specific parser.
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llvm-svn: 108179
2010-07-12 19:22:53 +00:00
ae9da1481a
MC/AsmParser: Move some misc. Darwin directive handling to DarwinAsmParser.
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llvm-svn: 108174
2010-07-12 18:49:22 +00:00
2419606bfb
Add AVX 256-bit packed MOVNT variants
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llvm-svn: 108021
2010-07-09 21:42:42 +00:00
6bc772eec7
Add AVX 256-bit unpack and interleave
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llvm-svn: 108017
2010-07-09 21:20:35 +00:00
792e906bef
Start the support for AVX instructions with 256-bit %ymm registers. A couple of
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notes:
- The instructions are being added with dummy placeholder patterns using some 256
specifiers, this is not meant to work now, but since there are some multiclasses
generic enough to accept them, when we go for codegen, the stuff will be already
there.
- Add VEX encoding bits to support YMM
- Add MOVUPS and MOVAPS in the first round
- Use "Y" as suffix for those Instructions: MOVUPSYrr, ...
- All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX
file.
llvm-svn: 107996
2010-07-09 18:27:43 +00:00
9f034c1e5d
Rework segment prefix emission code to handle segments
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in memory operands at the same type as hard coded segments.
This fixes problems where we'd emit the segment override after
the REX prefix on instructions like:
mov %gs:(%rdi), %rax
This fixes rdar://8127102. I have several cleanup patches coming
next.
llvm-svn: 107917
2010-07-08 22:28:12 +00:00
ac5881295c
Implement the major chunk of PR7195: support for 'callw'
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in the integrated assembler. Still some discussion to be
done.
llvm-svn: 107825
2010-07-07 22:27:31 +00:00
6c61451011
Add more assembly opcodes for SSE compare instructions
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llvm-svn: 107823
2010-07-07 22:24:03 +00:00
fd8060335b
Add AVX AES instructions
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llvm-svn: 107798
2010-07-07 18:24:20 +00:00
6d122aef97
Add AVX SSE4.2 instructions
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llvm-svn: 107752
2010-07-07 03:39:29 +00:00
8f5472a8e8
Add AVX SSE4.1 insertps, ptest and movntdqa instructions
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llvm-svn: 107747
2010-07-07 01:14:56 +00:00
6430c7350d
Add AVX SSE4.1 extractps and pinsr instructions
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llvm-svn: 107746
2010-07-07 01:01:13 +00:00
f3116ebe96
Add AVX SSE4.1 Extract Integer instructions
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llvm-svn: 107740
2010-07-07 00:07:24 +00:00
1f9ad516c6
Add the rest of AVX SSE4.1 packed move with sign/zero extend instructions
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llvm-svn: 107723
2010-07-06 23:15:17 +00:00
35702d27c4
Add part of AVX SSE4.1 packed move with sign/zero extend instructions
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llvm-svn: 107720
2010-07-06 23:01:41 +00:00
e2bd058d32
Add AVX vblendvpd, vblendvps and vpblendvb instructions
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Update VEX encoding to support those new instructions
llvm-svn: 107715
2010-07-06 22:36:24 +00:00
ca99012ac0
Add AVX SSE4.1 blend, mpsadbw and vdp
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llvm-svn: 107560
2010-07-03 01:37:03 +00:00
bc75502f09
Add AVX SSE4.1 binop (some forms of packed max,min,mul,pack,cmp) instructions
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llvm-svn: 107558
2010-07-03 01:15:47 +00:00
fc9cdc4d61
Add AVX SSE4.1 Horizontal Minimum and Position instruction
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llvm-svn: 107552
2010-07-03 00:49:21 +00:00
621c85b038
Add AVX SSE4.1 round instructions
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llvm-svn: 107549
2010-07-03 00:37:44 +00:00
c7111fd355
- Add support for the rest of AVX SSE3 instructions
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- Fix VEX prefix to be emitted with 3 bytes whenever VEX_5M
represents a REX equivalent two byte leading opcode
llvm-svn: 107523
2010-07-02 22:06:54 +00:00
5e88700f28
Move SSE3 Move patterns to a more appropriate section
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Add AVX SSE3 packed horizontal and & sub instructions
llvm-svn: 107405
2010-07-01 17:35:02 +00:00
886ee33a38
Add AVX SSE3 packed addsub instructions
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llvm-svn: 107404
2010-07-01 17:08:18 +00:00
a7a0c83563
Add AVX SSE3 replicate and convert instructions
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llvm-svn: 107375
2010-07-01 02:33:39 +00:00
Sean Callanan