Commit Graph

70276 Commits

Author SHA1 Message Date
Matt Arsenault 1578aa78d4 R600: Move division custom lowering out of AMDILISelLowering
llvm-svn: 210997
2014-06-15 20:08:02 +00:00
Eric Christopher f6db93ab81 Temporarily revert r210953 in an attempt to bring the ARM buildbots
back.

llvm-svn: 210996
2014-06-15 19:55:14 +00:00
Matt Arsenault cf9a9a148e R600: Report that integer division is expensive.
Divides by weird constants now emit much better code.

llvm-svn: 210995
2014-06-15 19:48:16 +00:00
Matt Arsenault 66ee0816da R600: Remove dead code
llvm-svn: 210994
2014-06-15 19:48:13 +00:00
David Blaikie b9597a8e57 PR20038: DebugInfo missing DIEs for some concrete variables.
I haven't nailed this down entirely, but this is about as small of a
test case as I can seem to construct and adequately demonstrates the
crasher. I'll continue investigating the root cause/fix(es).

llvm-svn: 210993
2014-06-15 19:34:26 +00:00
Tim Northover 65277a2bc0 LegalizeDAG: make sure cast is unsigned before using FP_TO_UINT.
It's valid to use FP_TO_SINT when asking for a smaller type (e.g. all
"unsigned int16" values fit into a "signed int32"), but the reverse
isn't true.

Unfortunately, I'm not actually aware of any architecture with
asymmetric FP_TO_SINT and FP_TO_UINT handling and the logic happens to
work in the symmetric case, so I can't actually write a test for this.

llvm-svn: 210986
2014-06-15 09:27:20 +00:00
Tim Northover dbecc3b3fc AArch64: improve handling & modelling of FP_TO_XINT nodes.
There's probably no acatual change in behaviour here, just updating
the LowerFP_TO_INT function to be more similar to the reverse
implementation and updating costs to current CodeGen.

llvm-svn: 210985
2014-06-15 09:27:15 +00:00
Tim Northover ef0d760cd9 AArch64: improve vector [su]itofp handling.
This somehow got missed in the AArch64 merge, so should fix a
performance regression since 3.4.

llvm-svn: 210984
2014-06-15 09:27:06 +00:00
Artyom Skrobov c7b4253cfb Replacing the private implementations of SwapValue with calls to sys::swapByteOrder()
llvm-svn: 210980
2014-06-14 13:49:57 +00:00
Artyom Skrobov 9aea8432c5 Using llvm::sys::swapByteOrder() for the common case of byte-swapping a value in place
llvm-svn: 210978
2014-06-14 13:18:07 +00:00
Artyom Skrobov ef5e867f16 Renaming SwapByteOrder() to getSwappedBytes()
The next commit will add swapByteOrder(), acting in-place

llvm-svn: 210973
2014-06-14 11:36:01 +00:00
Matt Arsenault b2e8744eeb Fix typo
llvm-svn: 210968
2014-06-14 04:26:07 +00:00
Matt Arsenault e682a19a1c R600: Fix asserts related to constant initializers
This would assert if a constant address space was extern
and therefore didn't have an initializer. If the initializer
was undef, it would hit the unreachable unhandled initializer case.

An extern global should never really occur since we don't have
machine linking, but bugpoint likes to remove initializers.

llvm-svn: 210967
2014-06-14 04:26:05 +00:00
Matt Arsenault 41aa27c96b R600: Use address space enum instead of value
llvm-svn: 210966
2014-06-14 04:26:01 +00:00
Nick Lewycky b06a796051 Remove extra whitespace in function declaration. No functionality change.
llvm-svn: 210965
2014-06-14 03:48:29 +00:00
David Blaikie 6f9e867c45 DebugInfo: Remove some extra handling of abstract variables and instead rely solely on the delayed handling introduced in r210946
Now that we handle finding abstract variables at the end of the module,
remove the upfront handling and just ensure the abstract variable is
built when necessary.

In theory we could have a split implementation, where inlined variables
are immediately constructed referencing the abstract definition, and
concrete variables are delayed - but let's go with one solution for now
unless there's a reason not to.

llvm-svn: 210961
2014-06-13 23:52:55 +00:00
Eric Christopher fb0c26c696 Remove InstrItineraryData off of the TargetMachine - it's already
on the subtarget and just forward the accessor.

llvm-svn: 210955
2014-06-13 23:11:13 +00:00
Eric Christopher a0cdc005dd Move ARMJITInfo off of the TargetMachine and down onto the subtarget.
This required untangling a mess of headers that included around.

llvm-svn: 210953
2014-06-13 23:04:46 +00:00
Jiangning Liu 96e92c1d75 Move GlobalMerge from Transform to CodeGen.
This patch is to move GlobalMerge pass from Transform/Scalar                                                           
to CodeGen, because GlobalMerge depends on TargetMachine.
In the mean time, the macro INITIALIZE_TM_PASS is also moved
to CodeGen/Passes.h. With this fix we can avoid making
libScalarOpts depend on libCodeGen.

llvm-svn: 210951
2014-06-13 22:57:59 +00:00
Eric Christopher f047bfd115 The hazard recognizer only needs a subtarget, not a target machine
so make it take one. Fix up all users accordingly.

llvm-svn: 210948
2014-06-13 22:38:52 +00:00
Eric Christopher 170ebcf07f Fix typo.
llvm-svn: 210947
2014-06-13 22:38:48 +00:00
David Blaikie e847f132f7 DebugInfo: Reference abstract definitions from variables in concrete definitions that preceed their first inline definition.
Rather than relying on abstract variables looked up at the time the
concrete variable is created, look them up at the end of the module to
ensure they're referenced even if they're created after the concrete
definition. This completes/matches the work done in r209677 to handle
this for the subprograms themselves.

llvm-svn: 210946
2014-06-13 22:35:44 +00:00
Alexey Samsonov aa90998c87 [DWARF parser] Use distinction between DW_AT_ranges_base and DW_AT_GNU_ranges_base instead of DWARF version
llvm-svn: 210945
2014-06-13 22:31:03 +00:00
David Blaikie be7c677008 DwarfDebug::getExistingAbstractVariable: constify an existing reference parameter that didn't need to be mutated.
llvm-svn: 210944
2014-06-13 22:29:31 +00:00
David Blaikie eb1a27239c DebugInfo: Following up to r209677, refactor local variable emission to delay the choice between emitting the definition attributes or using DW_AT_abstract_definition
This doesn't fix the abstract variable handling yet, but it introduces a
similar delay mechanism as was added for subprograms, causing
DW_AT_location to be reordered to the beginning of the attribute list
for local variables, and fixes all the test fallout for that.

A subsequent commit will remove the abstract variable handling in
DbgVariable and just do the abstract variable lookup at module end to
ensure that abstract variables introduced after their concrete
counterparts are appropriately referenced by the concrete variable.

llvm-svn: 210943
2014-06-13 22:18:23 +00:00
Zachary Turner 586fd74c30 Make the error-handling functions thread-safe.
Prior to this change, error handling functions must be installed
and removed only inside of an llvm_[start/stop]_multithreading
pair.  This change allows error handling functions to be installed
any time, and from any thread.

Reviewed by: chandlerc

Differential Revision: http://reviews.llvm.org/D4140

llvm-svn: 210937
2014-06-13 21:20:44 +00:00
Alexey Samsonov e595e1ade0 Remove top-level Clang -fsanitize= flags for optional ASan features.
Init-order and use-after-return modes can currently be enabled
by runtime flags. use-after-scope mode is not really working at the
moment.

The only problem I see is that users won't be able to disable extra
instrumentation for init-order and use-after-scope by a top-level Clang flag.
But this instrumentation was implicitly enabled for quite a while and
we didn't hear from users hurt by it.

llvm-svn: 210924
2014-06-13 17:53:44 +00:00
Tim Northover 51472bc600 X86: lower ATOMIC_CMP_SWAP_WITH_SUCCESS directly
Lowering this new node allows us to fold the almost universal
comparison for success before it's even formed. Instead we can create
a copy from EFLAGS and an X86ISD::SETCC operation since all "cmpxchg"
instructions set the zero-flag to the correct value.

rdar://problem/13201607

llvm-svn: 210923
2014-06-13 17:29:39 +00:00
Matt Arsenault fd8c24ede8 R600: Cleanup some old AMDIL stuff.
Move / delete some of the more obviously wrong
setOperationAction calls. Most of these are setting Expand
for types that aren't legal which is the default anyway.
Leave stuff that might require more thought on whether it's
junk or not as it is.

No functionality change.

llvm-svn: 210922
2014-06-13 17:20:53 +00:00
Rafael Espindola 2a826e40fa Finishing touch for the std::error_code transition.
While std::error_code itself seems to work OK in all platforms, there
are few annoying differences with regards to the std::errc enumeration.

This patch adds a simple llvm enumeration, which will hopefully avoid build
breakages in other platforms and surprises as we get more uses of
std::error_code.

llvm-svn: 210920
2014-06-13 17:20:48 +00:00
Tim Northover 20b9f739eb Atomics: make use of the "cmpxchg weak" instruction.
This also simplifies the IR we create slightly: instead of working out
where success & failure should go manually, it turns out we can just
always jump to a success/failure block created for the purpose. Later
phases will sort out the mess without much difficulty.

llvm-svn: 210917
2014-06-13 16:45:52 +00:00
Tim Northover d039abdeeb Atomics: switch direction of cmpxchg comparison
This has two benefits: it makes the result more suitable for direct
insertaion into the struct to emulate the new cmpxchg, and it means
the name we give the instruction matches its actual effect better.

llvm-svn: 210916
2014-06-13 16:45:36 +00:00
Tom Stellard bc5b5370de R600: Remove AMDIL instruction and register definitions
Most of these are no longer used any more.

llvm-svn: 210915
2014-06-13 16:38:59 +00:00
Rafael Espindola 54f1997979 Remove unused and odd code.
This code was never being used and any use of it would look fairly strange.
For example, it would try to map a object_error::parse_failed to
std::errc::invalid_argument.

llvm-svn: 210912
2014-06-13 15:36:17 +00:00
Tim Northover 6bf04e4512 SCCP: update for cmpxchg returning { iN, i1 } now.
I accidentally missed this one since its use looked OK locally.

llvm-svn: 210909
2014-06-13 14:54:09 +00:00
Zoran Jovanovic a5acdcf924 [mips][mips64r6] Relocation R_MIPS_PC18_S3
Differential Revision: http://reviews.llvm.org/D3890

llvm-svn: 210908
2014-06-13 14:26:47 +00:00
Tim Northover 420a216817 IR: add "cmpxchg weak" variant to support permitted failure.
This commit adds a weak variant of the cmpxchg operation, as described
in C++11. A cmpxchg instruction with this modifier is permitted to
fail to store, even if the comparison indicated it should.

As a result, cmpxchg instructions must return a flag indicating
success in addition to their original iN value loaded. Thus, for
uniformity *all* cmpxchg instructions now return "{ iN, i1 }". The
second flag is 1 when the store succeeded.

At the DAG level, a new ATOMIC_CMP_SWAP_WITH_SUCCESS node has been
added as the natural representation for the new cmpxchg instructions.
It is a strong cmpxchg.

By default this gets Expanded to the existing ATOMIC_CMP_SWAP during
Legalization, so existing backends should see no change in behaviour.
If they wish to deal with the enhanced node instead, they can call
setOperationAction on it. Beware: as a node with 2 results, it cannot
be selected from TableGen.

Currently, no use is made of the extra information provided in this
patch. Test updates are almost entirely adapting the input IR to the
new scheme.

Summary for out of tree users:
------------------------------

+ Legacy Bitcode files are upgraded during read.
+ Legacy assembly IR files will be invalid.
+ Front-ends must adapt to different type for "cmpxchg".
+ Backends should be unaffected by default.

llvm-svn: 210903
2014-06-13 14:24:07 +00:00
Daniel Sanders c171f65a87 [mips] Add cache and pref instructions
Summary:
cache and pref were added in MIPS-III, and MIPS32 but were re-encoded in
MIPS32r6/MIPS64r6 to use a 9-bit offset rather than the 16-bit offset
available to earlier cores.

Resolved the decoding conflict between pref and lwc3.

Depends on D4115

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4116

llvm-svn: 210900
2014-06-13 13:15:59 +00:00
Daniel Sanders af8b32e176 [mips][mips64r6] bc1any[24] are not available on MIPS32r6/MIPS64r6
Summary:
These MIPS-3D instructions have never been implemented in LLVM so we only
add testcases.

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4115

llvm-svn: 210899
2014-06-13 13:08:38 +00:00
Daniel Sanders 86cb398b9d [mips][mips64r6] b(ge|lt)zal are not available on MIPS32r6/MIPS64r6 and bal is a normal instruction
Summary:
b(ge|lt)zal have been removed in MIPS32r6/MIPS64r6. However, bal (an alias
for 'bgezal $zero, $offset') still remains with the same encoding it had
prior to MIPS32r6/MIPS64r6.

Updated the MipsNaCLELFStreamer, and MipsLongBranch to correctly handle the
MIPS32r6/MIPS64r6 BAL instruction in addition to the existing BAL_BR pseudo.

No changes were required to the CodeGen test that looks for BAL
(test/CodeGen/Mips/longbranch.ll) since the new instruction has the same
syntax.

Depends on D4113

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4114

llvm-svn: 210898
2014-06-13 13:02:52 +00:00
Daniel Sanders e898236bc2 [mips][mips64r6] daddi is not available on MIPS64r6
Summary:
It's not emitted by the code generator so we only need assembler tests.

Also added missing daddi aliases from dsub mnemonics, and removed a couple
duplicate dsub tests.

Depends on D4112

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4113

llvm-svn: 210897
2014-06-13 12:49:06 +00:00
Cameron McInally c43c8f9458 Add HasCDI predicate to AVX512 VPBROADCASTM*.
llvm-svn: 210892
2014-06-13 11:40:31 +00:00
Tim Northover 24fe2322a2 CPP backend: set volatile property on atomic instructions.
llvm-svn: 210890
2014-06-13 09:14:50 +00:00
Oliver Stannard b5e596f7c3 ARM: Fix fastcc calling convention for Thumb1
When targetting Thumb1 on a processor which has a VFP unit (which
is not accessible from Thumb1), we were converting the fastcc calling
convention to AAPCS-VFP, which is not possible.

llvm-svn: 210889
2014-06-13 08:33:03 +00:00
Matt Arsenault c02eea7f64 R600: Don't call setOperationAction with things that aren't opcodes.
CondCode actions are set with setCondCodeAction.
This should have been a harmless bug since the values seem to only
collide only with nodes that don't need to be handled, and these are
already correctly setup elsewhere.

llvm-svn: 210888
2014-06-13 07:44:38 +00:00
Matt Arsenault 825fb0b094 R600/SI: Fix selection error on i64 rotl / rotr.
Evergreen is still broken due to missing shl_parts.

llvm-svn: 210885
2014-06-13 04:00:30 +00:00
Rafael Espindola b4ad29be92 Fix build on windows.
llvm-svn: 210873
2014-06-13 02:36:09 +00:00
Rafael Espindola db4ed0bdab Remove 'using std::errro_code' from lib.
llvm-svn: 210871
2014-06-13 02:24:39 +00:00
Juergen Ributzka 3453bcf64d [FastISel][X86] Add support for cvttss2si/cvttsd2si intrinsics.
This adds support for the cvttss2si/cvttsd2si intrinsics. Preceding
insertelement instructions are folded into the conversion instruction (if
possible).

llvm-svn: 210870
2014-06-13 02:21:58 +00:00
Tom Stellard 2e59a45f80 R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtarget
llvm-svn: 210869
2014-06-13 01:32:00 +00:00