Commit Graph

100031 Commits

Author SHA1 Message Date
David Blaikie 15632ae11a DwarfUnit: Provide a reference to a defining DwarfCompileUnit from DwarfTypeUnit.
Type units need to insert their file strings into the compile unit's
line/file table. This is preliminary work to that end.

llvm-svn: 201196
2014-02-12 00:31:30 +00:00
David Blaikie 101613e903 DwarfUnit: Refactor DW_AT_file creation into a common function.
This is preliminary work to fix type unit file strings so they appear in
their originating CU's line table - but it's also just good/simple
cleanup, so I'm committing it ahead of time.

llvm-svn: 201195
2014-02-12 00:11:25 +00:00
David Blaikie 5201930762 DwarfUnit: Replace unnecessary conditionals with asserts.
We used to be pretty vague about what debug entities were what, with
many conditionals to silently drop/skip/accept things. These don't seem
to be relevant anymore.

llvm-svn: 201194
2014-02-11 23:57:03 +00:00
Evan Cheng 57add3e4ee Tweak ARM fastcc by adopting these two AAPCS rules:
* CPRCs may be allocated to co-processor registers or the stack – they may never be allocated to core registers
* When a CPRC is allocated to the stack, all other VFP registers should be marked as unavailable

The difference is only noticeable in rare cases where there are a large number of floating point arguments (e.g.
7 doubles + additional float, double arguments). Although it's probably still better to avoid vmov as it can cause
stalls in some older ARM cores. The other, more subtle benefit, is to minimize difference between the various
calling conventions.

rdar://16039676

llvm-svn: 201193
2014-02-11 23:49:31 +00:00
Adrian Prantl cbcd578f0c Reapply r201180 with an additional error path.
Debug info: Emit values in subregisters that do not have a separate
DWARF register number by emitting a super-register + DW_OP_bit_piece.
This is necessary because on x86_64, there are no DWARF register numbers
for i386-style subregisters.
Fixes a bunch of FIXMEs.

rdar://problem/16015314

llvm-svn: 201190
2014-02-11 22:22:15 +00:00
Adrian Prantl 80b6fd02fa Revert "Debug info: Emit values in subregisters that do not have a separate"
This reverts commit r201179 for buildbot breakage.

llvm-svn: 201188
2014-02-11 22:03:30 +00:00
David Blaikie 284cfc1089 DebugInfo: Don't include the name of the CU file in the line table file list when it's unneeded
This comes up in empty files or files containing #file directives that
never reference the actual source file name. Came up in a small test of
line tables I was playing with.

llvm-svn: 201187
2014-02-11 21:49:46 +00:00
David Blaikie 6bd395f3f0 DebugInfo: Remove dependence on file numbering in the line table.
These tests were unnecessarily sensitive to the presence and ordering of
elements in the line table file_names list which will break on a future
change I'm working on.

llvm-svn: 201185
2014-02-11 21:46:46 +00:00
Adrian Prantl c4fd6b71c6 whitespace
llvm-svn: 201181
2014-02-11 21:23:02 +00:00
Adrian Prantl a83cc8a356 Debug info: Emit values in subregisters that do not have a separate
DWARF register number by emitting a super-register + DW_OP_bit_piece.
This is necessary because on x86_64, there are no DWARF register numbers
for i386-style subregisters.
Fixes a bunch of FIXMEs.

rdar://problem/16015314

llvm-svn: 201180
2014-02-11 21:22:59 +00:00
Adrian Prantl 6f84d31540 make llvm-dwarfdump a little more resilient when parsing .debug_loc
sections. The call to data.getUnsigned(&Offset, AddressSize) only
increments Offset if the read succeeds, which will result in an infinite
loop.

llvm-svn: 201179
2014-02-11 21:22:53 +00:00
Matt Arsenault 71b71d25eb R600/SI: Fix assertion on infinite loops.
This isn't the most useful case to fix in the real world,
but bugpoint runs into this.

llvm-svn: 201177
2014-02-11 21:12:38 +00:00
Benjamin Kramer 94fc18d040 InstCombine: Teach icmp merging about the equivalence of bit tests and UGE/ULT with a power of 2.
This happens in bitfield code. While there reorganize the existing code
a bit.

llvm-svn: 201176
2014-02-11 21:09:03 +00:00
Jim Grosbach 7422074df0 Tidy up a bit. Formatting only.
llvm-svn: 201174
2014-02-11 20:48:41 +00:00
Jim Grosbach 8bfcb735fa ARM: Thumb2 LDR(literal) can target SP.
Fix a slightly overzealous destination register restriction for the
'without .w' alias. Add some explicit testcases.

rdar://16033140

llvm-svn: 201173
2014-02-11 20:48:39 +00:00
Benjamin Kramer 987b850cf2 SCEV: Cast switched values to make -Wswitch more useful.
llvm-svn: 201170
2014-02-11 19:02:55 +00:00
Sylvestre Ledru 539997978e Improve the declaration when LDPO_PIE is not available.
Thanks to İsmail Dönmez for the better declaration.

llvm-svn: 201163
2014-02-11 17:30:18 +00:00
Sylvestre Ledru 1515a48e14 If LDPO_PIE is not defined (before binutils 2.23 version),
use the hardcoded declaration 3
See r201110 for the initial change

llvm-svn: 201161
2014-02-11 17:11:32 +00:00
Mark Seaborn 6e15ee85d1 Add a note about using "Differential Revision:" in commit messages
I noticed this convention from the commit logs.  It seems like it
would be useful to document it, to encourage other committers to link
back to code reviews in their commits.

Differential Revision: http://llvm-reviews.chandlerc.com/D2678

llvm-svn: 201160
2014-02-11 16:58:03 +00:00
Benjamin Kramer 5a188549ad ScalarEvolution: Analyze trip count of loops with a switch guarding the exit.
llvm-svn: 201159
2014-02-11 15:44:32 +00:00
Robert Lougher 7d9084ffa1 Teach the DAGCombiner how to fold concat_vector nodes when the input is two
BUILD_VECTOR nodes, e.g.:

(concat_vectors (BUILD_VECTOR a1, a2, a3, a4), (BUILD_VECTOR b1, b2, b3, b4))
->
(BUILD_VECTOR a1, a2, a3, a4, b1, b2, b3, b4)

This fixes an issue with AVX, where a sequence was not recognized as a 256-bit
vbroadcast due to the concat_vectors.

llvm-svn: 201158
2014-02-11 15:42:46 +00:00
Bradley Smith 9d80849714 [AArch64] Add missing PCRel relocations for AArch64 in RuntimeDyldELF
llvm-svn: 201149
2014-02-11 12:59:09 +00:00
Chandler Carruth fc25854b09 [LPM] Switch LICM to actively use LCSSA in addition to preserving it.
Fixes PR18753 and PR18782.

This is necessary for LICM to preserve LCSSA correctly and efficiently.
There is still some active discussion about whether we should be using
LCSSA, but we can't just immediately stop using it and we *need* LICM to
preserve it while we are using it. We can restore the old SSAUpdater
driven code if and when there is a serious effort to remove the reliance
on LCSSA from all of the loop passes.

However, this also serves as a great example of why LCSSA is very nice
to have. This change significantly simplifies the process of sinking
instructions for LICM, and makes it quite a bit less expensive.

It wouldn't even be as complex as it is except that I had to start the
process of removing the big recursive LCSSA formation hammer in order to
switch even this much of the re-forming code to asserting that LCSSA was
preserved. I'll fully remove that next just to tidy things up until the
LCSSA debate settles one way or the other.

llvm-svn: 201148
2014-02-11 12:52:27 +00:00
Robert Lytton 70b5ba49c3 XCore target: fix const section handling
Xcore target ABI requires const data that is externally visible
to be handled differently if it has C-language linkage rather than
C++ language linkage.

Clang now emits ".cp.rodata" section information.

All other externally visible constant data will be placed in the DP section.

llvm-svn: 201144
2014-02-11 10:36:26 +00:00
Robert Lytton 9b6bb461b1 XCore target: Lower ATOMIC_LOAD & ATOMIC_STORE
llvm-svn: 201143
2014-02-11 10:36:18 +00:00
Elena Demikhovsky 1f32c313f1 AVX: fixed a bug in LowerVECTOR_SHUFFLE
llvm-svn: 201140
2014-02-11 10:21:53 +00:00
Dmitri Gribenko 70e6585f0c Remove TimeValue::toPosixTime() -- it is buggy, semantics are unclear, and its
only current user should be using toEpochTime() instead.

llvm-svn: 201136
2014-02-11 09:11:18 +00:00
Elena Demikhovsky 2aafc22ed9 AVX-512: Optimized BUILD_VECTOR pattern;
fixed encoding of VEXTRACTPS instruction.

llvm-svn: 201134
2014-02-11 07:25:59 +00:00
Quentin Colombet 64ca544d95 [CodeGenPrepare] Test case for the promotions that bypass the
profitability check due to some other checks in the addressing
mode matcher. I.e., test case for commit r201121.

<rdar://problem/16020230>

llvm-svn: 201132
2014-02-11 06:55:43 +00:00
Lang Hames d41001706a In RuntimeDyldImpl::emitSection, make Allocate (section size to be allocated) a
uintptr_t. An unsigned could overflow for large sections.

No test case - anything big enough to overflow an unsigned is going to take an
appreciable time to zero when the test passes.

The choice of uintptr_t was made to match the RTDyldMemoryManager APIs, but
these should probably be hardcoded to uint64_ts: It is legitimate to JIT for
64-bit targets from a 32-bit host/compiler.

llvm-svn: 201127
2014-02-11 05:28:24 +00:00
Craig Topper 3f6954ffd0 Changed attributes of all gather intrinsics from IntrReadMem to IntrReadArgMem as they access only memory based on argument. Patch by Robert Khasanov.
llvm-svn: 201126
2014-02-11 04:05:33 +00:00
Aaron Ballman 07e7618e95 Using the helper API for random number generation.
llvm-svn: 201125
2014-02-11 03:40:14 +00:00
Aaron Ballman 3f5e8b8dc1 Hopefully fixing the MinGW 32 build, which was broken by r200767. Not using rand_s() since MinGW does not have an implementation for it, but instead using the underlying CryptGenRandom APIs.
llvm-svn: 201124
2014-02-11 02:47:33 +00:00
Quentin Colombet 5a69dda9b0 [CodeGenPrepare] Undo changes that happened for the profitability check.
The addressing mode matcher checks at some point the profitability of folding an
instruction into the addressing mode. When the instruction to be folded has
several uses, it checks that the instruction can be folded in each use.
To do so, it creates a new matcher for each use and check if the instruction is
in the list of the matched instructions of this new matcher.

The new matchers may promote some instructions and this has to be undone to keep
the state of the original matcher consistent.

A test case will follow.

<rdar://problem/16020230>

llvm-svn: 201121
2014-02-11 01:59:02 +00:00
David Blaikie a47009dbd3 DebugInfo: Use existing symbol rather than creating it again.
llvm-svn: 201119
2014-02-11 01:23:52 +00:00
Eli Bendersky b60f83878c Move the *PassPrinter into their own module.
These are self-contained in functionality so it makes sense to separate them,
as opt.cpp has grown quite big already.

Following Eric's suggestions, if this code is ever deemed useful outside of
tools/opt, it will make sense to move it to one of the LLVM libraries like IR.

llvm-svn: 201116
2014-02-10 23:34:23 +00:00
Juergen Ributzka 73a7fcc6e1 [Stackmaps] Cleanup code. No functional change intended.
llvm-svn: 201115
2014-02-10 23:30:26 +00:00
Manman Ren 03456a176d LTO API: add lto_module_create_from_memory_with_path.
This function adds an extra path argument to lto_module_create_from_memory.
The path argument will be passed to makeBuffer to make sure the MemoryBuffer
has a name and the created module has a module identifier.

This is mainly for emitting warning messages from the linker. When we emit
warning message on a module, we can use the module identifier.

rdar://15985737

llvm-svn: 201114
2014-02-10 23:26:14 +00:00
Rafael Espindola efedd3aa1b Mark the methods in the Mangler const.
A const ObjectFile needs to be able to provide its name. For an IRObjectFile,
that means being able to call the mangler. Since each IRObjectFile can have
a different mangling, it is natural for them to contain a Mangler which is
therefore also const.

llvm-svn: 201113
2014-02-10 21:25:13 +00:00
Reid Kleckner 47e84fb675 cmake: Do not export targets when installing toolchain only
Patch by Brad King!

llvm-svn: 201111
2014-02-10 20:44:57 +00:00
Rafael Espindola 76e376d30a Fix an old FIXME. LDPO_PIE is available since 2.23, realeased 2012-10-22.
llvm-svn: 201110
2014-02-10 20:38:38 +00:00
Rafael Espindola b5155a572f Change the begin and end methods in ObjectFile to match the style guide.
llvm-svn: 201108
2014-02-10 20:24:04 +00:00
Matt Arsenault 0cdcd961bf R600: Implement isTruncateFree
Truncation is just accessing a subregister for any multiple of
the register size, so it's free.

llvm-svn: 201107
2014-02-10 19:57:42 +00:00
Chandler Carruth 756c22cded [LPM] A terribly simple fix to a terribly complex bug: PR18773.
The crux of the issue is that LCSSA doesn't preserve stateful alias
analyses. Before r200067, LICM didn't cause LCSSA to run in the LTO pass
manager, where LICM runs essentially without any of the other loop
passes. As a consequence the globalmodref-aa pass run before that loop
pass manager was able to survive the loop pass manager and be used by
DSE to eliminate stores in the function called from the loop body in
Adobe-C++/loop_unroll (and similar patterns in other benchmarks).

When LICM was taught to preserve LCSSA it had to require it as well.
This caused it to be run in the loop pass manager and because it did not
preserve AA, the stateful AA was lost. Most of LLVM's AA isn't stateful
and so this didn't manifest in most cases. Also, in most cases LCSSA was
already running, and so there was no interesting change.

The real kicker is that LCSSA by its definition (injecting PHI nodes
only) trivially preserves AA! All we need to do is mark it, and then
everything goes back to working as intended. It probably was blocking
some other weird cases of stateful AA but the only one I have is
a 1000-line IR test case from loop_unroll, so I don't really have a good
test case here.

Hopefully this fixes the regressions on performance that have been seen
since that revision.

llvm-svn: 201104
2014-02-10 19:39:35 +00:00
Hans Wennborg 4a4be11e62 Copy the ThreadLocalMode in GlobalVariable::copyAttributesFrom
This fixes the oversight from r159077.

llvm-svn: 201098
2014-02-10 17:13:56 +00:00
Tom Stellard 5d7aaaed7d R600/SI: Initialize M0 and emit S_WQM_B64 whenever DS instructions are used
DS instructions that access local memory can only uses addresses that
are less than or equal to the value of M0.  When M0 is uninitialized,
then we experience undefined behavior.

This patch also changes the behavior to emit S_WQM_B64 on pixel shaders
no matter what kind of DS instruction is used.

llvm-svn: 201097
2014-02-10 16:58:30 +00:00
Tom Stellard 9a32e5f29a R600/SI: Only use S_WQM_B64 in pixel shaders
This doesn't change any functionality, since we only have two shader
types (compute and pixel) that use local memory.  We're just changing
the logic to match the documentation.

llvm-svn: 201096
2014-02-10 16:58:27 +00:00
David Blaikie 00107f8203 Remove some prototype code accidentally committed in r201043
Thanks to Chandler for the catch.

llvm-svn: 201095
2014-02-10 16:49:07 +00:00
Tim Northover b0430415e6 ARM: use natural LLVM IR for vshll instructions
Similarly to the vshrn instructions, these are simple zext/sext + trunc
operations. Using normal LLVM IR should allow for better code, and more sharing
with the AArch64 backend.

llvm-svn: 201093
2014-02-10 16:20:29 +00:00
Chad Rosier bcde0c49cb [AArch64] Handle aliases of conditional branches without b.pred form.
llvm-svn: 201091
2014-02-10 15:43:11 +00:00