3b727f55aa
Make ELF OS ABI dependent on the OS from target triple.
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llvm-svn: 113508
2010-09-09 17:57:50 +00:00
0ec303b97b
Move remaining MMX instructions from SSE to MMX.
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llvm-svn: 113501
2010-09-09 17:13:07 +00:00
01cda2d35a
Silence compiler warning.
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llvm-svn: 113478
2010-09-09 07:30:15 +00:00
4adbaf1843
Fix NEON VLD pseudo instruction itineraries that were incorrectly copied from
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the VST pseudos. The VLD/VST scheduling still needs work (see pr6722), but
at least we shouldn't confuse the loads with the stores.
llvm-svn: 113473
2010-09-09 05:40:26 +00:00
2ff757d422
Nuke whitespace and fix some indenting.
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llvm-svn: 113463
2010-09-09 01:06:51 +00:00
5f4a6f295c
Move most MMX instructions (defined as anything that
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uses MMX, even if it also uses other things) from InstrSSE
into InstrMMX. No (intended) functional change.
llvm-svn: 113462
2010-09-09 01:02:39 +00:00
bd3d121641
Handle 64-bit floating point binops as well.
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llvm-svn: 113461
2010-09-09 01:02:03 +00:00
24dc27f73a
Basic 32-bit FP operations.
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llvm-svn: 113459
2010-09-09 00:53:57 +00:00
84971c850a
For double-spaced VLD3/VLD4 instructions, copy the explicit super-register use
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operand from the pseudo instruction to the new instruction as an implicit use.
This will preserve any other flags (e.g., kill) on the operand.
llvm-svn: 113456
2010-09-09 00:38:32 +00:00
f14b9bf98d
Handle float->double extension.
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llvm-svn: 113455
2010-09-09 00:26:48 +00:00
3cf63f1edd
Rewrite TargetMaterializeConstant splitting it out into two functions
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for integer and fp constants. Implement todo to use vfp3 instructions
to materialize easy constants if we can.
llvm-svn: 113453
2010-09-09 00:19:41 +00:00
4ccd5ce6ea
Simplify copying over operands from pseudo NEON load/store instructions.
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For VLD3/VLD4 with double-spaced registers, add the implicit use of the
super register for both the instruction loading the even registers and the
instruction loading the odd registers.
llvm-svn: 113452
2010-09-09 00:15:32 +00:00
359f8ba337
Clean up a comment.
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llvm-svn: 113442
2010-09-08 23:39:54 +00:00
c3e9c404aa
Very basic compare support.
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llvm-svn: 113440
2010-09-08 23:13:45 +00:00
5838af54bf
Delete dead code.
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llvm-svn: 113436
2010-09-08 22:58:35 +00:00
722cd122dc
Fix LDM_RET schedule itinery.
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llvm-svn: 113435
2010-09-08 22:57:08 +00:00
28a9c2f89a
fix rdar://8407548, I missed the commuted form of xchg/test without a suffix.
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llvm-svn: 113427
2010-09-08 22:27:05 +00:00
d7aba234c2
fix wonky formatting.
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llvm-svn: 113426
2010-09-08 22:22:10 +00:00
8ead237758
fix bugs in push/pop segment support, rdar://8407242
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llvm-svn: 113422
2010-09-08 22:13:08 +00:00
0d2e6ad504
Add intrinsic-based patterns for MMX PINSRW and PEXTRW.
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llvm-svn: 113420
2010-09-08 22:08:40 +00:00
6489df7c8c
Make the loads/stores match the type we really want to store.
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llvm-svn: 113417
2010-09-08 21:49:50 +00:00
e54dba94f9
Check in forgotten file. Should fix build.
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llvm-svn: 113409
2010-09-08 21:09:48 +00:00
4dae01781f
Slight cleanup, use only one form of MMXI_binop_rm_int.
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llvm-svn: 113406
2010-09-08 20:54:00 +00:00
504d23bd05
Re-enable usage of the ARM base pointer. r113394 fixed the known failures.
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Re-running some nightly testers w/ it enabled to verify.
llvm-svn: 113399
2010-09-08 20:12:02 +00:00
21c9471706
Fix errant fall-throughs causing the base pointer to be used when the frame
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pointer was intended. rdar://8401980
llvm-svn: 113394
2010-09-08 19:55:28 +00:00
d79bb127dd
Add intrinsic forms of mmx<->sse conversions. Notes:
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Omission of memory form of PI2PD is intentional; this
does not use an MMX register and does not put the chip
into MMX mode (PI2PS, oddly enough, does).
Operands of PI2PS follow the gcc builtin, not Intel.
llvm-svn: 113388
2010-09-08 19:15:38 +00:00
f5dd1929a2
Rewrite TargetMaterializeConstant.
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llvm-svn: 113387
2010-09-08 18:56:34 +00:00
99a9f4661a
Minor change. Fix comments and remove unused and redundant code
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llvm-svn: 113378
2010-09-08 18:12:31 +00:00
f7fee1c185
x86 vector shuffle lowering now relies only on target specific
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nodes to emit shuffles and don't do isel mask matching anymore.
- Add the selection of the remaining shuffle opcode (movddup)
- Introduce two new functions to "recognize" where we may get
potential folds and add several comments to them explaining why
they are not yet in the desidered shape.
- Add more patterns to fallback the case where we select
a specific shuffle opcode as if it could fold a load, but it
can't, so remap to a valid instruction.
- Add a couple of FIXMEs to address in the following days once
there's a good solution to the current folding problem.
llvm-svn: 113369
2010-09-08 17:43:25 +00:00
7dfca6fb51
Be more careful about when to do dynamic stack realignment. Since we have an
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option to disable base pointer usage, pay attention to it when deciding
if we can realign (if no base pointer and VLAs, we can't).
llvm-svn: 113366
2010-09-08 17:22:12 +00:00
53aa5e31e1
Add missing assert
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llvm-svn: 113365
2010-09-08 17:05:45 +00:00
e542972828
Fix CellSPU vector shuffles, again.
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Some cases of lowering to rotate were miscompiled.
llvm-svn: 113355
2010-09-08 11:53:38 +00:00
2907d2e419
add support for the commuted form of the test instruction, rdar://8018260.
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llvm-svn: 113352
2010-09-08 05:51:12 +00:00
a9ca7837e4
implement proper support for sysret{,l,q}, rdar://8403907
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llvm-svn: 113350
2010-09-08 05:45:34 +00:00
063363fa80
implement the iret suite of instructions properly,
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fixing rdar://8403974
llvm-svn: 113349
2010-09-08 05:38:31 +00:00
086a83afb1
add support for instruction prefixes on the same line as the instruction,
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implementing rdar://8033482 and PR7254.
llvm-svn: 113348
2010-09-08 05:17:37 +00:00
91689c1d0f
change the MC "ParseInstruction" interface to make it the
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implementation's job to check for and lex the EndOfStatement
marker.
llvm-svn: 113347
2010-09-08 05:10:46 +00:00
8caea68a4f
gas accepts xchg <mem>, <reg> as a synonym for xchg <reg>, <mem>.
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Add this to the mc assembler, fixing PR8061
llvm-svn: 113346
2010-09-08 04:53:27 +00:00
7a23aa081a
ARM/Disassembler: Fix definitions incompatible(unsigned and uint32_t) to Cygwin-1.5, following up to r113255.
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llvm-svn: 113345
2010-09-08 04:48:17 +00:00
4703cb4a96
fix the encoding of the "jump on *cx" family of instructions,
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rdar://8061602
llvm-svn: 113343
2010-09-08 04:30:51 +00:00
535d3b4e09
remove trailing whitespace
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llvm-svn: 113338
2010-09-08 03:54:02 +00:00
19cb2f4c67
remove obsolete comment
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llvm-svn: 113337
2010-09-08 03:51:44 +00:00
261df12f64
disable for the moment while tracking down a few Thumb2-O0 failure that look
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related. (attempt deux, complete w/ test update this time)
llvm-svn: 113333
2010-09-08 02:00:34 +00:00
b2c950187e
woops. need to update a test along with this.
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llvm-svn: 113332
2010-09-08 01:49:09 +00:00
7cda56ea6a
disable temporarily while sorting out a few test failures in Thumb2-O0 tests.
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llvm-svn: 113331
2010-09-08 01:47:49 +00:00
136d035e45
correct spill code to properly determine if dynamic stack realignment is
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present in the function and thus whether aligned load/store instructions can
be used.
llvm-svn: 113323
2010-09-08 00:26:59 +00:00
abcbe2474d
VFP/NEON load/store multiple instructions are addrmode4, not 5.
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llvm-svn: 113322
2010-09-08 00:25:50 +00:00
88628e9738
To shrink a t2LDM instruction to the 16-bit wide tLDM instruction, the base
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register must be one of the destination registers for the load. Otherwise,
the tLDM instruction will write-back to the base register, which isn't what's
desired (otherwise, we'd have a t2LDM_UPD instead).
rdar://8394087
llvm-svn: 113297
2010-09-07 22:30:53 +00:00
9877af3b46
grammar tweak
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llvm-svn: 113289
2010-09-07 21:30:25 +00:00
6b1d62c529
Factor out some x86 vector shuffle rewriting and add comments about the direction the shuffle lowering is heading to
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llvm-svn: 113286
2010-09-07 21:03:14 +00:00
Roman Divacky