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187 Commits

Author SHA1 Message Date
Chris Lattner d17089231a remove a bunch of dead named arguments in input patterns, 
though some look dubious afaict, these are all ok.

llvm-svn: 96899
 2010-02-23 06:54:29 +00:00
Chris Lattner 48370e14e7 fix a type mismatch in this pattern, where we were using an i64 imm in a 
place where an i32 imm was required, the old isel just got lucky.

This fixes CodeGen/X86/x86-64-and-mask.ll

llvm-svn: 96894
 2010-02-23 06:09:57 +00:00
Chris Lattner 140caa7240 remove special cases for vmlaunch, vmresume, vmxoff, and swapgs 
fix swapgs to be spelled right.

llvm-svn: 96058
 2010-02-13 00:41:14 +00:00
Daniel Dunbar d7e9212e2d X86: Fix definition for RCL/RCR.*m? operations -- they were getting represented 
with "tied memory operands", which is wrong.

llvm-svn: 95950
 2010-02-12 01:22:03 +00:00
Chris Lattner b06015aa69 move target-independent opcodes out of TargetInstrInfo 
into TargetOpcodes.h.  #include the new TargetOpcodes.h
into MachineInstr.  Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the 
codebase.

llvm-svn: 95687
 2010-02-09 19:54:29 +00:00
Chris Lattner 86bd194234 really kill off the last MRMInitReg inst, remove logic from encoder. 
llvm-svn: 95437
 2010-02-05 21:34:18 +00:00
Chris Lattner 340b542f8b factor code better in X86MCInstLower::Lower, teach it to 
lower the SETB* instructions.

llvm-svn: 95431
 2010-02-05 21:13:48 +00:00
Evan Cheng b33dbc5019 Change TAILJMP's to be varargs and transfer implicit uses over from TCRETURN's. Otherwise the missing uses can make post-regalloc scheduling do bad things. This fixes 403.gcc. 
llvm-svn: 94950
 2010-01-31 07:28:44 +00:00
Daniel Dunbar 862023fcb2 Mark EH_RETURN64 as CodeGenOnly. 
llvm-svn: 94205
 2010-01-22 20:16:37 +00:00
Evan Cheng 08557ef5f4 Eliminate or_not_add and just use AddedComplexity so isel tries or_is_add patterns first. 
llvm-svn: 93245
 2010-01-12 18:31:19 +00:00
Dan Gohman c119580307 Reapply the MOV64r0 patch, with a fix: MOV64r0 clobbers EFLAGS. 
llvm-svn: 93229
 2010-01-12 04:42:54 +00:00
Evan Cheng 99789a7a76 Extend r93152 to work on OR r, r. If the source set bits are known not to overlap, then select as an ADD instead. 
llvm-svn: 93191
 2010-01-11 22:03:29 +00:00
Evan Cheng 7bdf339602 Revert 93158. It's breaking quite a few x86_64 tests. 
llvm-svn: 93185
 2010-01-11 21:13:41 +00:00
Dan Gohman e99a3c191e Use a 32-bit and with implicit zero-extension instead of a 64-bit and if it 
has an immediate with at least 32 bits of leading zeros, to avoid needing to
materialize that immediate in a register first.

FileCheckize, tidy, and extend a testcase to cover this case.

This fixes rdar://7527390.

llvm-svn: 93160
 2010-01-11 17:58:34 +00:00
Dan Gohman 3a55686345 Re-instate MOV64r0 and MOV16r0, with adjustments to work with the 
new AsmPrinter. This is perhaps less elegant than describing them
in terms of MOV32r0 and subreg operations, but it allows the
current register to rematerialize them.

llvm-svn: 93158
 2010-01-11 17:37:57 +00:00
Dan Gohman f6e8369a5b Pattern top-level operators don't need to be restricted to a 
single user. The _su forms are intended for non-top-level nodes.

llvm-svn: 93155
 2010-01-11 17:21:05 +00:00
Evan Cheng 64d9f40557 Select an OR with immediate as an ADD if the input bits are known zero. This allow the instruction to be 3address-fied if needed. 
llvm-svn: 93152
 2010-01-11 17:03:47 +00:00
Evan Cheng b92f263ceb Fix what looks to me obvious instruction definition bugs. 
1. CMPXCHG8B and CMPXCHG16B did not specify implicit physical register defs and uses.
2. LCMPXCHG8B is loading 64 bit memory, not 32 bit.

llvm-svn: 92985
 2010-01-08 01:29:19 +00:00
Evan Cheng 7844a99d60 Perform this folding as a target specific dag combine: 
(or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)

The isel patterns may not catch all the cases if general dag combine has reduced width of source operands.

llvm-svn: 92513
 2010-01-04 21:22:48 +00:00
Sean Callanan 04d8cb74f3 Instruction fixes, added instructions, and AsmString changes in the 
X86 instruction tables.

Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.

This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.

* X86*.td
	Removed tabs and fixed 80-line violations

* X86Instr64bit.td
	(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
		Added
	(CALL, CMOV) Added qualifiers
	(JMP) Added PC-relative jump instruction
	(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
		that it is 64-bit only (ambiguous since it has no
		REX prefix)
	(MOV) Added rr form going the other way, which is encoded
		differently
	(MOV) Changed immediates to offsets, which is more correct;
		also fixed MOV64o64a to have to a 64-bit offset
	(MOV) Fixed qualifiers
	(MOV) Added debug-register and condition-register moves
	(MOVZX) Added more forms
	(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
		(as with MOV) are encoded differently
	(ROL) Made REX.W required
	(BT) Uncommented mr form for disassembly only
	(CVT__2__) Added several missing non-intrinsic forms
	(LXADD, XCHG) Reordered operands to make more sense for
		MRMSrcMem
	(XCHG) Added register-to-register forms
	(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
	(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
		Added
* X86InstrFPStack.td
	(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
	 FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
	 FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
	 FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
	 FXRSTOR)
		Added
	(FCOM, FCOMP) Added qualifiers
	(FSTENV, FSAVE, FSTSW) Fixed opcode names
	(FNSTSW) Added implicit register operand
* X86InstrInfo.td
	(opaque512mem) Added for FXSAVE/FXRSTOR
	(offset8, offset16, offset32, offset64) Added for MOV
	(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
	 LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
	 LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
	 LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
	 CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
	 SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
	 VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
	 VMWRITE, VMXOFF, VMXON) Added
	(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
	(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
	 JGE, JLE, JG, JCXZ) Added 32-bit forms
	(MOV) Changed some immediate forms to offset forms
	(MOV) Added reversed reg-reg forms, which are encoded
		differently
	(MOV) Added debug-register and condition-register moves
	(CMOV) Added qualifiers
	(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
	(BT) Uncommented memory-register forms for disassembler
	(MOVSX, MOVZX) Added forms
	(XCHG, LXADD) Made operand order make sense for MRMSrcMem
	(XCHG) Added register-register forms
	(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
	(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
	change

* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
  qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier

llvm-svn: 91638
 2009-12-18 00:01:26 +00:00
Evan Cheng 1be6286028 Re-enable 91381 with fixes. 
llvm-svn: 91489
 2009-12-16 00:53:11 +00:00
Evan Cheng b3032962ef Fix an encoding bug. 
llvm-svn: 91417
 2009-12-15 06:49:02 +00:00
Evan Cheng 0e8b9e32d1 Use sbb x, x to materialize carry bit in a GPR. The result is all one's or all zero's. 
llvm-svn: 91381
 2009-12-15 00:53:42 +00:00
Dan Gohman 6f51309021 Fix a minor inconsistency. 
llvm-svn: 90165
 2009-11-30 23:33:37 +00:00
Evan Cheng d33400e636 MOV64rm should be marked isReMaterializable. 
llvm-svn: 89019
 2009-11-17 00:55:55 +00:00
Anton Korobeynikov 0f38d989bd Do not infer the target type for COPY_TO_REGCLASS from dest regclass, this won't work if it can contain several types. Require explicit result type for the node for now. This fixes PR5364. 
PS: It seems that blackfin usage of copy_to_regclass is completely bogus!
llvm-svn: 85766
 2009-11-02 00:11:39 +00:00
Dan Gohman f7c4299312 Initial x86 support for BlockAddresses. 
llvm-svn: 85557
 2009-10-30 01:28:02 +00:00
Dan Gohman 453d64c9f5 Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a 
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.

llvm-svn: 85517
 2009-10-29 18:10:34 +00:00
Chris Lattner 5db7b6a5d4 remove strings from instructions who are never asmprinted. 
All of these "subreg32" modifier instructions are handled
explicitly by the MCInst lowering phase.  If they got to
the asmprinter, they would explode.  They should eventually
be replace with correct use of subregs.

llvm-svn: 84526
 2009-10-19 19:51:42 +00:00
Torok Edwin 033f01c922 Fix PR5247, "lock addq" pattern (and other atomics), it DOES modify EFLAGS. 
LLC was scheduling compares before the adds causing wrong branches to be taken
in programs, resulting in misoptimized code wherever atomic adds where used.

llvm-svn: 84485
 2009-10-19 11:00:58 +00:00
Dan Gohman 722b1eefdb Add support for using the FLAGS result of or, xor, and and instructions 
on x86, to avoid explicit test instructions. A few existing tests changed
due to arbitrary register allocation differences.

llvm-svn: 82263
 2009-09-18 19:59:53 +00:00
Sean Callanan 8e31aa773f Added RCL and RCR (rotate left and right with a 
carry bit) instructions to the Intel instruction
tables.

llvm-svn: 82260
 2009-09-18 19:35:23 +00:00
Sean Callanan cc774e7476 Added the LODS (load byte into register, usually 
as part string parsing) instructions to the Intel
instruction tables.

llvm-svn: 82089
 2009-09-16 22:59:28 +00:00
Sean Callanan 73645ac10c Added the LAR (load segment access rights) 
instructions to the Intel instruction tables.

llvm-svn: 82084
 2009-09-16 21:55:34 +00:00
Sean Callanan ca968cf1f0 Added an alternate form of register-register CMP 
to the Intel instruction tables.

llvm-svn: 82081
 2009-09-16 21:11:23 +00:00
Sean Callanan 0fdee53266 Added the definitions for one-bit left shifts to 
the Intel instruction tables.

The patterns will stay blank because ADD reg, reg
is faster, but having the encoding available is
useful for the disassembler.

llvm-svn: 81994
 2009-09-16 02:28:43 +00:00
Sean Callanan 7a27b9342c Updated comments per Eli's suggestion. 
llvm-svn: 81923
 2009-09-15 21:43:27 +00:00
Sean Callanan 79b570de9d Added register-to-register ADD instructions to the 
Intel tables, where the source operand is
specified by the R/M field and the destination
operand by the Reg field.

llvm-svn: 81914
 2009-09-15 20:53:57 +00:00
Sean Callanan e8ea876cc3 Added a new register class for segment registers 
to the Intel register table.
Added 16- and 64-bit MOVs to and from the segment
registers to the Intel instruction tables.

llvm-svn: 81895
 2009-09-15 18:47:29 +00:00
Dan Gohman 65829a4ccb On x86-64, the 32-bit cmov doesn't actually clear the high 32-bit of 
its result if the condition is false.

llvm-svn: 81814
 2009-09-15 00:14:11 +00:00
Sean Callanan 29849eadef Added CMPS (string comparison) instructions for all 
operand widths to the Intel instruction tables, for
the purposes of the disassembler.

llvm-svn: 81601
 2009-09-12 02:25:20 +00:00
Sean Callanan 4dc00d3781 Added SCAS instructions in their 8, 16, 32, and 
64-bit variants for the disassembler.

llvm-svn: 81591
 2009-09-12 00:37:19 +00:00
Sean Callanan 31e48cdb5d Added ADC, SUB, SBB, and OR instructions that operate 
on rAX and an immediate.

llvm-svn: 81551
 2009-09-11 19:01:56 +00:00
Sean Callanan 62aebf9fa2 Added XOR instructions for rAX and immediates of 
various widths.

llvm-svn: 81458
 2009-09-10 19:52:26 +00:00
Sean Callanan 64804f37bb Added MOV instructions between rAX and memory offsets, 
including segment offsets and (for 8-bit operands)
absolute offsets.

llvm-svn: 81457
 2009-09-10 18:33:42 +00:00
Sean Callanan 31bb414efd Added a variety of PUSH and POP instructions, including 
ones capable of accessing R/M operands instead of just
registers.

llvm-svn: 81456
 2009-09-10 18:29:13 +00:00
Dan Gohman 319cc69f88 Add a -disable-16bit flag and associated support for experimenting with 
disabling the use of 16-bit operations on x86. This doesn't yet work for
inline asms with 16-bit constraints, vectors with 16-bit elements,
trampoline code, and perhaps other obscurities, but it's enough to try
some experiments.

llvm-svn: 80930
 2009-09-03 17:18:51 +00:00
Sean Callanan f400442927 Added opaque 32-, 48-, and 80-bit memory operand types to the X86 
instruction tables to support segmented addressing (and other objects
of obscure type).
Modified the X86 assembly printers to handle these new operand types.
Added JMP and CALL instructions that use segmented addresses.

llvm-svn: 80857
 2009-09-03 00:04:47 +00:00
Sean Callanan a8ee2e7496 Fixed the asmstrings for 8-bit, 16-bit, and 32-bit ADD %rAX, imm instructions. 
Added a 64-bit ADD %RAX, imm32 instruction.
Added all 4 forms for AND %rAX, imm and CMP %rAX, imm.

llvm-svn: 80746
 2009-09-02 00:55:49 +00:00
Sean Callanan 09b2e51711 Added TEST %rAX, $imm instructions to the Intel tables. These are required for the X86 disassembler. 
llvm-svn: 80696
 2009-09-01 18:14:18 +00:00