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7 Commits

Author SHA1 Message Date
Matt Arsenault c34819afe3 GlobalISel: Handle G_BUILD_VECTOR in isKnownToBeAPowerOfTwo 2021-03-22 14:20:35 -04:00
Matt Arsenault 6314a72730 AMDGPU/GlobalISel: Enable CSE in pre-legalizer combiner 2021-03-21 10:07:37 -04:00
Petar Avramovic d7834556b7 Reland [GlobalISel] Start using vectors in GISelKnownBits 
This is recommit of 4c8fb7ddd6.
MIR in one unit test had mismatched types.

For vectors we consider a bit as known if it is the same for all demanded
vector elements (all elements by default). KnownBits BitWidth for vector
type is size of vector element. Add support for G_BUILD_VECTOR.
This allows combines of urem_pow2_to_mask in pre-legalizer combiner.

Differential Revision: https://reviews.llvm.org/D96122
 2021-03-04 21:47:13 +01:00
Nico Weber 4b1015361c Revert "[GlobalISel] Start using vectors in GISelKnownBits" 
This reverts commit 4c8fb7ddd6.
Breaks check-llvm everywhere, see https://reviews.llvm.org/D96122
 2021-03-04 10:13:40 -05:00
Petar Avramovic 4c8fb7ddd6 [GlobalISel] Start using vectors in GISelKnownBits 
For vectors we consider a bit as known if it is the same for all demanded
vector elements (all elements by default). KnownBits BitWidth for vector
type is size of vector element. Add support for G_BUILD_VECTOR.
This allows combines of urem_pow2_to_mask in pre-legalizer combiner.

Differential Revision: https://reviews.llvm.org/D96122
 2021-03-04 15:05:23 +01:00
Jay Foad 6dcf9207df [AMDGPU] Fix a urem combine test to test what it was supposed to 2021-01-11 13:32:34 +00:00
Matt Arsenault 1f9b6ef91f GlobalISel: Add combine for G_UREM by power of 2 
Really I want this in the legalizer, but this is a start.
 2021-01-07 16:36:35 -05:00