Commit Graph

112892 Commits

Author SHA1 Message Date
Simon Pilgrim f6b81dae9e [X86] Convert all uses of WriteFShuffle to X86SchedWriteWidths.
In preparation of splitting WriteFShuffle by vector width.

llvm-svn: 331262
2018-05-01 14:14:42 +00:00
Sander de Smalen 788dc70c78 [AArch64][SVE] Asm: Support for contiguous ST1 (scalar+scalar) store instructions.
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D46121

llvm-svn: 331260
2018-05-01 13:36:03 +00:00
Simon Dardis 3d562fb975 Reland r331175: "[mips] Fix the predicates of jump and branch and link instructions"
The previous version of this patch restricted the 'jal' instruction to MIPS and
microMIPSr3. microMIPS32r6 does not have this instruction and instead uses jal
as an alias for balc.

Original commit message:
> Reviewers: smaksimovic, atanasyan, abeserminji
>
> Differential Revision: https://reviews.llvm.org/D46114
>

llvm-svn: 331259
2018-05-01 13:06:49 +00:00
Simon Pilgrim 57f2b185ac [X86] Split WriteVecLogic into XMM and YMM/ZMM scheduler classes
This removes all the WriteVecLogic InstRW overrides.

llvm-svn: 331258
2018-05-01 12:39:17 +00:00
Omer Paparo Bivas 82ef8e19ef [InstCombine] Adjusting bswap pattern matching to hold for And/Shift mixed case
Differential Revision: https://reviews.llvm.org/D45731

Change-Id: I85d4226504e954933c41598327c91b2d08192a9d
llvm-svn: 331257
2018-05-01 12:25:46 +00:00
Simon Pilgrim 6f710a6440 [X86] Convert all uses of WriteFLogic/WriteVecLogic to X86SchedWriteWidths.
In preparation of splitting WriteVecLogic by vector width.

llvm-svn: 331256
2018-05-01 12:15:29 +00:00
Florian Hahn ba4d85ee3f [MC] Add llvm_unreachable to toString to fix compile time warning.
Without this change, GCC 7 raises the warning below:
        control reaches end of non-void function

Reviewers: sbc100, andreadb

Reviewed By: andreadb

Differential Revision: https://reviews.llvm.org/D46304

llvm-svn: 331255
2018-05-01 11:18:31 +00:00
Simon Pilgrim fc0c26f1a6 [X86] Tag PSLLDQ/PSRLDQ as WriteShuffle scheduler classes instead of shifts.
Although they are encoded similar to bit shifts, the byte shifts behave like shuffles from a scheduling point of view.

llvm-svn: 331253
2018-05-01 11:05:42 +00:00
Andrea Di Biagio d4c58400c5 [X86] Correct spill slot size.
This patch fixes a bug introduced by revision 330778 (originally reviewed at:
https://reviews.llvm.org/D44782), where function isFrameLoadOpcode returned
the wrong number of bytes read for opcodes VMOVSSrm and VMOVSDrm.

This corrects that mistake, and extends the regression test to catch cases where
the dead stores should be removed.

Patch by Jeremy Morse.

Differential Revision: https://reviews.llvm.org/D46256

llvm-svn: 331252
2018-05-01 10:29:38 +00:00
Gabor Buella 0537fdbcab NFC, Avoid a warning in WasmObjectWriter
The warning was (introduced in r331220):

lib/MC/WasmObjectWriter.cpp:51:1: warning: control reaches end of non-void function [-Wreturn-type]
 }
 ^

llvm-svn: 331251
2018-05-01 10:21:10 +00:00
Gabor Buella c8ded04e85 [X86] movdiri and movdir64b instructions
Reviewers: spatel, craig.topper, RKSimon

Reviewed By: craig.topper, RKSimon

Differential Revision: https://reviews.llvm.org/D45983

llvm-svn: 331248
2018-05-01 10:01:16 +00:00
Chandler Carruth 2c85a23123 [PM/LoopUnswitch] Remove the last manual domtree update code from loop
unswitch and replace it with the amazingly simple update API code.

This addresses piles of FIXMEs around the update logic here and makes
everything substantially simpler.

llvm-svn: 331247
2018-05-01 09:54:39 +00:00
Chandler Carruth 44aab925fd [PM/LoopUnswitch] Add back a successor set that was removed based on
code review.

It turns out this *is* necessary, and I read the comment on the API
correctly the first time. ;]

The `applyUpdates` routine requires that updates are "balanced". This is
in order to cleanly handle cycles like inserting, removing, nad then
re-inserting the same edge. This precludes inserting the same edge
multiple times in a row as handling that would cause the insertion logic
to become *ordered* instead of *unordered* (which is what the API
provides).

It happens that in this specific case nothing (other than an assert and
contract violation) goes wrong because we're never inserting and
removing the same edge. The implementation *happens* to do the right
thing to eliminate redundant insertions in that case.

But the requirement is there and there is an assert to catch it.
Somehow, after the code review I never did another asserts-clang build
testing loop-unswich for a long time. As a consequence, I didn't notice
this despite a bunch of testing going on, but it shows up immediately
with an asserts build of clang itself.

llvm-svn: 331246
2018-05-01 09:42:09 +00:00
Craig Topper 33dc01d105 [X86] Remove 'opaque ptr' from the intel syntax parser and printer.
Previously for instructions like fxsave we would print "opaque ptr" as part of the memory operand. Now we print nothing.

We also no longer accept "opaque ptr" in the parser. We still accept any size to be specified for these instructions, but we may want to consider only parsing when no explicit size is specified. This what gas does.

llvm-svn: 331243
2018-05-01 04:42:00 +00:00
Eric Christopher 8024425801 Temporarily revert "[DEBUG] Initial adaptation of NVPTX target for debug info emission."
This appears to have some issues associated with the file directive output
causing multiple global symbols with the name "file" to be emitted into a
startup section. I'm investigating more specific causes and working with the
original author.

This reverts commit r330271.

Also Revert "[DEBUGINFO, NVPTX] Add the test for the debug info of the local"

This reverts commit r330592 and the follow up of 330779 as the testcase is dependent upon r330271.

llvm-svn: 331237
2018-05-01 00:10:13 +00:00
Alina Sbirlea 020363edcc [ModRefInfo] Rename local variable IsMustAlias to avoid shadowing MustAlias enum entry.
llvm-svn: 331222
2018-04-30 20:11:13 +00:00
Florian Hahn 3df8844b92 [SimplifyCFG] Use BB::instructionsWithoutDebug to skip DbgInfo (NFC).
This patch updates some code responsible the skip debug info to use
BasicBlock::instructionsWithoutDebug. I think this makes things slightly
simpler and more direct.

Reviewers: aprantl, vsk, hans, danielcdh

Reviewed By: hans

Differential Revision: https://reviews.llvm.org/D46252

llvm-svn: 331221
2018-04-30 20:10:53 +00:00
Sam Clegg a165f2d60d [WebAssembly] MC: Improve debug output
llvm-svn: 331220
2018-04-30 19:40:57 +00:00
Krzysztof Parzyszek 1cf329c933 [LivePhysRegs] Remove registers clobbered by regmasks from the live set
Dead defs were being removed from the live set (in stepForward), but
registers clobbered by regmasks weren't (more specifically, they were
actually removed by removeRegsInMask, but then they were added back in).

llvm-svn: 331219
2018-04-30 19:38:47 +00:00
Nirav Dave 6c0665e221 [MC] Change AsmParser to leverage Assembler during evaluation
Teach AsmParser to check with Assembler for when evaluating constant
expressions.  This improves the handing of preprocessor expressions
that must be resolved at parse time. This idiom can be found as
assembling-time assertion checks in source-level assemblers. Note that
this relies on the MCStreamer to keep sufficient tabs on Section /
Fragment information which the MCAsmStreamer does not. As a result the
textual output may fail where the equivalent object generation would
pass. This can most easily be resolved by folding the MCAsmStreamer
and MCObjectStreamer together which is planned for in a separate
patch.

Currently, this feature is only enabled for assembly input, keeping IR
compilation consistent between assembly and object generation.

Reviewers: echristo, rnk, probinson, espindola, peter.smith

Reviewed By: peter.smith

Subscribers: eraman, peter.smith, arichardson, jyknight, hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D45164

llvm-svn: 331218
2018-04-30 19:22:40 +00:00
Florian Hahn 8fe04ad3f7 [LoopSimplify] Use BB::instructionsWithoutDebug to skip DbgInfo (NFC).
This patch updates some code responsible the skip debug info to use
BasicBlock::instructionsWithoutDebug. I think this makes things slightly
simpler and more direct.

Reviewers: aprantl, vsk, chandlerc

Reviewed By: aprantl

Differential Revision: https://reviews.llvm.org/D46253

llvm-svn: 331217
2018-04-30 19:19:36 +00:00
Matt Arsenault 0084adc516 AMDGPU: Add Vega12 and Vega20
Changes by
  Matt Arsenault
  Konstantin Zhuravlyov

llvm-svn: 331215
2018-04-30 19:08:16 +00:00
Roman Tereshin 46f838f370 [MIR] Reset unique MBB numbering in MachineFunction::reset()
No need to waste space nor number MBBs differently if MF gets recreated.

Reviewers: qcolombet, stoklund, t.p.northover, bogner, javed.absar

Reviewed By: qcolombet

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D46078

llvm-svn: 331213
2018-04-30 18:58:57 +00:00
Sanjay Patel 1babf5ff32 [DAGCombiner] rename function attribute for disabling ftrunc transform
This is the matching name change for the Clang patch at:
D46236
rL331209

Differential Revision: https://reviews.llvm.org/D46237 

llvm-svn: 331210
2018-04-30 18:20:33 +00:00
Simon Pilgrim 3c35408e48 [X86] Introduce X86SchedWriteWidths schedule wrapper for different vector widths.
We need to split most of the scheduler classes by vector width to remove more of the InstRW overrides, this patch should make this easier/tidier by allowing us to pass the X86SchedWriteWidths wrapper to multi-width multiclasses and then split as required.

I've included fields for Scl (scalar float/double), MMX (MMX integer), XMM, YMM and ZMM widths. These fields mostly share the same classes but it should give us the flexibility that we may need in the future.

This patch has replaced a set of example SSE/AVX512 instruction cases but isn't exhaustive as it gets very noisy before we really need the functionality.

Differential Revision: https://reviews.llvm.org/D46266

llvm-svn: 331208
2018-04-30 18:18:38 +00:00
Roman Lebedev aa4faec114 [InstCombine] Unfold masked merge with constant mask
Summary:
As discussed in D45733, we want to do this in InstCombine.

https://rise4fun.com/Alive/LGk

Reviewers: spatel, craig.topper

Reviewed By: spatel

Subscribers: chandlerc, xbolva00, llvm-commits

Differential Revision: https://reviews.llvm.org/D45867

llvm-svn: 331205
2018-04-30 17:59:33 +00:00
Ulrich Weigand c3ec80fea1 [SystemZ] Handle SADDO et.al. and ADD/SUBCARRY
This provides an optimized implementation of SADDO/SSUBO/UADDO/USUBO
as well as ADDCARRY/SUBCARRY on top of the new CC implementation.

In particular, multi-word arithmetic now uses UADDO/ADDCARRY instead
of the old ADDC/ADDE logic, which means we no longer need to use
"glue" links for those instructions.  This also allows making full
use of the memory-based instructions like ALSI, which couldn't be
recognized due to limitations in the DAG matcher previously.

Also, the llvm.sadd.with.overflow et.al. intrinsincs now expand to
directly using the ADD instructions and checking for a CC 3 result.

llvm-svn: 331203
2018-04-30 17:54:28 +00:00
Ulrich Weigand b32f3656d2 [SystemZ] Do not use glue to represent condition code dependencies
Currently, an instruction setting the condition code is linked to
the instruction using the condition code via a "glue" link in the
SelectionDAG.  This has a number of drawbacks; in particular, it
means the same CC cannot be used by multiple users.  It also makes
it more difficult to efficiently implement SADDO et. al.

This patch changes the back-end to represent CC dependencies as
normal values during SelectionDAG matching, along the lines of
how this is handled in the X86 back-end already.

In addition to the core mechanics of updating all relevant patterns,
this requires a number of additional changes:

- We now need to be able to spill/restore a CC value into a GPR
  if necessary.  This means providing a copyPhysReg implementation
  for moves involving CC, and defining getCrossCopyRegClass.

- Since we still prefer to avoid such spills, we provide an override
  for IsProfitableToFold to avoid creating a merged LOAD / ICMP if
  this would result in multiple users of the CC.

- combineCCMask no longer requires a single CC user, and no longer
  need to be careful about preventing invalid glue/chain cycles.

- emitSelect needs to be more careful in marking CC live-in to
  the basic block it generates.  Also, we can now optimize the
  case of multiple subsequent selects with the same condition
  just like X86 does.

llvm-svn: 331202
2018-04-30 17:52:32 +00:00
Daniel Sanders 2de9d4ad5d Fix infinite loop after r331115
There are two separate fixes here:
* The lowering code for non-extending loads should report UnableToLegalize instead of emitting the same instruction.
* The target should not be requesting lowering of non-extending loads.

llvm-svn: 331201
2018-04-30 17:20:01 +00:00
Jonas Devlieghere 4bbcb5ab04 [DebugInfo] Prevent infinite recursion for malformed DWARF
This prevents infinite recursion in DWARFDie::findRecursively for
malformed DWARF where a DIE references itself.

This fixes PR36257.

Differential revision: https://reviews.llvm.org/D43092

llvm-svn: 331200
2018-04-30 17:02:41 +00:00
Davide Italiano bd3bf1660b [SLPVectorizer] Debug info shouldn't impact spill cost computation.
<rdar://problem/39794738>

(Also, PR32761).

Differential Revision:  https://reviews.llvm.org/D46199

llvm-svn: 331199
2018-04-30 16:57:33 +00:00
Simon Pilgrim c80a5aa09a [X86][Atom] Remove unnecessary x87 load/move instrw overrides.
llvm-svn: 331198
2018-04-30 16:51:13 +00:00
Tom Stellard add59c052d AMDGPU: Remove some dead code
llvm-svn: 331196
2018-04-30 16:28:02 +00:00
Ulrich Weigand 79e5cd2fc5 [SystemZ] Refactor some VT casts in DAG match patterns
In patterns where we need to specify a result VT, prefer

  [(set (tr.vt tr.op:$V1), (operator ...))]

over

  [(set tr.op:$V1, (tr.vt (operator ...)))]

This is NFC now, but simplifies some future changes.

llvm-svn: 331192
2018-04-30 15:52:28 +00:00
Ulrich Weigand fb56686cd3 [SystemZ] Improve handling of Select pseudo-instructions
If we have LOCR instructions, select them directly from SelectionDAG
instead of first going through a pseudo instruction and then using
the custom inserter to emit the LOCR.

Provide Select pseudo-instructions for VR32/VR64 if we have vector
instructions, to avoid having to go through the first 16 FPRs
unnecessarily.

If we do not have LOCFHR, prefer using LOCR followed by a move
over a conditional branch.

llvm-svn: 331191
2018-04-30 15:49:27 +00:00
Nico Weber da750079fa IWYU for llvm-config.h, removals. Also see r331184.
llvm-svn: 331190
2018-04-30 15:26:01 +00:00
Simon Pilgrim 0a732da261 [X86] Drop unnecessary VPORrm InstrRW override in SkylakeServer.
llvm-svn: 331188
2018-04-30 15:18:33 +00:00
Simon Pilgrim b521ec7525 [X86] Fix SkylakeServer typo in WritePSADBW class - it only uses 1 resource.
llvm-svn: 331187
2018-04-30 15:17:16 +00:00
Tom Stellard 6c81418a63 AMDGPU/GlobalISel: Don't try to lower geometry shaders
Summary: The AMDGPU_GS calling convention is not supported yet.

Reviewers: arsenm, nhaehnle

Reviewed By: nhaehnle

Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D46041

llvm-svn: 331186
2018-04-30 15:15:23 +00:00
Nico Weber 432a38838d IWYU for llvm-config.h in llvm, additions.
See r331124 for how I made a list of files missing the include.
I then ran this Python script:

    for f in open('filelist.txt'):
        f = f.strip()
        fl = open(f).readlines()

        found = False
        for i in xrange(len(fl)):
            p = '#include "llvm/'
            if not fl[i].startswith(p):
                continue
            if fl[i][len(p):] > 'Config':
                fl.insert(i, '#include "llvm/Config/llvm-config.h"\n')
                found = True
                break
        if not found:
            print 'not found', f
        else:
            open(f, 'w').write(''.join(fl))

and then looked through everything with `svn diff | diffstat -l | xargs -n 1000 gvim -p`
and tried to fix include ordering and whatnot.

No intended behavior change.

llvm-svn: 331184
2018-04-30 14:59:11 +00:00
Bjorn Pettersson 9a8483a4b2 [BranchFolding] Salvage DBG_VALUE instructions from empty blocks
Summary:
This patch will introduce copying of DBG_VALUE instructions
from an otherwise empty basic block to predecessor/successor
blocks in case the empty block is eliminated/bypassed. It
is currently only done in one identified situation in the
BranchFolding pass, before optimizing on empty block.
It can be seen as a light variant of the propagation done
by the LiveDebugValues pass, which unfortunately is executed
after the BranchFolding pass.

We only propagate (copy) DBG_VALUE instructions in a limited
number of situations:
 a) If the empty BB is the only predecessor of a successor
    we can copy the DBG_VALUE instruction to the beginning of
    the successor (because the DBG_VALUE instruction is always
    part of the flow between the blocks).
 b) If the empty BB is the only successor of a predecessor
    we can copy the DBG_VALUE instruction to the end of the
    predecessor (because the DBG_VALUE instruction is always
    part of the flow between the blocks). In this case we add
    the DBG_VALUE just before the first terminator (assuming
    that the terminators do not impact the DBG_VALUE).

A future solution, to handle more situations, could perhaps
be to run the LiveDebugValues pass before branch folding?

This fix is related to PR37234. It is expected to resolve
the problem seen, when applied together with the fix in
SelectionDAG from here: https://reviews.llvm.org/D46129

Reviewers: #debug-info, aprantl, rnk

Reviewed By: #debug-info, aprantl

Subscribers: ormris, gbedwell, llvm-commits

Differential Revision: https://reviews.llvm.org/D46184

llvm-svn: 331183
2018-04-30 14:37:46 +00:00
Bjorn Pettersson abafca619b [SelectionDAG] Improve selection of DBG_VALUE using a PHI node result
Summary:
When building the selection DAG at ISel all PHI nodes are
selected and lowered to Machine Instruction PHI nodes before
we start to create any SDNodes. So there are no SDNodes for
values produced by the PHI nodes.

In the past when selecting a dbg.value intrinsic that uses
the value produced by a PHI node we have been handling such
dbg.value intrinsics as "dangling debug info". I.e. we have
not created a SDDbgValue node directly, because there is
no existing SDNode for the PHI result, instead we deferred
the creationg of a SDDbgValue until we found the first use
of the PHI result.

The old solution had a couple of flaws. The position of the
selected DBG_VALUE instruction would end up quite late in a
basic block, and for example not directly after the PHI node
as in the LLVM IR input. And in case there were no use at all
in the basic block the dbg.value could be dropped completely.

This patch introduces a new VREG kind of SDDbgValue nodes.
It is similar to a SDNODE kind of node, but it refers directly
to a virtual register and not a SDNode. When we do selection
for a dbg.value that is using the result of a PHI node we
can do a lookup of the virtual register directly (as it already
is determined for the PHI node) and create a SDDbgValue node
immediately instead of delaying the selection until we find a
use.

This should fix a problem with losing debug info at ISel
as seen in PR37234 (https://bugs.llvm.org/show_bug.cgi?id=37234).
It does not resolve PR37234 completely, because the debug info
is dropped later on in the BranchFolder (see D46184).

Reviewers: #debug-info, aprantl

Reviewed By: #debug-info, aprantl

Subscribers: rnk, gbedwell, aprantl, JDevlieghere, llvm-commits

Differential Revision: https://reviews.llvm.org/D46129

llvm-svn: 331182
2018-04-30 14:37:39 +00:00
Gabor Buella ad9a04295e NFC, Avoid a warning on pointer casting in PassPlugin.cpp
llvm-svn: 331179
2018-04-30 14:21:28 +00:00
Simon Dardis 5a512d63c9 Revert "[mips] Fix the predicates of jump and branch and link instructions"
That commit broke one of the LLD builders, reverting while I investigate.

This patch reverts r331175.

llvm-svn: 331178
2018-04-30 14:03:35 +00:00
Simon Dardis cc95a9c557 [mips] Fix the predicates of jump and branch and link instructions
Reviewers: smaksimovic, atanasyan, abeserminji

Differential Revision: https://reviews.llvm.org/D46114

llvm-svn: 331175
2018-04-30 13:37:42 +00:00
Florian Hahn deb01ea126 [LV] Use BB::instructionsWithoutDebug to skip DbgInfo (NFC).
This patch updates some code responsible the skip debug info to use
BasicBlock::instructionsWithoutDebug. I think this makes things
slightly simpler and more direct.

Reviewers: mkuper, rengolin, dcaballe, aprantl, vsk

Reviewed By: rengolin

Differential Revision: https://reviews.llvm.org/D46254

llvm-svn: 331174
2018-04-30 13:28:08 +00:00
Simon Pilgrim 318f816f49 [X86] Fix typo in skylake-avx512 model for PMAXSD/PMINSD instructions
The PMAXSD/PMINSD instregexs had been written as PMAX(C?)SD - looks like this was a search+replace error when matching float MAXSD/MINSD commutative instructions.

llvm-svn: 331167
2018-04-30 10:46:35 +00:00
Simon Dardis 57c2095d1b [mips] Fix microMIPS loads and stores.
Previously these instructions were unselectable and instead were generated
through the instruction mapping tables.

Reviewers: atanasyan, smaksimovic, abeserminji

Differential Revision: https://reviews.llvm.org/D46055

llvm-svn: 331165
2018-04-30 09:44:44 +00:00
Sander de Smalen 5861c263e0 [AArch64][SVE] Asm: Improve diagnostics for gather loads.
This patch extends the 'isSVEVectorRegWithShiftExtend' function to 
improve diagnostics for SVE's gather load (scalar + vector) addressing 
modes. Instead of always suggesting the 'unscaled' addressing mode, 
the use of DiagnosticPredicate enables a more specific error message
in the context where the scaling is incorrect. For example:

  ld1h z0.d, p0/z, [x0, z0.d, lsl #2]
                                   ^ 
           shift amount should be '1'

Instead of suggesting the packed, unscaled addressing mode:
  expected 'z[0..31].d, (uxtw|sxtw)'

the assembler now suggests using the proper scaling:
  expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'

Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D46124

llvm-svn: 331162
2018-04-30 07:24:38 +00:00
Craig Topper 5a4c88005c [X86] Add a Requires<[In64BitMode]> to FARJMP64
Otherwise we can try to assemble it in 32-bit mode and throw an assert in the encoder.

llvm-svn: 331161
2018-04-30 06:21:24 +00:00