94b5a80b93
Change instruction description to split OperandList into OutOperandList and
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InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 01:14:50 +00:00
9d41b311fb
Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit.
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llvm-svn: 38501
2007-07-10 18:08:01 +00:00
881248c4e1
No need for ccop anymore.
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llvm-svn: 37965
2007-07-06 23:34:09 +00:00
76a97c5f8a
Do away with ImmutablePredicateOperand.
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llvm-svn: 37961
2007-07-06 23:22:46 +00:00
5c66888580
PredicateDefOperand -> OptionalDefOperand.
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llvm-svn: 37931
2007-07-06 01:00:49 +00:00
085314b455
Unbreak the build.
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llvm-svn: 37914
2007-07-05 17:13:19 +00:00
aa3b8014bd
Each ARM use predicate operand is now made up of two components. The new component is the CPSR register.
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llvm-svn: 37895
2007-07-05 07:13:32 +00:00
e8c1e428f2
Revert the earlier change that removed the M_REMATERIALIZABLE machine
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instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).
llvm-svn: 37728
2007-06-26 00:48:07 +00:00
0c550df9d2
Fix the build.
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llvm-svn: 37705
2007-06-22 16:59:54 +00:00
c3c949b473
Allow predicated immediate ARM to ARM calls.
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llvm-svn: 37659
2007-06-19 21:05:09 +00:00
9e82064924
Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
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with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.
llvm-svn: 37644
2007-06-19 01:48:05 +00:00
a7ca624028
Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.
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llvm-svn: 37643
2007-06-19 01:26:51 +00:00
e8c3cbf971
Mark these instructions clobbersPred. They modify the condition code register.
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llvm-svn: 37468
2007-06-06 10:17:05 +00:00
9aa5fc8577
Opcode modifier s comes after condition code. e.g. addlts, not addslt.
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llvm-svn: 37388
2007-06-01 20:51:29 +00:00
a2ab4e5feb
Make jumptable non-predicable for now.
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llvm-svn: 37381
2007-06-01 00:56:15 +00:00
a6e9a4ce07
For ldrb, strh, etc., the condition code is before the width specifier. e.g. streqh, not strheq.
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llvm-svn: 37349
2007-05-29 23:32:06 +00:00
d1de276c16
Use AXI3 not AXI2 for appropriate PIC PC-relative loads and stores. Cosmetic.
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llvm-svn: 37271
2007-05-21 22:42:04 +00:00
7d55f3733e
Add some patterns for PIC PC-relative loads and stores.
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llvm-svn: 37269
2007-05-21 22:14:33 +00:00
4ae1840d21
Mark calls non-predicable for now. Need to ensure it's the last instruction in the if-converted block or make sure it preserve condition code.
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llvm-svn: 37199
2007-05-18 01:53:54 +00:00
dcd6cdf896
Make ARM::B isPredicable; Make Bcc and MOVCC condition option a normal operand so they are not predicable.
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llvm-svn: 37118
2007-05-16 20:50:01 +00:00
01a4227ed1
Conditional branch is not a barrier.
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llvm-svn: 37103
2007-05-16 07:45:54 +00:00
0f7cbe8370
Add PredicateOperand to all ARM instructions that have the condition field.
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llvm-svn: 37066
2007-05-15 01:29:07 +00:00
9c031c0ddf
Switch BCC, MOVCCr, etc. to PredicateOperand.
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llvm-svn: 36948
2007-05-08 21:08:43 +00:00
7e7280b538
change per review
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llvm-svn: 36519
2007-04-28 00:36:37 +00:00
29c05756b5
Prevent Thumb code from generating ARM instructions
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llvm-svn: 36518
2007-04-27 22:17:18 +00:00
c39c12a3fa
ARM TLS: implement "general dynamic", "initial exec" and "local exec" models.
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llvm-svn: 36506
2007-04-27 13:54:47 +00:00
598bc0d9a3
dag combiner just got better at pruning bits. This fixes CodeGen/ARM/rev.ll
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llvm-svn: 36222
2007-04-17 22:39:58 +00:00
6be85337b0
- Divides the comparisons in two types: comparisons that only use N and Z
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flags (ARMISD::CMPNZ) and comparisons that use all flags (ARMISD::CMP).
- Defines the instructions: TST, TEQ (ARM) and TST (Thumb).
llvm-svn: 35573
2007-04-02 01:30:03 +00:00
143b0dff31
bugfix: sometimes the spiller puts a load between the "mov lr, pc" and "bx" of a CALL_NOLINK.
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llvm-svn: 35381
2007-03-27 16:19:21 +00:00
a88c4a74f3
bugfix: When the source register of CALL_NOLINK was LR, the following code was emitted:
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mov lr, pc
bx lr
So, the function was not called.
llvm-svn: 35218
2007-03-20 17:57:23 +00:00
9e7b838469
Make two piece constant generation as a single instruction. It's re-materialized as a load from constantpool.
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llvm-svn: 35207
2007-03-20 08:11:30 +00:00
9bb01c9f4f
Fix naming inconsistencies.
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llvm-svn: 35163
2007-03-19 07:48:02 +00:00
ee2763f76f
Special LDR instructions to load from non-pc-relative constantpools. These are
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rematerializable. Only used for constant generation for now.
llvm-svn: 35162
2007-03-19 07:20:03 +00:00
5be3e09a30
Constant generation instructions are re-materializable.
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llvm-svn: 35161
2007-03-19 07:09:02 +00:00
456db39ea9
ARM callseq_end should have a input flag operand so it would be scheduled right after the call.
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llvm-svn: 33832
2007-02-03 09:11:58 +00:00
83f35170fa
- Fix codegen for pc relative constant (e.g. JT) in thumb mode:
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.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
add r1, pc, #PCRELV0
This is not legal since add r1, pc, #c requires the constant be a multiple of 4.
Do the following instead:
.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
mov r1, #PCRELV0
add r1, pc
- In thumb mode, it's not possible to use .set generate a pc relative stub
address. The stub is ARM code which is in a different section from the thumb
code. Load the value from a constpool instead.
- Some asm printing clean up.
llvm-svn: 33664
2007-01-30 20:37:08 +00:00
f9e5445ed4
Make LABEL a builtin opcode.
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llvm-svn: 33537
2007-01-26 14:34:52 +00:00
77c15ded10
Code clean up. Use def : pat instead of defining new instructions.
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llvm-svn: 33368
2007-01-19 20:27:35 +00:00
10043e215b
ARM backend contribution from Apple.
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llvm-svn: 33353
2007-01-19 07:51:42 +00:00
fd68718467
implement missing compares
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patch by Lauro
bug fixed by me
llvm-svn: 32795
2006-12-31 18:52:39 +00:00
7251e57ff8
Implement SELECT_CC (f32/f64) for ARM.
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llvm-svn: 32762
2006-12-28 13:11:14 +00:00
865b979833
remove duplicated line
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bug noticed by Lauro
llvm-svn: 32761
2006-12-28 12:51:40 +00:00
d0ced3f1e8
This patch defines extloadi1 and fixes an internal compiler error on
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arm.
llvm-svn: 32760
2006-12-26 19:30:42 +00:00
67d1c8ae0e
more general matching of the MVN instruction
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llvm-svn: 32484
2006-12-12 17:10:13 +00:00
9fa0a26808
use MVN to handle small negative constants
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llvm-svn: 32459
2006-12-12 01:03:11 +00:00
1bbe581d0f
add mvn
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llvm-svn: 32454
2006-12-12 00:37:38 +00:00
87f4382163
fix truncstorei1
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llvm-svn: 32364
2006-12-08 18:41:21 +00:00
5f7ab1b964
implement load effective address similar to the alpha backend
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remove lea_addri and the now unused memri addressing mode
llvm-svn: 31592
2006-11-09 13:58:55 +00:00
708cb60588
initial implementation of addressing mode 2
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TODO: fix lea_addri
llvm-svn: 31552
2006-11-08 17:07:32 +00:00
9ac6442db6
remove dead/redundant vars
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llvm-svn: 31435
2006-11-03 23:48:56 +00:00
Evan Cheng