e59eef3dd1
revert r117858 while I check out a failure I missed.
...
llvm-svn: 117859
2010-10-31 19:05:32 +00:00
9293008e90
the asm matcher can't handle operands with modifiers (like ${foo:bar}).
...
Instead of silently ignoring these instructions, emit a hard error and
force the target author to either refactor the target or mark the
instruction 'isCodeGenOnly'.
Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are
doing this.
llvm-svn: 117858
2010-10-31 18:48:12 +00:00
f49540cb4f
Kill of the vestiges of the 'call' Modifier (no longer needed for PLT).
...
llvm-svn: 115845
2010-10-06 21:36:43 +00:00
49d4c0bd18
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This
...
allow target to correctly compute latency for cases where static scheduling
itineraries isn't sufficient. e.g. variable_ops instructions such as
ARM::ldm.
This also allows target without scheduling itineraries to compute operand
latencies. e.g. X86 can return (approximated) latencies for high latency
instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
e.g. ldm and those used by store multiple instructions, e.g. stm.
llvm-svn: 115755
2010-10-06 06:27:31 +00:00
fae8305e2b
Nuke the rest of the :comment references
...
llvm-svn: 115373
2010-10-01 23:21:38 +00:00
c8e2e9d830
Nuke a few more unused asm strings
...
llvm-svn: 115193
2010-09-30 19:53:58 +00:00
b9429179f9
The asm strings are never used at all, so just nuke 'em entirely.
...
llvm-svn: 115160
2010-09-30 16:56:53 +00:00
4a9cb8f10e
Go ahead and jump!
...
Now that the MC lowering handles the expansion of the pseudos, kill the horrible
blobs of text.
llvm-svn: 115130
2010-09-30 02:18:06 +00:00
2fb20b1d37
ARM instruction itinerary fixes:
...
1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones.
2. Cortex-a9 is out-of-order so model all read cycles as cycle 1.
3. Lots of other random fixes for A8 and A9.
llvm-svn: 115121
2010-09-30 01:08:25 +00:00
2259d67a33
Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn.
...
llvm-svn: 115010
2010-09-29 00:49:25 +00:00
c35d7bbe43
Assign bitwise binary instructions different itinerary classes from ALU instructions such as add / sub.
...
llvm-svn: 115008
2010-09-29 00:27:46 +00:00
2c5df619c4
Revert r114703 and r114702, removing the isConditionalMove flag from instructions. After further
...
reflection, this isn't going to achieve the purpose I intended it for. Back to the drawing board!
llvm-svn: 114710
2010-09-23 23:45:25 +00:00
bd57e0ce3d
Add isConditionalMove bits to X86 and ARM instructions.
...
llvm-svn: 114703
2010-09-23 22:57:01 +00:00
8503054410
Clean up the 'trap' instruction printing a bit. Non-Darwin assemblers don't
...
(yet) recognize the 'trap' mnemonic, so we use .short/.long to emit the
opcode directly. On Darwin, however, we do want the mnemonic for more
readable assembly code and better disassembly.
Adjust the .td file to use the 'trap' mnemonic and handle using the binutils
workaround in the assembly printer. Also tweak the formatting of the opcode
values to make them consistent between the MC printer and the old printer.
llvm-svn: 114679
2010-09-23 18:05:37 +00:00
22f6922505
set isCompare for another three Thumb1 instructions
...
llvm-svn: 113867
2010-09-14 22:00:50 +00:00
2afac8e9bd
set comparable for a bunch of Thumb instructions
...
llvm-svn: 113849
2010-09-14 20:47:43 +00:00
367a5df8cf
For each instruction itinerary class, specify the number of micro-ops each
...
instruction in the class would be decoded to. Or zero if the number of
uOPs must be determined dynamically.
This will be used to determine the cost-effectiveness of predicating a
micro-coded instruction.
llvm-svn: 113513
2010-09-09 18:18:55 +00:00
9877af3b46
grammar tweak
...
llvm-svn: 113289
2010-09-07 21:30:25 +00:00
fef37287a8
Make ARM add rN, sp, #imm instructions rematerializable. That's how the address of locals is calculated, so this should
...
help relieve register pressure a bit. Recalculating the local address is
almost always going to be better than spilling.
llvm-svn: 112503
2010-08-30 19:49:58 +00:00
fa16acae44
Delete some unused instructions.
...
llvm-svn: 110710
2010-08-10 19:36:22 +00:00
b128824b60
Move newlines before inline jumptables from the asm strings in .td files to
...
the jtblock_operand print methods. This avoids extra newlines in the
disassembler's output. PR7757.
llvm-svn: 109948
2010-07-31 06:28:10 +00:00
523e554afa
LEApcrelJT shouldn't be marked as neverHasSideEffects, as we don't want it
...
being moved around away from the jump table it references. rdar://8104340
llvm-svn: 106483
2010-06-21 21:27:27 +00:00
84511e1526
Clean up 80 column violations. No functional change.
...
llvm-svn: 105350
2010-06-02 21:53:11 +00:00
0b20fdaff0
Cosmetic cleanup. No functional change.
...
llvm-svn: 104974
2010-05-28 17:51:20 +00:00
37eb2c24b9
make sure accesses to set up the jmpbuf don't get moved after it by the scheduler. Add a missing \n.
...
llvm-svn: 104967
2010-05-28 17:37:40 +00:00
faa3abbe39
Update the saved stack pointer in the sjlj function context following either
...
an alloca() or an llvm.stackrestore(). rdar://8031573
llvm-svn: 104900
2010-05-27 23:49:24 +00:00
a6897ecbb5
fix off by 1 (insn) error in eh.sjlj.setjmp thumb code sequence.
...
llvm-svn: 104661
2010-05-26 01:22:21 +00:00
bd9485db63
Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit.
...
Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.
llvm-svn: 104419
2010-05-22 01:06:18 +00:00
daeca2d156
t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoist more loads during machine LICM.
...
llvm-svn: 104115
2010-05-19 07:28:01 +00:00
dd7f566597
Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects.
...
llvm-svn: 104111
2010-05-19 06:07:03 +00:00
2c452fcd14
Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM.
...
llvm-svn: 104102
2010-05-19 01:52:25 +00:00
c601801a7e
Fix a regression in 464.h264 for thumb1 and thumb2 nightly tests.
...
Obvious in retrospect but not fun to debug.
llvm-svn: 103969
2010-05-17 20:31:13 +00:00
497d831966
Chris said that the comment char should be escaped. Fix all the occurences of "@" in *.td
...
llvm-svn: 103903
2010-05-16 09:15:36 +00:00
2b7aace2e0
"trap" pseudo-op turned out to be apple-local.
...
Temporary emit it as raw bytes until it will be added to binutils as well.
llvm-svn: 103878
2010-05-15 17:19:20 +00:00
2fa5a7e7e4
Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction.
...
llvm-svn: 103459
2010-05-11 07:26:32 +00:00
0433699ef0
set SDNPVariadic on nodes throughout the rest of the targets that
...
need them.
llvm-svn: 98937
2010-03-19 05:33:51 +00:00
d6243b49d4
Remove the writeback flag from ARM's address mode 4. Now that we have separate
...
instructions for ld/st with writeback, the flag is completely redundant.
llvm-svn: 98643
2010-03-16 17:46:45 +00:00
947f04bad0
Change ARM ld/st multiple instructions to have variant instructions for
...
writebacks to the address register. This gets rid of the hack that the
first register on the list was the magic writeback register operand. There
was an implicit constraint that if that operand was not reg0 it had to match
the base register operand. The post-RA scheduler's antidependency breaker
did not understand that constraint and sometimes changed one without the
other. This also fixes Radar 7495976 and should help the verifier work
better for ARM code.
There are now new ld/st instructions explicit writeback operands and explicit
constraints that tie those registers together.
llvm-svn: 98409
2010-03-13 01:08:20 +00:00
9a3e2398ae
Factored out the disassembly printing of CPS option, MSR mask, and Negative Zero
...
operands into their own PrintMethod, in order not to pollute the printOperand()
impl with disassembly only Imm modifiers.
llvm-svn: 98172
2010-03-10 18:59:38 +00:00
1d63b9574d
Modified the asm string of 16-bit Thumb MUL instruction so that it prints:
...
MULS <Rdm>, <Rn>, <Rdm>
according to A8.6.105 MUL Encoding T1.
llvm-svn: 97675
2010-03-03 23:15:43 +00:00
44908a5e17
Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL,
...
SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.
llvm-svn: 97573
2010-03-02 18:14:57 +00:00
8c5d683aa9
The mayHaveSideEffects flag is no longer used.
...
llvm-svn: 97348
2010-02-27 23:47:46 +00:00
74cca5a989
Added the following 16-bit Thumb instructions for disassembly only: YIELD, WFE,
...
WFI, SEV, SETEND.
llvm-svn: 97149
2010-02-25 17:51:03 +00:00
90adefcf7e
Added tNOP for disassembly only.
...
llvm-svn: 97105
2010-02-25 03:28:51 +00:00
57656da73f
Added tSVC and tTRAP for disassembly only.
...
llvm-svn: 97098
2010-02-25 02:21:11 +00:00
45fceea0e4
Updated version of r96634 (which was reverted due to failing 176.gcc and
...
126.gcc nightly tests. These failures uncovered latent bugs that machine DCE
could remove one half of a stack adjust down/up pair, causing PEI to assert.
This update fixes that, and the tests now pass.
llvm-svn: 96822
2010-02-22 23:10:38 +00:00
3e2cad3b1a
80 column cleanup
...
llvm-svn: 96393
2010-02-16 21:23:02 +00:00
fba7fce5be
Remove trailing whitespace
...
llvm-svn: 96388
2010-02-16 21:07:46 +00:00
f40b8e03fb
Added BKPT/tBKPT (breakpoint) to the instruction table for disassembly purpose.
...
llvm-svn: 95884
2010-02-11 18:12:29 +00:00
f7279bd10f
Radar 7417921
...
tMOVCCi pattern only valid for low registers, as the Thumb1 mov immediate to
register instruction only works with low registers. Allowing high registers
for the instruction resulted in the assembler choosing the wide (32-bit)
encoding for the mov, but LLVM though the instruction was only 16 bits wide,
so offset calculations for constant pools became incorrect, leading to
out of range constant pool entries.
llvm-svn: 95686
2010-02-09 19:51:37 +00:00
a570d05228
tighten up eh.setjmp sequence a bit.
...
llvm-svn: 95603
2010-02-08 23:22:00 +00:00
a3575ca846
Adjust setjmp instruction sequence to not need 32-bit alignment padding
...
llvm-svn: 94627
2010-01-27 00:07:20 +00:00
267430f74d
Fix PR5694. The CMN instructions set the flags differently from CMP, so they
...
cannot be directly interchanged for comparisons against negated values.
Disable the CMN instructions for the time being.
llvm-svn: 94119
2010-01-22 00:08:13 +00:00
27f000a9af
The most significant encoding bit of GPR:$src or GPR:$dst was over-specified in
...
the various MOV (register) instructions (16-bit Thumb), including tBRIND (the
indirect branch). Instead of '1', it should be specified as '?', because GPR
only specifies the register class, which includes both hi-and-lo registers.
llvm-svn: 93759
2010-01-18 20:15:56 +00:00
0f45f4f849
Added 16-bit Thumb Load/Store immediate instructions with encoding bits so that
...
the disassembler can properly decode Load/Store register/immediate instructions.
llvm-svn: 93471
2010-01-14 22:42:17 +00:00
b34888b6d0
Fixed a couple of places for Thumb MOV where encoding bits are underspecified.
...
llvm-svn: 93349
2010-01-13 21:00:26 +00:00
a94837dc24
Remove the JustSP single-register regclass.
...
It was only being used by instructions with the t_addrmode_sp addressing mode,
and that is pattern matched in a way that guarantees SP is used. There is
never any register allocation done from this class.
llvm-svn: 93280
2010-01-13 00:43:06 +00:00
b05fbe1486
Add a SPR register class to the ARM target.
...
Certain Thumb instructions require only SP (e.g. tSTRspi).
llvm-svn: 91944
2009-12-22 23:54:44 +00:00
7f30b64dce
Renamed "tCMNZ" to "tCMNz" to be consistent with other similar namings.
...
llvm-svn: 91571
2009-12-16 23:36:52 +00:00
466231ab92
Add encoding bits for some Thumb instructions. Plus explicitly set the top two
...
bytes of Inst to 0x0000 for the benefit of the Thumb decoder.
llvm-svn: 91496
2009-12-16 02:32:54 +00:00
c28e629c2d
Added encoding bits for the Thumb ISA. Initial checkin.
...
llvm-svn: 91434
2009-12-15 17:24:14 +00:00
36d4dec28a
Thumb1 exception handling setjmp
...
llvm-svn: 90246
2009-12-01 18:10:36 +00:00
bdb43a9d99
Remat VLDRD from constpool. Clean up some instruction property specifications.
...
llvm-svn: 89478
2009-11-20 19:57:15 +00:00
b18525937c
More consistent thumb1 asm printing.
...
llvm-svn: 89328
2009-11-19 06:57:41 +00:00
207b246650
- Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative
...
load of a GV from constantpool and then add pc. It allows the code sequence to
be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
to this pass. This is done before post regalloc scheduling to allow the
scheduler to proper schedule these instructions. It also allow them to be
if-converted and shrunk by later passes.
llvm-svn: 86304
2009-11-06 23:52:48 +00:00
c63943018f
The .n suffix must go after the predicate.
...
llvm-svn: 86019
2009-11-04 07:38:48 +00:00
3f1a92468a
Use ldr.n to workaround a darwin assembler bug.
...
llvm-svn: 85980
2009-11-04 00:00:39 +00:00
064c5fef11
For Thumb indirect branches, use "mov pc, reg" which does not switch
...
between ARM/Thumb modes and does not require the low bit of the target
address to be set for Thumb.
llvm-svn: 85874
2009-11-03 06:29:56 +00:00
1c66e8a6b7
Put BlockAddresses into ARM constant pools.
...
llvm-svn: 85824
2009-11-02 20:59:23 +00:00
6f29ad9170
Use cbz and cbnz instructions.
...
llvm-svn: 85698
2009-10-31 23:46:45 +00:00
1cf0b03064
Add ARM codegen for indirect branches.
...
clang/test/CodeGen/indirect-goto.c runs! (unoptimized)
llvm-svn: 85577
2009-10-30 05:45:42 +00:00
453d64c9f5
Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a
...
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.
llvm-svn: 85517
2009-10-29 18:10:34 +00:00
73789b848d
Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the
...
opcode and operand with a tab. Check for these instructions in the usual
places.
llvm-svn: 85411
2009-10-28 18:26:41 +00:00
b02bdb4552
Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space.
...
llvm-svn: 85184
2009-10-27 00:08:59 +00:00
1b2b64f618
Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple,
...
ld / st pairs, etc.
llvm-svn: 83197
2009-10-01 08:22:27 +00:00
3bbc6c3ae6
Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions.
...
llvm-svn: 83191
2009-10-01 01:33:39 +00:00
bcad0c8421
Add "isBarrier = 1" to return instructions.
...
Patch by Sylvere Teissier.
llvm-svn: 83135
2009-09-30 01:35:11 +00:00
a1c6495af7
Remove comments which don't add much to .s readibility.
...
llvm-svn: 81306
2009-09-09 01:38:23 +00:00
d93c668f00
Calls clobber FPSCR.
...
llvm-svn: 80956
2009-09-03 22:12:28 +00:00
4f835f1d7d
Remove .n suffix for some 16-bit opcodes now that Darwin assembler is fixed.
...
llvm-svn: 80615
2009-08-31 20:14:07 +00:00
4047b53a40
Print a nl before pic labels so they start at a new line. This makes assembly more readable.
...
llvm-svn: 80350
2009-08-28 06:59:37 +00:00
6da267de23
v4, v5 does not support sxtb / sxth.
...
llvm-svn: 80322
2009-08-28 00:31:43 +00:00
ceffeb6abd
Rename ARM "lane_cst" operands to "nohash_imm" since they are used for
...
several things other than Neon vector lane numbers. For inline assembly
operands with a "c" print code, check that they really are immediates.
llvm-svn: 79676
2009-08-21 21:58:55 +00:00
01de985ae6
Fix an obvious copy-n-paste bug.
...
llvm-svn: 79535
2009-08-20 17:01:04 +00:00
a7c2dfbca1
Update Cortex-A8 instruction itineraries for integer instructions.
...
llvm-svn: 79436
2009-08-19 18:00:44 +00:00
dd406177de
Fix revsh pattern.
...
llvm-svn: 79318
2009-08-18 05:43:23 +00:00
e41903b10d
Also shrink immediate branches; also more assembler workarounds.
...
llvm-svn: 79014
2009-08-14 18:31:44 +00:00
db73d68cbe
Shrink ADR and LDR from constantpool late during constantpool island pass.
...
llvm-svn: 78970
2009-08-14 00:32:16 +00:00
a9c2aad939
Finalize itineraries for cortex-a8 integer multiply
...
llvm-svn: 78908
2009-08-13 15:51:13 +00:00
b369ee4c48
Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one.
...
llvm-svn: 78827
2009-08-12 18:31:53 +00:00
bb2af3555c
Shrink Thumb2 movcc instructions.
...
llvm-svn: 78790
2009-08-12 05:17:19 +00:00
fd10869d4b
80 col violation.
...
llvm-svn: 78778
2009-08-12 02:03:03 +00:00
f6a9d06241
Shrinkify Thumb2 r = add sp, imm.
...
llvm-svn: 78745
2009-08-11 23:00:31 +00:00
cc9ca3500d
Shrinkify Thumb2 load / store multiple instructions.
...
llvm-svn: 78717
2009-08-11 21:11:32 +00:00
9f94459d24
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
...
the latter is capable of representing either a primitive or an extended type.
llvm-svn: 78713
2009-08-11 20:47:22 +00:00
53aa7a960c
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
...
llvm-svn: 78610
2009-08-10 22:56:29 +00:00
51cbd2d6c4
Add support to reduce most of 32-bit Thumb2 arithmetic instructions.
...
llvm-svn: 78550
2009-08-10 02:37:24 +00:00
cfed3005e5
Use subclassing to print lane-like immediates (w/o hash) eliminating
...
'no_hash' modifier. Hopefully this will make Daniel happy :)
llvm-svn: 78514
2009-08-08 23:10:41 +00:00
274fcbe43e
tADDhirr should target GPR, not tGPR.
...
llvm-svn: 78454
2009-08-08 03:19:44 +00:00
317bd7aab2
tBfar is bl, which clobbers LR.
...
llvm-svn: 78370
2009-08-07 05:45:07 +00:00
b972e5633f
It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.
...
This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.
This fixes PR4659 and PR4682.
llvm-svn: 78361
2009-08-07 00:34:42 +00:00
b062c236c5
Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary.
...
llvm-svn: 78321
2009-08-06 16:52:47 +00:00
7cc6aca1e6
Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode.
...
llvm-svn: 78126
2009-08-04 23:47:55 +00:00
6ab54fdb0a
Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the same
...
instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.
Also, we should be using BLX to call external function stubs.
llvm-svn: 77756
2009-08-01 00:16:10 +00:00
175bd14967
Make sure Thumb2 uses the right call instructions.
...
llvm-svn: 77507
2009-07-29 21:26:42 +00:00
0d98d8b8b3
- Fix an obvious copy and paste error.
...
- Darwin Thumb2 call clobbers r9.
llvm-svn: 77500
2009-07-29 20:10:36 +00:00
c8bed03349
In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in).
...
llvm-svn: 77364
2009-07-28 20:53:24 +00:00
e5b969f6a6
Remove TPat. No patterns depend on just isThumb(). Must use either T1Pat (isThumb1Only()) or T2Pat (is Thumb2).
...
llvm-svn: 77242
2009-07-27 19:59:26 +00:00
faede73a32
Rename tMOVhi2lor to tMOVgpr2tgpr. It's not moving from a high register to a low register. It's moving from a GPR register class to a more restrictive tGPR class. Also change tMOVlor2hir, and tMOVhir2hir.
...
llvm-svn: 77172
2009-07-26 23:59:01 +00:00
95a73e2eab
Since we have moved unified assembly, switch to ADR instruction instead of a the difficult-to-read .set + add syntax to materialize pc-relative address.
...
Turns out this also fixed a poor code selection on Thumb1. I have no idea why we were using a mov + add to do the same thing as ADR before.
llvm-svn: 76889
2009-07-23 18:26:03 +00:00
e270d4a4dd
Use getTargetConstant instead of getConstant since it's meant as an constant operand.
...
llvm-svn: 76803
2009-07-22 22:03:29 +00:00
4b02b2f79c
Don't forget D16 - D31 are clobbered by calls and sjlj eh.
...
llvm-svn: 76729
2009-07-22 06:46:53 +00:00
6253a19651
Add R12 to the list of registers clobbered by 16-bit Thumb calls as a pre-caution. r12 could be live once we have mixed 32-bit and 16-bit instructions.
...
llvm-svn: 76728
2009-07-22 06:37:28 +00:00
38e88cb53f
Do not select tSXTB / tSXTH in thumb2 mode.
...
llvm-svn: 76600
2009-07-21 18:15:26 +00:00
aaf48343fb
Fix tSUBspi operand definition. It reads and writes sp, which is a high register.
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llvm-svn: 76155
2009-07-17 05:43:12 +00:00
bd9ba429ca
1. In Thumb mode, select tBx instead of ARM variants.
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2. BX does not "use" the link register, it defines it.
3. Fix a couple more places in thumb td file that still uses pre-UAL syntax.
llvm-svn: 75585
2009-07-14 01:49:27 +00:00
0794c6a083
Smarter isel of ldrsb / ldrsh. Only make use of these when [r,r] address is feasible.
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llvm-svn: 75360
2009-07-11 07:08:13 +00:00
cd4cdd1157
Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically.
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A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.
llvm-svn: 75359
2009-07-11 06:43:01 +00:00
61671c87a7
We don't need separate thumb1 instructions tADDSi3 etc. for addc and subc. The "normal" version always modify condition register CPSR so we should just use def : pat to match to the same instructions.
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llvm-svn: 75219
2009-07-10 02:09:04 +00:00
0f9cce7951
Add a thumb2 pass to insert IT blocks.
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llvm-svn: 75218
2009-07-10 01:54:42 +00:00
26b2ba4285
Added Thumb IT instruction.
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llvm-svn: 75198
2009-07-09 23:43:36 +00:00
22c2fba978
Use common code for both ARM and Thumb-2 instruction and register info.
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llvm-svn: 75067
2009-07-08 23:10:31 +00:00
af7451b674
Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first.
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llvm-svn: 75010
2009-07-08 16:09:28 +00:00
27303cde82
Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table.
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llvm-svn: 74543
2009-06-30 18:04:13 +00:00
57726817aa
A few more load instructions.
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llvm-svn: 74500
2009-06-30 02:15:48 +00:00
dbf11ba800
Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative.
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llvm-svn: 74423
2009-06-29 15:33:01 +00:00
b23b50d54d
Implement Thumb2 ldr.
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After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.
llvm-svn: 74420
2009-06-29 07:51:04 +00:00
eab9ca7ea6
Renaming for consistency.
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llvm-svn: 74368
2009-06-27 02:26:13 +00:00
9643ba8123
tst is also commutable.
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llvm-svn: 74236
2009-06-26 00:19:07 +00:00
e85169cd1b
Add Def/Use of CPSR for Thumb-1 instructions.
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llvm-svn: 74219
2009-06-25 22:49:55 +00:00
e892e8bfaf
Test commit
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llvm-svn: 74185
2009-06-25 17:52:32 +00:00
b566ab7b97
Some reorg and additional comments.
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llvm-svn: 74152
2009-06-25 01:05:06 +00:00
83f979a48b
Add Thumb2 pc relative add.
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llvm-svn: 74141
2009-06-24 23:47:58 +00:00
bec1dba896
Add IsThumb1Only to most 16-bit thumb instructions since we want to isel 32-bit instructions when they are available.
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llvm-svn: 73985
2009-06-23 19:38:13 +00:00
e67b77028e
Add explicit types for shift count constants. This is in preparation for
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another change that makes the types ambiguous (at least as far as tablegen
is concerned).
llvm-svn: 73909
2009-06-22 22:08:29 +00:00
d984158320
Mark a few Thumb instructions commutable; just happened to spot this
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while experimenting. I'm reasonably sure this is correct, but please
tell me if these instructions have some strange property which makes this
change unsafe.
llvm-svn: 73746
2009-06-19 01:43:08 +00:00
d93b5b672f
Mark some pattern-less instructions as neverHasSideEffects.
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llvm-svn: 73252
2009-06-12 20:46:18 +00:00
46632d89bb
correct register class for tADDspi to GPR since the register will always be SP
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llvm-svn: 71602
2009-05-12 22:30:18 +00:00
fde2110aa9
PR2985 / <rdar://problem/6584986>
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When compiling in Thumb mode, only the low (R0-R7) registers are available
for most instructions. Breaking the low registers into a new register class
handles this. Uses of R12, SP, etc, are handled explicitly where needed
with copies inserted to move results into low registers where the rest of
the code generator can deal with them.
llvm-svn: 68545
2009-04-07 20:34:09 +00:00
669f1d0b0b
remove trailing whitespace
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llvm-svn: 67874
2009-03-27 23:06:27 +00:00
69cc2cbbff
Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.
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llvm-svn: 60487
2008-12-03 18:15:48 +00:00
effb894453
Rename ConstantSDNode::getValue to getZExtValue, for consistency
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with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.
llvm-svn: 56159
2008-09-12 16:56:44 +00:00
ee98fa9db2
More refactoring.
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llvm-svn: 55528
2008-08-29 06:41:12 +00:00
1ea55cf816
This commit changes:
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1. Legalize now always promotes truncstore of i1 to i8.
2. Remove patterns and gunk related to truncstore i1 from targets.
3. Rename the StoreXAction stuff to TruncStoreAction in TLI.
4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions.
5. Mark a wide variety of invalid truncstores as such in various targets, e.g.
X86 currently doesn't support truncstore of any of its integer types.
6. Add legalize support for truncstores with invalid value input types.
7. Add a dag combine transform to turn store(truncate) into truncstore when
safe.
The later allows us to compile CodeGen/X86/storetrunc-fp.ll to:
_foo:
fldt 20(%esp)
fldt 4(%esp)
faddp %st(1)
movl 36(%esp), %eax
fstps (%eax)
ret
instead of:
_foo:
subl $4, %esp
fldt 24(%esp)
fldt 8(%esp)
faddp %st(1)
fstps (%esp)
movl 40(%esp), %eax
movss (%esp), %xmm0
movss %xmm0, (%eax)
addl $4, %esp
ret
llvm-svn: 46140
2008-01-17 19:59:44 +00:00
94de7bc3aa
get def use info more correct.
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llvm-svn: 45821
2008-01-10 05:12:37 +00:00
7250120177
Only mark instructions that load a single value without extension as isSimpleLoad = 1.
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llvm-svn: 45727
2008-01-07 23:56:57 +00:00
a4ce4f6987
rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.
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llvm-svn: 45667
2008-01-06 23:38:27 +00:00
10324d0175
rename isStore -> mayStore to more accurately reflect what it captures.
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llvm-svn: 45656
2008-01-06 08:36:04 +00:00
f4d55ec4e8
remove explicit isStore flags that are now inferrable.
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llvm-svn: 45653
2008-01-06 05:55:01 +00:00
f3ebc3f3d2
Remove attribution from file headers, per discussion on llvmdev.
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llvm-svn: 45418
2007-12-29 20:36:04 +00:00
f359fed9f9
Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stack
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adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in
the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If
not, then there is the potential for the stack to be changed while the stack's
being used by another instruction (like a call).
This can only result in tears...
llvm-svn: 44037
2007-11-13 00:44:25 +00:00
3e18e504ae
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.
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llvm-svn: 41863
2007-09-11 19:55:27 +00:00
f7c6effc44
Initial JIT support for ARM by Raul Fernandes Herbster.
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llvm-svn: 40887
2007-08-07 01:37:15 +00:00
ac1591be42
No more noResults.
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llvm-svn: 40132
2007-07-21 00:34:19 +00:00
94b5a80b93
Change instruction description to split OperandList into OutOperandList and
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InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 01:14:50 +00:00
9d41b311fb
Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit.
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llvm-svn: 38501
2007-07-10 18:08:01 +00:00
881248c4e1
No need for ccop anymore.
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llvm-svn: 37965
2007-07-06 23:34:09 +00:00
aa3b8014bd
Each ARM use predicate operand is now made up of two components. The new component is the CPSR register.
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llvm-svn: 37895
2007-07-05 07:13:32 +00:00
e8c1e428f2
Revert the earlier change that removed the M_REMATERIALIZABLE machine
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instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).
llvm-svn: 37728
2007-06-26 00:48:07 +00:00
9e82064924
Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
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with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.
llvm-svn: 37644
2007-06-19 01:48:05 +00:00
a7ca624028
Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.
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llvm-svn: 37643
2007-06-19 01:26:51 +00:00
f62a5afb98
tBcc is not a barrier.
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llvm-svn: 37516
2007-06-08 09:13:23 +00:00
e8c3cbf971
Mark these instructions clobbersPred. They modify the condition code register.
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llvm-svn: 37468
2007-06-06 10:17:05 +00:00
1634e7186b
ARM::tB is also predicable.
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llvm-svn: 37125
2007-05-16 21:53:43 +00:00
0f7cbe8370
Add PredicateOperand to all ARM instructions that have the condition field.
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llvm-svn: 37066
2007-05-15 01:29:07 +00:00
9c031c0ddf
Switch BCC, MOVCCr, etc. to PredicateOperand.
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llvm-svn: 36948
2007-05-08 21:08:43 +00:00
fa34bc9623
Doh. PC displacement is between the constantpool and the add instruction.
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llvm-svn: 36630
2007-05-01 20:27:19 +00:00
c39c12a3fa
ARM TLS: implement "general dynamic", "initial exec" and "local exec" models.
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llvm-svn: 36506
2007-04-27 13:54:47 +00:00
e54018687d
Back out previous check-in. Incorrect.
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llvm-svn: 36503
2007-04-27 07:50:02 +00:00
68ec63b3d7
tLEApcrel is a AddrModeTs, i.e. pc relative.
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llvm-svn: 36502
2007-04-27 07:37:22 +00:00
6be85337b0
- Divides the comparisons in two types: comparisons that only use N and Z
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flags (ARMISD::CMPNZ) and comparisons that use all flags (ARMISD::CMP).
- Defines the instructions: TST, TEQ (ARM) and TST (Thumb).
llvm-svn: 35573
2007-04-02 01:30:03 +00:00
cc44b1e743
Can't re-materialize mov r, imm in thumb since mov would clobber the condition code.
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llvm-svn: 35479
2007-03-29 21:38:31 +00:00
143b0dff31
bugfix: sometimes the spiller puts a load between the "mov lr, pc" and "bx" of a CALL_NOLINK.
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llvm-svn: 35381
2007-03-27 16:19:21 +00:00
a88c4a74f3
bugfix: When the source register of CALL_NOLINK was LR, the following code was emitted:
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mov lr, pc
bx lr
So, the function was not called.
llvm-svn: 35218
2007-03-20 17:57:23 +00:00
9bb01c9f4f
Fix naming inconsistencies.
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llvm-svn: 35163
2007-03-19 07:48:02 +00:00
ee2763f76f
Special LDR instructions to load from non-pc-relative constantpools. These are
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rematerializable. Only used for constant generation for now.
llvm-svn: 35162
2007-03-19 07:20:03 +00:00
5be3e09a30
Constant generation instructions are re-materializable.
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llvm-svn: 35161
2007-03-19 07:09:02 +00:00
ec13f826a2
Spill / restore should avoid modifying the condition register.
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llvm-svn: 33971
2007-02-07 00:06:56 +00:00
06736d0f88
.set pc relative displacement bug: label should be moved down one instruction
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to just before the add r1, pc:
Before:
.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
mov r1, #PCRELV0
add r1, pc
Now:
.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
mov r1, #PCRELV0
LPCRELL0:
add r1, pc
llvm-svn: 33744
2007-02-01 03:04:49 +00:00
e7e966de5e
Special epilogue for vararg functions. We cannot do a pop to pc because
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there follows a sp increment for the va register save region. Instead issue
a separate pop to another register, increment sp, and then return:
pop {r4, r5, r6, r7}
pop {r3}
add sp, #3 * 4
bx r3
llvm-svn: 33739
2007-02-01 01:49:46 +00:00
0584836340
Thumb asm syntax does not want 's' suffix for flag setting opcodes.
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llvm-svn: 33717
2007-01-31 20:12:31 +00:00
83f35170fa
- Fix codegen for pc relative constant (e.g. JT) in thumb mode:
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.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
add r1, pc, #PCRELV0
This is not legal since add r1, pc, #c requires the constant be a multiple of 4.
Do the following instead:
.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
mov r1, #PCRELV0
add r1, pc
- In thumb mode, it's not possible to use .set generate a pc relative stub
address. The stub is ARM code which is in a different section from the thumb
code. Load the value from a constpool instead.
- Some asm printing clean up.
llvm-svn: 33664
2007-01-30 20:37:08 +00:00
1cd3c0efb8
Change the operand orders to t_addrmode_s* to make it easier to morph
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instructions that use these address modes to instructions that use
t_addrmode_sp.
llvm-svn: 33651
2007-01-30 02:35:32 +00:00
863736b0ad
Use BL to implement Thumb far jumps.
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llvm-svn: 33649
2007-01-30 01:13:37 +00:00
0701c5a074
Thumb jumptable support.
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llvm-svn: 33568
2007-01-27 02:29:45 +00:00
f40b9006a8
Thumb add / sub with carry.
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llvm-svn: 33562
2007-01-27 00:07:15 +00:00
add7f164a1
Represent tADDspi and tSUBspi as two-address instructions.
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llvm-svn: 33551
2007-01-26 21:33:19 +00:00
d02d75c295
extload -> zextload
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llvm-svn: 33542
2007-01-26 19:13:16 +00:00
1526ba50d9
Use PC relative ldr to load from a constantpool in Thumb mode.
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llvm-svn: 33484
2007-01-24 08:53:17 +00:00
c0b7366cf9
- Reorg Thumb load / store instructions. Combine each rr and ri pair of
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instructions into one (e.g. tLDRrr, tLDRri -> tLDR).
- Thumb ldrsb and ldrsh only have the [reg, reg] address format. If the
address is not an add, materialize a 0 immediate into a register and use
it as the offset field.
llvm-svn: 33470
2007-01-23 22:59:13 +00:00
10043e215b
ARM backend contribution from Apple.
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llvm-svn: 33353
2007-01-19 07:51:42 +00:00
Chris Lattner