Commit Graph

391 Commits

Author SHA1 Message Date
Chad Rosier 1ec8e404fc Mark the Int_eh_sjlj_dispatchsetup pseudo instruction as clobbering all
registers.  Previously, the register we being marked as implicitly defined, but
not killed.  In some cases this would cause the register scavenger to spill a
dead register.

Also, use an empty register mask to simplify the logic and to reduce the memory
footprint.
rdar://12592448

llvm-svn: 167499
2012-11-06 23:05:24 +00:00
Jim Grosbach 4739f2eb19 ARM: Better disassembly for pc-relative LDR.
When the operand is a plain immediate rather than a label, print it
as [pc, #imm] like we do for the Thumb2 wide encoding variant.

rdar://12154503

llvm-svn: 166991
2012-10-30 01:04:51 +00:00
Sylvestre Ledru 91ce36c986 Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767
llvm-svn: 164768
2012-09-27 10:14:43 +00:00
Sylvestre Ledru 721cffd53a Fix a typo 'iff' => 'if'
llvm-svn: 164767
2012-09-27 09:59:43 +00:00
Jakob Stoklund Olesen b3de7b1790 Revert r162713: "Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM."
This wasn't the right way to enforce ordering of atomics.

We are already setting the isVolatile bit on memory operands of atomic
operations which is good enough to enforce the correct ordering.

llvm-svn: 162732
2012-08-28 03:11:27 +00:00
Jakob Stoklund Olesen b24cb8c541 Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM.
It is not safe to use normal LDR instructions because they may be
reordered by the scheduler. The ATOMIC_LDR pseudos have a mayStore flag
that prevents reordering.

Atomic loads are also prevented from participating in rematerialization
and load folding.

llvm-svn: 162713
2012-08-27 23:58:52 +00:00
Jakob Stoklund Olesen 74352494a6 Missed tLEApcrelJT.
ARMConstantIslandPass expects this instruction to stay in the same basic
block as the jump table branch.

llvm-svn: 162615
2012-08-24 22:46:55 +00:00
Jakob Stoklund Olesen 6a81d30269 Remove variable_ops from ARM call instructions.
Function argument registers are added to the call SDNode, but
InstrEmitter now knows how to make those operands implicit, and the call
instruction doesn't have to be variadic.

Explicit register operands should only be those that are encoded in the
instruction, implicit register operands are for extra dependencies like
call argument and return values.

llvm-svn: 160188
2012-07-13 20:27:00 +00:00
Evan Cheng 68c2f9a9a7 (sub X, imm) gets canonicalized to (add X, -imm)
There are patterns to handle immediates when they fit in the immediate field.
e.g. %sub = add i32 %x, -123
=>   sub r0, r0, #123
Add patterns to catch immediates that do not fit but should be materialized
with a single movw instruction rather than movw + movt pair.
e.g. %sub = add i32 %x, -65535
=>   movw r1, #65535
     sub r0, r0, r1

rdar://11726136

llvm-svn: 159057
2012-06-23 00:29:06 +00:00
Benjamin Kramer bde9176663 Fix typos found by http://github.com/lyda/misspell-check
llvm-svn: 157885
2012-06-02 10:20:22 +00:00
Kevin Enderby 914223010c Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bits
for the assembler and disassembler.  Which were not being set/read correctly
for offsets greater than 22 bits in some cases.

Changes to lib/Target/ARM/ARMAsmBackend.cpp from Gideon Myles!

llvm-svn: 156118
2012-05-03 22:41:56 +00:00
Richard Barton 0fc56890ba Disallow YIELD and other allocated nop hints in pre-ARMv6 architectures.
llvm-svn: 155983
2012-05-02 09:43:18 +00:00
Jim Grosbach c6f32b3295 ARM: Thumb add(sp plus register) asm constraints.
Make sure when parsing the Thumb1 sp+register ADD instruction that
the source and destination operands match. In thumb2, just use the
wide encoding if they don't. In Thumb1, issue a diagnostic.

rdar://11219154

llvm-svn: 155748
2012-04-27 23:51:36 +00:00
Jim Grosbach 9d8f6f3d9d ARM: Tweak tADDrSP definition for consistent operand order.
Make the operand order of the instruction match that of the asm syntax.

llvm-svn: 155747
2012-04-27 23:51:33 +00:00
Jim Grosbach ad66de155b ARM add missing Thumb1 two-operand aliases for shift-by-immediate.
rdar://11222742

llvm-svn: 154457
2012-04-11 00:15:16 +00:00
Jakob Stoklund Olesen b4bd3880ba Eliminate iOS-specific tail call instructions.
After register masks were introdruced to represent the call clobbers, it
is no longer necessary to have duplicate instruction for iOS.

llvm-svn: 154209
2012-04-06 21:17:42 +00:00
Jakob Stoklund Olesen 6a2e99a46a Deduplicate ARM call-related instructions.
We had special instructions for iOS because r9 is call-clobbered, but
that is represented dynamically by the register mask operands now, so
there is no need for the pseudo-instructions.

llvm-svn: 154144
2012-04-06 00:04:58 +00:00
Jim Grosbach 930f2f66e7 ARM assembly aliases for add negative immediates using sub.
'add r2, #-1024' should just use 'sub r2, #1024' rather than erroring out.
Thumb1 aliases for adding a negative immediate to the stack pointer,
also.

rdar://11192734

llvm-svn: 154123
2012-04-05 20:57:13 +00:00
Jakob Stoklund Olesen fa7a53746c Switch ARM target to register masks.
I'll let the buildbots determine the compile time improvements from this
change, but 464.h264ref has 5% faster codegen at -O2.

This patch does cause some assembly changes.  Branch folding can make
different decisions about calls with dead return values.
CriticalAntiDepBreaker may choose different registers because its
liveness tracking is affected.  MachineCopyPropagation may sometimes
leave a dead copy behind.

llvm-svn: 151331
2012-02-24 01:19:29 +00:00
Jia Liu b22310fda6 Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
llvm-svn: 150878
2012-02-18 12:03:15 +00:00
James Molloy d9ba4fd48f Teach the MC and disassembler about SoftFail, and hook it up to UNPREDICTABLE on ARM. Wire this to tBLX in order to provide test coverage.
llvm-svn: 150169
2012-02-09 10:56:31 +00:00
Jim Grosbach 9ab3d8be4e Rename pattern for clarity.
llvm-svn: 148422
2012-01-18 21:54:09 +00:00
Jakob Stoklund Olesen 35545421c8 Use RegisterTuples to generate pseudo-registers.
The QQ and QQQQ registers are not 'real', they are pseudo-registers used
to model some vld and vst instructions.

This makes the call clobber lists longer, but I intend to get rid of
those soon.

llvm-svn: 148151
2012-01-13 22:55:42 +00:00
Bob Wilson 1a74de9504 Add variants of the dispatchsetup pseudo for Thumb and !VFP. <rdar://10620138>
My change r146949 added register clobbers to the eh_sjlj_dispatchsetup pseudo
instruction, but on Thumb1 some of those registers cannot be used.  This
caused massive failures on the testsuite when compiling for Thumb1.  While
fixing that, I noticed that the eh_sjlj_setjmp instruction has a "nofp"
variant, and I realized that dispatchsetup needs the same thing, so I have
added that as well.

llvm-svn: 147204
2011-12-22 23:39:48 +00:00
Evan Cheng 68132d8093 ARM target code clean up. Check for iOS, not Darwin where it makes sense.
llvm-svn: 146981
2011-12-20 18:26:50 +00:00
Jim Grosbach 561e4e18cf ARM pre-UAL NEG mnemonic for convenience when porting old code.
llvm-svn: 146511
2011-12-13 20:23:22 +00:00
Bill Wendling aa9047d3f5 Now Igor, throw the switch...give my creation life!
Use the custom inserter for the ARM setjmp intrinsics. Instead of creating the
SjLj dispatch table in IR, where it frequently violates serveral assumptions --
in particular assumptions made by the landingpad instruction about what can
branch to a landing pad and what cannot. Performing this in the back-end allows
us to violate these assumptions without the IR getting angry at us.

It also allows us to perform a small optimization. We can shove the address of
the dispatch's basic block into the function context and not have to add code
around the setjmp to check for the return value and jump to the dispatch.

Neat, huh?
<rdar://problem/10116753>

llvm-svn: 142294
2011-10-17 22:26:23 +00:00
Jakob Stoklund Olesen dd2b39d989 Mark tADDrSPi as having side effects again.
It really doesn't, but when r141929 removed the hasSideEffects flag from
this instruction, it caused miscompilations.  I am guessing that it got
moved across a stack pointer update.

Also clear isRematerializable after checking that this instruction is
in fact never rematerialized in the nightly test suite.

llvm-svn: 142030
2011-10-15 00:57:13 +00:00
Jakob Stoklund Olesen d9444d455e Ban rematerializable instructions with side effects.
TableGen infers unmodeled side effects on instructions without a
pattern.  Fix some instruction definitions where that was overlooked.

Also raise an error if a rematerializable instruction has unmodeled side
effects. That doen't make any sense.

llvm-svn: 141929
2011-10-14 01:00:49 +00:00
Jim Grosbach 08a478063c Thumb1 convenience aliases for disassembler round-trip testing. CPS instruction.
llvm-svn: 140108
2011-09-20 00:10:37 +00:00
Jim Grosbach 4da03f007f Thumb CPS definition is not disassembler only.
llvm-svn: 140106
2011-09-20 00:00:06 +00:00
Jim Grosbach d0c435c23c Thumb2 assembly parsing and encoding for SUB(immediate).
llvm-svn: 139966
2011-09-16 22:58:42 +00:00
Eli Friedman ba912e06c2 Use a more efficient lowering for Unordered/Monotonic atomic load/store on Thumb1.
llvm-svn: 139865
2011-09-15 22:18:49 +00:00
Owen Anderson 29cfe6c368 Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.
llvm-svn: 139415
2011-09-09 21:48:23 +00:00
Jim Grosbach 4b701af908 Thumb parsing and encoding for SUB (SP minu immediate).
Fix FiXME in test file. Remove FIXME for SUB (SP minus register) since that
form is Thumb2 only.

llvm-svn: 138494
2011-08-24 21:42:27 +00:00
Jim Grosbach 0a0b3071df Thumb parsing and encoding support for ADD SP instructions.
Fix the test FIXME and add parsing support for the ADD (SP plus immediate)
and ADD (SP plus register) instruction forms.

llvm-svn: 138488
2011-08-24 21:22:15 +00:00
Jim Grosbach 6ccd79f4d5 Add missing explicit writeback operand to tSTMIA_UPD.
rdar://10014745

llvm-svn: 138457
2011-08-24 18:19:42 +00:00
Jim Grosbach a281f2d07d Thumb add SP assembly syntax fix.
llvm-svn: 138448
2011-08-24 18:04:27 +00:00
Jim Grosbach 1b8457a84c Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.
Add the predicate operand to the instructions. Update the back end
accordingly where the instructions are used. Restrict the SP operands
to actually only be SP, as otherwise these break assembly parsing for the
normal instruction variants.

llvm-svn: 138445
2011-08-24 17:46:13 +00:00
Jim Grosbach 5cc338da67 Thumb parsing and encoding for SVC.
llvm-svn: 138360
2011-08-23 19:49:10 +00:00
Jim Grosbach 505be75900 Thumb parsing and encoding for tSTRspi.
llvm-svn: 138348
2011-08-23 18:39:41 +00:00
Jim Grosbach e364ad540a Clean up Thumb load/store multiple definitions.
There is no non-writeback store multiple instruction in Thumb1, so
don't define one. As a result load multiple is the only instantiation of
the multiclass, so refactor that away entirely.

llvm-svn: 138338
2011-08-23 17:41:15 +00:00
Jim Grosbach bfeb4f78af Revert r138278 now that r138289 has fixed the root issue.
llvm-svn: 138299
2011-08-22 23:25:48 +00:00
Jim Grosbach ca2ffad8b1 Temporarilly mark tMUL as not commutable.
It's not playing nicely in the coalescer with the tied operand. Disable
commutability for now while we figure out the deeper fix.

llvm-svn: 138278
2011-08-22 22:00:18 +00:00
Jim Grosbach 6caa557ae6 Clean up predicates on ARM target instruction aliases.
llvm-svn: 138249
2011-08-22 18:04:24 +00:00
Jim Grosbach 2597722e07 Thumb parsing and encoding support for NOP.
The irony is not lost that this is not a completely trivial patchset.

llvm-svn: 138143
2011-08-19 23:24:36 +00:00
Jim Grosbach 8022015a16 Fix NEG alias
llvm-svn: 138125
2011-08-19 22:30:58 +00:00
Jim Grosbach 066e9ec1e4 Update tests.
llvm-svn: 138116
2011-08-19 22:19:48 +00:00
Jim Grosbach 8e048495c8 Thumb assembly parsing and encoding for MUL.
llvm-svn: 138108
2011-08-19 22:07:46 +00:00
Jim Grosbach f86cd37bef Thumb assembly parsing and encoding for MOV.
llvm-svn: 138076
2011-08-19 20:46:54 +00:00