795ed98180
Compute critical loop predecessors in the same way as critical loop exits.
...
Critical edges going into a loop are not as bad as critical exits. We can handle
them by splitting the critical edge, or by having both inside and outside
registers live out of the predecessor.
llvm-svn: 117423
2010-10-27 00:39:05 +00:00
0e7a011a00
Physical registers trivially have multiple connected components all the time.
...
Only virtuals should be requires to be connected.
llvm-svn: 117422
2010-10-27 00:39:01 +00:00
2577b2e8b1
One more spot where the new arm mode LDR instruction representation
...
doesn't need the additional addrmode2 register operand. Missed it the first
time around.
llvm-svn: 117421
2010-10-27 00:38:16 +00:00
e9b429e96f
Adding disassembler to the MicroBlaze backend.
...
llvm-svn: 117420
2010-10-27 00:23:01 +00:00
5a7c715470
Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on
...
rdar://8477752.
llvm-svn: 117419
2010-10-27 00:19:44 +00:00
a92801b695
Since I parameterized this bit, I should probably actually use said parameter.
...
llvm-svn: 117418
2010-10-26 23:58:04 +00:00
e660f4d072
Use a MemIntrinsicSDNode for ISD::PREFETCH, which touches
...
memory, so a MachineMemOperand is useful (not propagated
into the MachineInstr yet). No functional change except
for dump output.
llvm-svn: 117413
2010-10-26 23:11:10 +00:00
5f88cc34e1
Remove the vector of live vregs. I thought we would need to track
...
them, but hopefully we won't. And this is not the right data structure
to do it anyway.
llvm-svn: 117412
2010-10-26 22:58:24 +00:00
825b2d1946
Add correct NEON encodings for vqshl, vqshrn, vqshrun, vqrshl, vqshrn, and vqrshrun.
...
llvm-svn: 117411
2010-10-26 22:50:46 +00:00
1e4d9a17c2
First part of refactoring ARM addrmode2 (load/store) instructions to be more
...
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.
llvm-svn: 117409
2010-10-26 22:37:02 +00:00
e4f3317cda
After splitting, compute connected components of all new registers, not just for
...
the remainder register.
Example:
bb0:
x = 1
bb1:
use(x)
...
x = 2
jump bb1
When x is isolated in bb1, the inner part breaks into two components, x1 and x2:
bb0:
x0 = 1
bb1:
x1 = x0
use(x1)
...
x2 = 2
x0 = x2
jump bb1
llvm-svn: 117408
2010-10-26 22:36:09 +00:00
260fa289df
Verify that live intervals are connected. If there are multiple connected
...
components, each should get its own virtual register.
llvm-svn: 117407
2010-10-26 22:36:07 +00:00
022e7795cf
Call RenumberValues for all new registers created during splitting. This is
...
necessary to get correct hasPHIKill flags.
llvm-svn: 117406
2010-10-26 22:36:05 +00:00
4453324e5b
Preserve PHIDef bits in cloned values during splitting.
...
llvm-svn: 117405
2010-10-26 22:36:02 +00:00
05561e8b7b
Assign source ordering to nodes created for StoreInst.
...
llvm-svn: 117404
2010-10-26 22:14:52 +00:00
2888e2c7f9
Correct NEON encodings for vshrn, vrshl, vrshr, vrshrn.
...
llvm-svn: 117402
2010-10-26 21:58:41 +00:00
e18579976f
Simplify classes for shift instructions, which are never commutable.
...
llvm-svn: 117398
2010-10-26 21:13:59 +00:00
3665fee8de
Provide correct NEON encodings for vshl, register and immediate forms.
...
llvm-svn: 117394
2010-10-26 20:56:57 +00:00
b7050233fb
Teach MachineBasicBlock::print() to annotate instructions and blocks with
...
SlotIndexes when available.
llvm-svn: 117392
2010-10-26 20:21:46 +00:00
db594373bd
Remmeber to print full live interval on verification error.
...
llvm-svn: 117391
2010-10-26 20:21:43 +00:00
c9fb35e73b
Add support for .ident.
...
llvm-svn: 117389
2010-10-26 19:35:47 +00:00
9302bfdd5a
Grammar.
...
llvm-svn: 117388
2010-10-26 19:34:41 +00:00
79b3bf4d81
Nuke extraneous comment. It's applicable elsewhere, but not in this func.
...
llvm-svn: 117387
2010-10-26 19:22:23 +00:00
84aef49e32
Jakob's review of the basic register allocator.
...
llvm-svn: 117384
2010-10-26 18:34:01 +00:00
691ce68d3c
Add correct NEON encoding for vpadal.
...
llvm-svn: 117380
2010-10-26 18:18:03 +00:00
d94f3b4ae9
handle X86::EH_RETURN64 and X86::EH_RETURN.
...
llvm-svn: 117378
2010-10-26 18:09:55 +00:00
b5694e702c
s/beginScope/beginInstruction/g
...
s/endScope/endInstruction/g
llvm-svn: 117376
2010-10-26 17:49:02 +00:00
284cb361d1
Add NEON encodings for vmov and vmvn of immediates.
...
llvm-svn: 117374
2010-10-26 17:40:54 +00:00
9eabfa3a39
Don't verify physical registers going into landing pads.
...
Magic is happening that we don't understand.
llvm-svn: 117370
2010-10-26 16:49:23 +00:00
e8ae98817a
Implement some relaxations for arithmetic instructions. The limitation
...
on RIP relative relocations looks artificial, but this is a superset of
what we were able to do before.
llvm-svn: 117364
2010-10-26 14:09:12 +00:00
a49d062234
Change v64 datalayout in SPU.
...
The SPU ABI does not mention v64, and all examples
in C suggest v128 are treated similarily to arrays,
we use array alignment for v64 too. This makes the
alignment of e.g. [2 x <2 x i32>] behave "intuitively"
and similar to as if the elements were e.g. i32s.
This also makes an "unaligned store" test to be
aligned, with different (but functionally equivalent)
code generated.
llvm-svn: 117360
2010-10-26 10:45:47 +00:00
e96b8d7ab6
Use instruction itinerary to determine what instructions are 'cheap'.
...
llvm-svn: 117348
2010-10-26 02:08:50 +00:00
b45591979b
NEON vmov's are in Neon domain.
...
llvm-svn: 117347
2010-10-26 02:03:05 +00:00
90b2ac2696
For statistics that are only used in functions declared in !NDEBUG, wrap the
...
declarations in !NDEBUG to avoid -Wunused-variable warnings. Patch by
Matt Beaumont-Gay!
llvm-svn: 117345
2010-10-26 00:51:57 +00:00
e2c340c8d0
InlineSpiller can also update LiveStacks.
...
llvm-svn: 117338
2010-10-26 00:11:35 +00:00
7cdc1e5f16
Make the spiller responsible for updating the LiveStacks analysis.
...
llvm-svn: 117337
2010-10-26 00:11:33 +00:00
e1961fe289
When the "true" and "false" blocks of a diamond if-conversion are the same,
...
do not double-count the duplicate instructions by counting once from the
beginning and again from the end. Keep track of where the duplicates from
the beginning ended and don't go past that point when counting duplicates
at the end. Radar 8589805.
This change causes one of the MC/ARM/simple-fp-encoding tests to produce
different (better!) code without the vmovne instruction being tested.
I changed the test to produce vmovne and vmoveq instructions but moving
between register files in the opposite direction. That's not quite the same
but predicated versions of those instructions weren't being tested before,
so at least the test coverage is not any worse, just different.
llvm-svn: 117333
2010-10-26 00:02:24 +00:00
efd360c535
Change if-conversion to keep track of the extra cost due to microcoded
...
instructions separately from the count of non-predicated instructions. The
instruction count is used in places to determine how many instructions to
copy, predicate, etc. and things get confused if that count includes the
extra cost for microcoded ops.
llvm-svn: 117332
2010-10-26 00:02:21 +00:00
59f7cdaf98
Tidy up redundant check.
...
llvm-svn: 117331
2010-10-26 00:02:19 +00:00
43d6f34e9f
Neuter r117193 as it causes significant post-ra scheduler compile time regression.
...
llvm-svn: 117329
2010-10-25 23:56:21 +00:00
d9d0c348df
Produce the headers directly in the Finish method. This allows us to use
...
the existing streamer methods that are endian safe.
llvm-svn: 117323
2010-10-25 22:26:55 +00:00
ec57ac1c3c
An stdcall function calling a non-stdcall function
...
cannot use tailcall. PR 8461.
llvm-svn: 117322
2010-10-25 22:17:05 +00:00
c6096263e2
Support TBAA attachments on calls. This is somewhat experimental.
...
llvm-svn: 117317
2010-10-25 21:38:20 +00:00
43c3f4b63c
Simplify.
...
Do not count use of sdisel for single call instruction.
llvm-svn: 117316
2010-10-25 21:31:46 +00:00
1f6aad053d
Add correct encodings for NEON vabal.
...
llvm-svn: 117315
2010-10-25 21:29:04 +00:00
82b2e0da9c
Fix chaining in TBAA's pointsToConstantMemory.
...
llvm-svn: 117314
2010-10-25 21:24:55 +00:00
3bc6d198fb
Add counters to count basic blocks and machine basic blocks with out of order line number info.
...
Add counters to count how many basic blocks are entirely selected by fastisel.
llvm-svn: 117310
2010-10-25 20:55:43 +00:00
b9c91679aa
Add correct NEON encodings for vaba.
...
llvm-svn: 117309
2010-10-25 20:52:57 +00:00
a86114b961
Add simple counter to count no. of basic blocks without any line number information. At -O0, these basic block coule cause less than optimial debugging experience.
...
llvm-svn: 117307
2010-10-25 20:45:32 +00:00
e6715d0755
Only read one bit for testing for a readonly type, leaving the other
...
bits open for future uses.
llvm-svn: 117301
2010-10-25 20:22:29 +00:00
b3a48f3459
MC/AsmParser: Fix relative precedence of {+,-} and comparison ops.
...
llvm-svn: 117299
2010-10-25 20:18:56 +00:00
7484d2cbec
MC/AsmLexer: Fix bug in source location for Slash token.
...
llvm-svn: 117298
2010-10-25 20:18:53 +00:00
dd001b89d7
Attempt to provide correct encodings for NEON vbit and vbif, even though we can't test them at the moment.
...
llvm-svn: 117294
2010-10-25 20:17:22 +00:00
dea09c7564
Provide correct NEON encodings for vbsl.
...
llvm-svn: 117293
2010-10-25 20:13:13 +00:00
e6fe1a03c7
imm12 operands aren't Thumb2 only, so rename the printer helper function.
...
llvm-svn: 117291
2010-10-25 20:00:01 +00:00
fd864a1d31
Add a comment.
...
llvm-svn: 117288
2010-10-25 19:47:25 +00:00
2477446ee5
Add correct instruction encodings for vbic, vorn, and vmvn.
...
llvm-svn: 117282
2010-10-25 18:43:52 +00:00
752913d6ba
Add a virtual destructor.
...
llvm-svn: 117280
2010-10-25 18:38:32 +00:00
dff239c5f9
Provide correct NEON encodings for vand, veor, and vorr.
...
llvm-svn: 117279
2010-10-25 18:28:30 +00:00
feb3ee0c93
Add NEON encoding tests for vcgt and vacgt.
...
llvm-svn: 117276
2010-10-25 18:03:59 +00:00
0ed1543d4e
Add support for emitting ARM file attributes.
...
llvm-svn: 117275
2010-10-25 17:50:35 +00:00
e5d0677173
Add tests for NEON encodings of vcge and vacge.
...
llvm-svn: 117274
2010-10-25 17:49:32 +00:00
c178b80f65
Add a warning about our inability to test the encoding of vceq with immediate zero.
...
llvm-svn: 117273
2010-10-25 17:33:02 +00:00
912db6d9d0
In which I learn how to forward declare template classes.
...
llvm-svn: 117272
2010-10-25 17:27:30 +00:00
abaf2d8d3b
Update comments; BasicAA is no longer necessarily the end of the chain.
...
llvm-svn: 117268
2010-10-25 16:29:52 +00:00
1033ce669b
Reintroduce these asserts, now that BasicAA is a normal AliasAnalysis pass.
...
llvm-svn: 117266
2010-10-25 16:28:57 +00:00
2e20dfb0f2
Fix a case where instcombine was stripping metadata (and alignment)
...
from stores when folding in bitcasts.
llvm-svn: 117265
2010-10-25 16:16:27 +00:00
22fe18625d
Add a new 'hotpatch' attribute. This attribute will insert a two-byte no-op
...
instruction at the beginning of each function that has the attribute, allowing
the function to be easily hooked and/or patched.
llvm-svn: 117264
2010-10-25 15:37:09 +00:00
08745f5483
ATTRIBUTE_UNUSED has been renamed to LLVM_ATTRIBUTE_UNUSED.
...
Rather than rename this instance, use the cast-to-void idiom
instead. This will hopefully fix the windows buildbots.
llvm-svn: 117262
2010-10-25 13:10:03 +00:00
800fd3533c
Add X86::reloc_global_offset_table and use it to have a single place where
...
we check for _GLOBAL_OFFSET_TABLE_.
llvm-svn: 117241
2010-10-24 17:35:42 +00:00
31c803b2ba
Fix PR8445: a block with no predecessors may be the entry block, in which case
...
it isn't unreachable and should not be zapped. The check for the entry block
was missing in one case: a block containing a unwind instruction. While there,
do some small cleanups: "M" is not a great name for a Function* (it would be
more appropriate for a Module*), change it to "Fn"; use Fn in more places.
llvm-svn: 117224
2010-10-24 12:23:30 +00:00
76229bc128
SmallVectorize.
...
llvm-svn: 117213
2010-10-23 17:10:24 +00:00
c9616f26bd
Move rejection of NEON parameters earlier in fast isel call processing,
...
note that we can actually handle some f64 arguments.
llvm-svn: 117209
2010-10-23 09:37:17 +00:00
de0a4fbf3b
Make the disassembler tables const so they end up in read-only memory.
...
llvm-svn: 117206
2010-10-23 09:10:44 +00:00
aa19ee17c0
X86: Emit _fltused instead of __fltused on Windows x64.
...
llvm-svn: 117205
2010-10-23 09:06:59 +00:00
82058c05f8
Move the remaining attribute macros to systematic names based on the attribute
...
name and prefixed with 'LLVM_'.
llvm-svn: 117203
2010-10-23 08:40:19 +00:00
9873c9039e
Remove a define which is never referenced.
...
llvm-svn: 117202
2010-10-23 08:25:16 +00:00
88c54b82c1
Switch attribute macros to use 'LLVM_' as a prefix. We retain the old names
...
until other LLVM projects using these are cleaned up.
llvm-svn: 117200
2010-10-23 08:10:43 +00:00
9733158bfd
Fix a likely bug in an assertion by adding parentheses around '||'. This bug
...
was found by a GCC warning. ;]
llvm-svn: 117199
2010-10-23 07:46:14 +00:00
817bbac4f7
Enable ARM fastcc.
...
llvm-svn: 117194
2010-10-23 02:19:37 +00:00
15459b695f
Properly model the latency of register defs which are 1) function returns or
...
2) live-outs.
Previously the post-RA schedulers completely ignore these dependencies since
returns, branches, etc. are all scheduling barriers. This patch model the
latencies between instructions being scheduled and the barriers. It also
handle calls by marking their register uses.
llvm-svn: 117193
2010-10-23 02:10:46 +00:00
ad79526471
Latency between CPSR def and branch is zero.
...
llvm-svn: 117192
2010-10-23 02:04:38 +00:00
8a09620dc2
Verify LiveIntervals against the CFG, ensuring that live-in values are live-out
...
of all predecessors.
llvm-svn: 117191
2010-10-23 00:49:09 +00:00
696fe9d36c
Trailing whitespace.
...
llvm-svn: 117188
2010-10-22 23:48:29 +00:00
e8719c51aa
Nonvirtual dtor that was accessible enough to be bad.
...
llvm-svn: 117180
2010-10-22 23:33:19 +00:00
b171ca0a47
fix memory-layout assumption which only holds on little-endian systems
...
llvm-svn: 117176
2010-10-22 23:16:11 +00:00
1c24605a57
This is a prototype of an experimental register allocation
...
framework. It's purpose is not to improve register allocation per se,
but to make it easier to develop powerful live range splitting. I call
it the basic allocator because it is as simple as a global allocator
can be but provides the building blocks for sophisticated register
allocation with live range splitting.
A minimal implementation is provided that trivially spills whenever it
runs out of registers. I'm checking in now to get high-level design
and style feedback. I've only done minimal testing. The next step is
implementing a "greedy" allocation algorithm that does some register
reassignment and makes better splitting decisions.
llvm-svn: 117174
2010-10-22 23:09:15 +00:00
0fb303d3c0
Add more verification of LiveIntervals.
...
llvm-svn: 117170
2010-10-22 22:48:58 +00:00
4cf8fe31bb
Be more strict about detecting multi-use blocks for isolation.
...
When a block has exactly two uses and the register is both live-in and live-out,
don't isolate the block. We would be inserting two copies, so we haven't really
made any progress.
If the live-in and live-out values separate into disconnected components after
splitting, we would be making progress. We can't detect that for now.
llvm-svn: 117169
2010-10-22 22:48:56 +00:00
2c9ae05c67
ARM mode encoding information for CLZ, RBIT, REV*, and PKH*.
...
llvm-svn: 117165
2010-10-22 22:12:16 +00:00
21eedfb5a2
Unbreak build.
...
llvm-svn: 117155
2010-10-22 21:49:09 +00:00
a4e231c880
Teach instcombine to set the alignment arguments for NEON load/store intrinsics.
...
llvm-svn: 117154
2010-10-22 21:41:48 +00:00
77a38320c7
Transfer implicit ops when forming load multiple and return instructions.
...
llvm-svn: 117151
2010-10-22 21:29:58 +00:00
2d60075590
Be more strict when detecting critical edges before loop splitting.
...
An exit block with a critical edge must only have predecessors in the loop, or
just before the loop. This guarantees that the inserted copies in the loop
predecessors dominate the exit block.
llvm-svn: 117144
2010-10-22 20:28:23 +00:00
9a74301621
Add print methods
...
llvm-svn: 117143
2010-10-22 20:28:21 +00:00
9d0122af7d
Add correct NEON encodings for vqdmlal.
...
llvm-svn: 117134
2010-10-22 19:35:48 +00:00
2b80543fc2
Add the encoding information for the rest of the ARM mode multiply instructions.
...
llvm-svn: 117133
2010-10-22 19:15:30 +00:00
3d0264667f
Provide correct encodings for NEON vmlal.
...
llvm-svn: 117131
2010-10-22 19:05:25 +00:00
21abfc9450
Silence compiler warnings.
...
llvm-svn: 117128
2010-10-22 18:57:05 +00:00
f48719f1b5
Provide correct NEON encodings for vmla.
...
llvm-svn: 117126
2010-10-22 18:54:37 +00:00
6956a60563
More ARM multiply instuction binary encodings.
...
llvm-svn: 117121
2010-10-22 18:35:16 +00:00
08dd8c8295
Add fastcc cc: pass and return VFP / NEON values in registers. Controlled by -arm-fastcc for now.
...
llvm-svn: 117119
2010-10-22 18:23:05 +00:00
f98df0849f
Parameterize a bit of ARM encoding information, simplifying some instruction
...
definitions.
llvm-svn: 117114
2010-10-22 17:42:06 +00:00
9192e7ab12
Make some symbols static, move classes into anonymous namespaces.
...
llvm-svn: 117111
2010-10-22 17:35:07 +00:00
22261600a8
More ARM multiply instruction encoding information.
...
llvm-svn: 117108
2010-10-22 17:16:17 +00:00
1851090515
Making the e_machine configurable by the target backend in ELFObjectWriter.
...
llvm-svn: 117099
2010-10-22 15:52:49 +00:00
edd006c1c3
Reverting r117031 to cleanup valgrind errors.
...
It doesn't look like anything is wrong with the checkin,
but the new test cases expose a mem bug in AsmParser.
llvm-svn: 117087
2010-10-22 03:58:29 +00:00
93bbe6599f
Add some basic ret instruction support to arm fast-isel.
...
llvm-svn: 117085
2010-10-22 01:28:00 +00:00
9f6c622f88
Fixed handling of immediate operand sizes, which
...
weren't properly reflecting the OperandSize attribute
of the instruction leading to improper decoding of
certain instructions with the 66H prefix. Also added
a test case for this.
llvm-svn: 117084
2010-10-22 01:24:11 +00:00
3f688b92a9
Win32/Signals.inc: DontRemoveFileOnSignal(): Please acquire the CriticalSection.
...
It choked BugPoint on Mingw.
llvm-svn: 117083
2010-10-22 01:23:50 +00:00
e2ec62e252
ARM binary encoding for some of the multiply instructions.
...
llvm-svn: 117080
2010-10-21 22:52:30 +00:00
a97becfaac
ARM binary encodings for MVN variants.
...
llvm-svn: 117076
2010-10-21 22:19:32 +00:00
90600d3329
Trailing whitespace.
...
llvm-svn: 117073
2010-10-21 22:04:05 +00:00
5edb03ee57
ARM Binary encoding information for BFC/BFI instructions.
...
llvm-svn: 117072
2010-10-21 22:03:21 +00:00
8512270dbc
Add some more documentation.
...
llvm-svn: 117070
2010-10-21 21:55:35 +00:00
2f8637d393
These don't need to be virtual.
...
llvm-svn: 117068
2010-10-21 21:47:51 +00:00
31041a9967
Fix Warnings.
...
llvm-svn: 117062
2010-10-21 20:49:38 +00:00
0e36e0340a
X86: Base _fltused on the FunctionType of the called value instead of the potentially null "CalledFunction". Thanks Duncan!
...
This is needed for indirect calls.
llvm-svn: 117061
2010-10-21 20:49:23 +00:00
2bfa8ed045
Move the encoding logic for Q registers into getMachineOpValue().
...
llvm-svn: 117060
2010-10-21 20:49:13 +00:00
f64d93df79
Trailing whitespace.
...
llvm-svn: 117058
2010-10-21 20:40:39 +00:00
9e44cf2bb2
ARM encodes Q registers as 2xregno (i.e. the number of the D register that corresponds to the lower
...
half of the Q register), rather than with just regno. This allows us to unify the encodings for
a lot of different NEON instrucitons that differ only in whether they have Q or D register operands.
llvm-svn: 117056
2010-10-21 20:21:49 +00:00
b353e4f579
Handle storing args to the stack for calls.
...
llvm-svn: 117055
2010-10-21 20:09:54 +00:00
a7f6150c14
Adding initial AsmParser implementation for the MBlaze backend. It is
...
mostly based on the ARM AsmParser at this time and is not particularly
functional.
Changed the MBlaze data layout from:
"E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32"
to:
"E-p:32:32:32-i8:8:8-i16:16:16"
because the MicroBlaze doesn't have i64, f64, v64, or v128 data types.
Cleaned up the MBlaze source code:
1. The floating point register class has been removed. The
MicroBlaze does not have floating point registers. Floating
point values are simply stored in integer registers.
2. Renaming the CPURegs register class to GPR to reflect the
standard naming.
3. Removing a lot of stale code from AsmPrinter after
the conversion to InstPrinter.
4. Simplified sign extended loads by marking them as
expanded in ISelLowering.
llvm-svn: 117054
2010-10-21 19:48:38 +00:00
12c9e0cf1c
Explain what "constant" means here.
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llvm-svn: 117053
2010-10-21 19:45:09 +00:00
73bc5b0f86
More load/store refactoring, call reg+offset simplification from within
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the emitter to handle the addresses. Only simplify the offset if we need
to - also fix bug where in addrmode 5 we weren't dividing the offset by
4, which showed up due to not always lowering.
llvm-svn: 117051
2010-10-21 19:40:30 +00:00
d37f0715b1
trailing whitespace
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llvm-svn: 117050
2010-10-21 19:38:40 +00:00
104f1812ce
Update comments.
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llvm-svn: 117048
2010-10-21 19:01:22 +00:00
6b7e401049
Add correct NEON encodings for vhadd and vrhadd.
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llvm-svn: 117047
2010-10-21 18:55:04 +00:00
f4bbe50fc3
Don't include the destination interval in the union when computing
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Parent - union(Y, ...). Doh.
llvm-svn: 117042
2010-10-21 18:47:08 +00:00
7c9d584ebc
Permit landing pad successor blocks when verifying basic blocks that end in an
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unconditional branch.
llvm-svn: 117041
2010-10-21 18:47:06 +00:00
9561084188
Add correct encodings for NEON vaddw.s* and vaddw.u*.
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llvm-svn: 117040
2010-10-21 18:20:25 +00:00
15c97706e8
Provide correct NEON encodings for vaddl.u* and vaddl.s*.
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llvm-svn: 117039
2010-10-21 18:09:17 +00:00
8ba86f801d
Do not recurse into symbol refs that have a variant kind. This prevents us
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from losing the variant when producing a relocation on an alias.
llvm-svn: 117037
2010-10-21 18:00:20 +00:00
0138a05557
More tweaks to X86 instructions to allow the 'w' suffix in places it makes
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sense, when the instruction takes the 16-bit ax register or m16 memory
location. These changes to llvm-mc matches what the darwin assembler allows
for these instructions. Also added the missing flex (without the wait prefix)
and ud2a as an alias to ud2 (still to add ud2b).
llvm-svn: 117031
2010-10-21 17:16:46 +00:00
4c5c858d78
AlignLoc is never used for anything - zap it (gcc-4.6 warning).
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llvm-svn: 117025
2010-10-21 16:07:10 +00:00
b014abf3ef
The return value of this call is not used, so no point
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in assigning it to a variable (gcc-4.6 warning).
llvm-svn: 117024
2010-10-21 16:06:28 +00:00
94da154558
RetOp is not actually used for anything useful (though
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it looks like maybe it was supposed to be used in the
test...), so zap it (gcc-4.6 warning).
llvm-svn: 117023
2010-10-21 16:05:44 +00:00
2f16b91ce0
The variable liTRC is not used for anything useful, zap it
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(gcc-4.6 warning).
llvm-svn: 117022
2010-10-21 16:04:43 +00:00
ee4eb2bad1
Remove some variables that are never really used
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(gcc-4.6 warns about these).
llvm-svn: 117021
2010-10-21 16:03:28 +00:00
1f0d37e892
Add parentheses to pacify gcc, which warns otherwise.
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llvm-svn: 117020
2010-10-21 16:02:12 +00:00
abc7901e4e
Fix the cleanup process of exception information in JIT. Now JIT
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deregisters registered by it FDE structures allowing consecutive
JIT runs to succeed. Patch by Yuri. Fixes PR8285.
llvm-svn: 117004
2010-10-21 08:57:29 +00:00
f7ecd9e8bb
Removing stale AsmPrinter directory from MicroBlaze backend.
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llvm-svn: 116998
2010-10-21 05:05:06 +00:00
3e79a47a7a
Deleted lib/Target/MBlaze/AsmPrinter/CMakeLists.txt. This way the
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CMake build does not try to build that library, which collides with
MBlaze/InstPrinter.
llvm-svn: 116997
2010-10-21 05:01:26 +00:00
c16f77fb27
Recommit 116986 with capitalization typo fixed.
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llvm-svn: 116993
2010-10-21 03:57:26 +00:00
f4ebec03e0
putback r116983 and fix simple-fp-encoding.ll tests
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llvm-svn: 116992
2010-10-21 03:40:16 +00:00
078db00f1d
Reverting the commit 116986. It was breaking the build on llvm-x86_64-linux though it
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compiles on OS X. I'll ensure that it builds on a linux machine before committing
again.
llvm-svn: 116991
2010-10-21 03:34:22 +00:00
9e00f27e14
Revert r116983, which is breaking all the buildbots.
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llvm-svn: 116987
2010-10-21 03:11:16 +00:00
f608ac4db9
Major update of the MicroBlaze backend. The new features are:
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1. A delay slot filler that searches for valid instructions
to fill the delay slot with. Previously NOPs would always
be inserted into delay slots.
2. Support for MC based instruction printer added.
3. Support for MC based machine code generation and ELF
file generation. ELF file generation does not yet
completely work as much of the ELF support infrastructure
is still x86/x86-64 specific.
4. General clean up of the MBlaze backend code. Much of the
tablegen code has been cleanup and simplified.
Bug Fixes:
1. Removed duplicate periods from subtarget feature descriptions.
2. Many of the instructions had bad machine code information
in the tablegen files. Much of this has been fixed.
llvm-svn: 116986
2010-10-21 03:09:55 +00:00
f509c6ca27
X86: Add alloca probing to dynamic alloca on Windows. Fixes PR8424.
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llvm-svn: 116984
2010-10-21 01:41:01 +00:00
15c2ac90ec
Add missing scheduling itineraries for transfers between core registers and VFP registers.
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llvm-svn: 116983
2010-10-21 01:12:00 +00:00
Jakob Stoklund Olesen