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8 Commits

Author SHA1 Message Date
Matt Arsenault 2920f62423 AMDGPU: setcc test cleanup 
llvm-svn: 290306
 2016-12-22 03:21:45 +00:00
Matt Arsenault 5d8eb25e78 AMDGPU: Use unsigned compare for eq/ne 
For some reason there are both of these available, except
for scalar 64-bit compares which only has u64. I'm not sure
why there are both (I'm guessing it's for the one bit inputs we
don't use), but for consistency always using the
unsigned one.

llvm-svn: 282832
 2016-09-30 01:50:20 +00:00
Matt Arsenault bbb47da8a1 AMDGPU: Support commuting with immediate in src0 
llvm-svn: 280970
 2016-09-08 17:19:29 +00:00
Matt Arsenault 6689abe632 AMDGPU: Run r600 tests last 
llvm-svn: 268672
 2016-05-05 20:07:37 +00:00
Tom Stellard bc4497b13c AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions 
Reviewers: arsenm

Subscribers: mareko, MatzeB, qcolombet, arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D16603

llvm-svn: 260765
 2016-02-12 23:45:29 +00:00
Tom Stellard d1efda8e9e AMDGPU/SI: Promote i1 SETCC operations 
Summary:
While working on uniform branching, I've hit a few cases where we emit
i1 SETCC operations.

Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D16233

llvm-svn: 258352
 2016-01-20 21:48:24 +00:00
Tom Stellard 2e045bbc5f AMDGPU/SI: Prevent the DAGCombiner from creating setcc with i1 inputs 
Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D15035

llvm-svn: 258256
 2016-01-20 00:13:22 +00:00
Tom Stellard 45bb48ea19 R600 -> AMDGPU rename 
llvm-svn: 239657
 2015-06-13 03:28:10 +00:00