Commit Graph

79913 Commits

Author SHA1 Message Date
Matt Arsenault f05b02351f CodeGenPrepare: Don't match addressing modes through addrspacecast
This was resulting in the addrspacecast being removed and incorrectly
replaced with a ptrtoint when sinking.

llvm-svn: 238217
2015-05-26 16:59:43 +00:00
Rui Ueyama 407e097697 Object: Add Archive::getNumberOfSymbols().
Add a function that returns number of symbols in archive headers.

llvm-svn: 238213
2015-05-26 16:20:40 +00:00
Tom Stellard 245c15fce2 R600/SI: Add assembler support for all CI and VI VOP2 instructions
llvm-svn: 238211
2015-05-26 15:55:52 +00:00
Rafael Espindola bb9a71c1ed Replace getOrCreateSectionData with registerSection.
There is now no SectionData to be created.

llvm-svn: 238208
2015-05-26 15:07:25 +00:00
Rafael Espindola 3d2aeb2e20 Have getCurrentSectionData return a MCSection.
I will fix the name shortly.

llvm-svn: 238204
2015-05-26 14:48:11 +00:00
Rafael Espindola e6e287df74 Pass a MCSection to getCurrentSectionData.
A step towards merging MCSection and MCSectionData.

llvm-svn: 238203
2015-05-26 14:42:52 +00:00
Luke Cheeseman a5d053d6f4 Re-commit changes in r237579 with fix for bug breaking windows builds.
llvm-svn: 238201
2015-05-26 13:40:31 +00:00
Luke Cheeseman 0af4f635f1 Test Commit
llvm-svn: 238199
2015-05-26 13:10:35 +00:00
Elena Demikhovsky 887baa0b49 AVX-512: fixed a bug in arithmetic operations lowering for i1 type
https://llvm.org/bugs/show_bug.cgi?id=23630

llvm-svn: 238198
2015-05-26 12:37:17 +00:00
Elena Demikhovsky b2b901c607 AVX-512: fixed a bug in lowering VSELECT for 512-bit vector
https://llvm.org/bugs/show_bug.cgi?id=23634

llvm-svn: 238195
2015-05-26 11:32:39 +00:00
Michael Kuperstein db0712f986 Use std::bitset for SubtargetFeatures.
Previously, subtarget features were a bitfield with the underlying type being uint64_t. 
Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset.
No functional change.

The first several times this was committed (e.g. r229831, r233055), it caused several buildbot failures.
Apparently the reason for most failures was both clang and gcc's inability to deal with large numbers (> 10K) of bitset constructor calls in tablegen-generated initializers of instruction info tables. 
This should now be fixed.

llvm-svn: 238192
2015-05-26 10:47:10 +00:00
Daniel Sanders 58ee4c9451 [mips] Make TTypeEncoding indirect to allow .eh_frame to be read-only.
Summary:
Following on from r209907 which made personality encodings indirect, do the
same for TType encodings. This fixes the case where a try/catch block needs
to generate references to, for example, std::exception in the
.gcc_except_table.

This commit uses DW_EH_PE_sdata8 for N64 as far as is possible at the moment.
However, it is possible to end up with DW_EH_PE_sdata4 when a TargetMachine is
not available. There's no risk of issues with inconsistency here since the
tables are self describing but it does mean there is a small chance of the
PC-relative offset being out of range for particularly large programs.

Reviewers: petarj

Reviewed By: petarj

Subscribers: srhines, joerg, tberghammer, llvm-commits

Differential Revision: http://reviews.llvm.org/D9669

llvm-svn: 238190
2015-05-26 10:19:18 +00:00
Craig Topper f58341c6ee [TableGen] Fix line wrapping logic for the autogenerated header to use math that makes more sense (at least to me).
The old code had a bug if the description was between 75 and 85 characters or so as it substracted PSLen from Desc.size() instead of MAX_LINE_LEN in the compare. It also calculated odd values for PosE on the last split and just let StringRef::slice take care of it being larger than the description string.

llvm-svn: 238187
2015-05-26 08:07:56 +00:00
Craig Topper 33684f9e64 [TableGen] Rewrite an assert to not do a bunch unsigned math and then try to ensure the result is a positive number.
I think the fact that it was explicitly excluding 0 kept this from being a tautology. The exclusion of 0 for the old math was also a bug that's easily hit if the description gets split into multiple lines.

llvm-svn: 238186
2015-05-26 08:07:49 +00:00
Craig Topper cb7648be17 [TableGen] Put a space between '*' and description in the autogenerated tablegen header. Minor cleanup in surrounding code.
llvm-svn: 238185
2015-05-26 08:07:45 +00:00
Craig Topper e59cd0b9ec [TableGen] Fix indentation. NFC
llvm-svn: 238181
2015-05-26 06:48:47 +00:00
Craig Topper 1407b17711 [TableGen] Include header for each cpp file first. NFC
llvm-svn: 238180
2015-05-26 06:48:46 +00:00
Craig Topper cd371218be [TableGen] Remove unneeded namespace around a function. Just put llvm:: on the definition since it's already declared in a header file.
llvm-svn: 238178
2015-05-26 06:48:41 +00:00
Craig Topper b7644fd522 [TableGen] Use 'static' instead of an anonymous namespace.
llvm-svn: 238177
2015-05-26 06:48:38 +00:00
Rafael Espindola 64acc7fcc7 Remove most uses of MCSectionData from MCAssembler.
llvm-svn: 238172
2015-05-26 02:17:21 +00:00
Rafael Espindola 5a1e80bc43 Stop using MCSectionData in MCAsmLayout.h.
llvm-svn: 238170
2015-05-26 02:00:36 +00:00
Rafael Espindola ed34d58c09 Move MCSection destruction to MCContext::reset.
Fixes the leaks when running llc.

Also found by an asan bot.

llvm-svn: 238167
2015-05-26 01:52:19 +00:00
Rafael Espindola 61e724a8c5 Stop using MCSectionData in MCMachObjectWriter.h.
llvm-svn: 238165
2015-05-26 01:15:30 +00:00
Rafael Espindola 079027ea90 Stop using MCSectionData in MCExpr.h.
llvm-svn: 238163
2015-05-26 00:52:18 +00:00
Rafael Espindola 7549f87672 Return a MCSection from MCFragment::getParent().
Another step in merging MCSectionData and MCSection.

llvm-svn: 238162
2015-05-26 00:36:57 +00:00
Rafael Espindola 24d285d31b Call the destructors of the MCSections.
They now contain the fragments. If we don't call the destructors the
fragments leak.

Found by an asan bot.

llvm-svn: 238161
2015-05-26 00:32:28 +00:00
Rafael Espindola 8324c2f8be Store a MCSection in MCFragment.
Part of the work to merge MCSectionData into MCSection.

llvm-svn: 238160
2015-05-25 23:48:22 +00:00
Rafael Espindola a554c05d95 Turn MCSectionData into a field of MCSection.
This also changes MCAssembler to store a vector of MCSections instead of an
iplist of MCSectionData.

llvm-svn: 238159
2015-05-25 23:14:17 +00:00
Rafael Espindola 09266bad7f Move MCSectionData to MCSection.h.
Another step in merging MCSectionData and MCSection.

llvm-svn: 238158
2015-05-25 22:57:48 +00:00
Rafael Espindola 08850b3a88 Make a few MCSectionELF& variables const. NFC.
This just reduces the noise from another patch.

llvm-svn: 238156
2015-05-25 21:56:55 +00:00
Rafael Espindola 25ffbe17c9 Insert MCSectionData into the section list directly in getOrCreateSectionData.
Removing the logic from the constructor will make it easier to merge
MCSectionData and MCSection.

llvm-svn: 238155
2015-05-25 20:39:23 +00:00
Craig Topper 042a39274a Use range-based for loops. NFC.
llvm-svn: 238154
2015-05-25 20:01:18 +00:00
Bjorn Steinbrink 236446cd4c Remove conflicting attributes before adding deduced readonly/readnone
Summary:
In case of functions that have a pointer argument and only pass it to
each other, the function attributes pass deduces that the pointer should
get the readnone attribute, but fails to remove a readonly attribute
that may already have been present.

Reviewers: nlewycky

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9995

llvm-svn: 238152
2015-05-25 19:46:38 +00:00
Rafael Espindola cd62518369 Move HasInstructions to MCSection.
llvm-svn: 238150
2015-05-25 18:34:26 +00:00
Simon Pilgrim 0be4fa761f [X86][AVX2] Vectorized i16 shift operators
Part of D9474, this patch extends AVX2 v16i16 types to 2 x 8i32 vectors and uses i32 shift variable shifts before packing back to i16.

Adds AVX2 tests for v8i16 and v16i16 

llvm-svn: 238149
2015-05-25 17:49:13 +00:00
Tom Stellard 50828163a1 R600/SI: Remove some unnecessary patterns from VINTRP multiclass
DisableEncoding and Constraints can be set using let statements around
the multiclass defs.

llvm-svn: 238148
2015-05-25 16:15:56 +00:00
Tom Stellard ec87f841c6 R600/SI: Fix bug with v_interp_p1_f32 instructions on 16 bank lds chips
The src and dst register cannot be the same on chips with 16 lds banks.

llvm-svn: 238147
2015-05-25 16:15:54 +00:00
Tom Stellard c70cf90d09 R600/SI: Use NAME rather than opName as the key to the MCOpcode tables
This lets us drop a parameter the opName parameter to the VINTRP
multiclass and makes it possible to create multiple VINTRP defs
with the same asm mnemonic.

llvm-svn: 238146
2015-05-25 16:15:50 +00:00
Kit Barton 6646033e6e This patch adds support for the vector quadword add/sub instructions introduced
in POWER8:

vadduqm
vaddeuqm
vaddcuq
vaddecuq
vsubuqm
vsubeuqm
vsubcuq
vsubecuq
In addition to adding the instructions themselves, it also adds support for the
v1i128 type for intrinsics (Intrinsics.td, Function.cpp, and
IntrinsicEmitter.cpp).

http://reviews.llvm.org/D9081

llvm-svn: 238144
2015-05-25 15:49:26 +00:00
Rafael Espindola b028cc8098 Move bundle info from MCSectionData to MCSection.
llvm-svn: 238143
2015-05-25 15:04:26 +00:00
Rafael Espindola c1cd944854 Add a isBundleLocked helper to MCELFStreamer.
llvm-svn: 238142
2015-05-25 14:57:35 +00:00
Rafael Espindola b2ac19ed6e Move LayoutOrder to MCSection.
llvm-svn: 238141
2015-05-25 14:25:28 +00:00
Rafael Espindola 6e6820a7e6 Stop forwarding getOrdinal and setOrdinal.
llvm-svn: 238139
2015-05-25 14:12:48 +00:00
Rafael Espindola 1f02022027 Move Ordinal from MCSectionData to MCSection. NFC.
Part of the work to merge MCSectionData and MCSection.

llvm-svn: 238137
2015-05-25 14:00:56 +00:00
Rafael Espindola e7134b2d78 Simplify boolean conditional return statements.
Patch by Richard <legalize@xmission.com>

llvm-svn: 238134
2015-05-25 13:50:21 +00:00
Benjamin Kramer 68a29562f9 Refactor: Simplify boolean conditional return statements in llvm/lib/DebugInfo/DWARF
Use clang-tidy to simplify boolean conditional return statements. Patch by
Richard Thomson <legalize@xmission.com>!

Differential Revision: http://reviews.llvm.org/D9972

llvm-svn: 238132
2015-05-25 13:28:03 +00:00
Michael Kuperstein f145228676 [X86] When pattern-matching scalar FMA3 intrinsics, don't re-arrange the first and second operands.
The semantics of the scalar FMA intrinsics are that the high vector elements are copied from the first source.
The existing pattern switches src1 and src2 around, to match the "213" order, which ends up tying the original src2 to the dest. Since the actual scalar fma3 instructions copy the high elements from the dest register, the wrong values are copied.

This modifies the pattern to leave src1 and src2 in their original order.

Differential Revision: http://reviews.llvm.org/D9908

llvm-svn: 238131
2015-05-25 12:35:25 +00:00
Elena Demikhovsky 1c1391ba24 Added promotion to EXTRACT_SUBVECTOR operand.
I encountered with this case in one of KNL tests for i1 vectors.
v16i1 = EXTRACT_SUBVECTOR v32i1, x

llvm-svn: 238130
2015-05-25 11:33:13 +00:00
NAKAMURA Takumi 5582a6a4a5 Reformat.
llvm-svn: 238126
2015-05-25 01:43:34 +00:00
NAKAMURA Takumi fb3bd7127a Prune CRLFs.
llvm-svn: 238125
2015-05-25 01:43:23 +00:00