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9659 Commits

Author SHA1 Message Date
Duncan Sands 12da8ce3d2 Introduce new linkage types linkonce_odr, weak_odr, common_odr 
and extern_weak_odr.  These are the same as the non-odr versions,
except that they indicate that the global will only be overridden
by an *equivalent* global.  In C, a function with weak linkage can
be overridden by a function which behaves completely differently.
This means that IP passes have to skip weak functions, since any
deductions made from the function definition might be wrong, since
the definition could be replaced by something completely different
at link time.   This is not allowed in C++, thanks to the ODR
(One-Definition-Rule): if a function is replaced by another at
link-time, then the new function must be the same as the original
function.  If a language knows that a function or other global can
only be overridden by an equivalent global, it can give it the
weak_odr linkage type, and the optimizers will understand that it
is alright to make deductions based on the function body.  The
code generators on the other hand map weak and weak_odr linkage
to the same thing.

llvm-svn: 66339
 2009-03-07 15:45:40 +00:00
Dan Gohman ff659b5b86 Arithmetic instructions don't set EFLAGS bits OF and CF bits 
the same say the "test" instruction does in overflow cases,
so eliminating the test is only safe when those bits aren't
needed, as is the case for COND_E and COND_NE, or if it
can be proven that no overflow will occur. For now, just
restrict the optimization to COND_E and COND_NE and don't
do any overflow analysis.

llvm-svn: 66318
 2009-03-07 01:58:32 +00:00
Dan Gohman c719d73eec Don't use plain INC32 and DEC32 on x86-64; it needs 
INC64_32r and INC64_16r, because these instructions are encoded
differently on x86-64. This fixes JIT regressions on x86-64 in
kimwitu++ and others.

llvm-svn: 66207
 2009-03-05 21:32:23 +00:00
Dan Gohman e014b193c9 When creating X86ISD::INC and X86ISD::DEC nodes, only add one operand. 
The extra operand didn't appear to cause any trouble, but it was
erroneous regardless.

llvm-svn: 66206
 2009-03-05 21:29:28 +00:00
Dan Gohman 2c2f192c74 Fix the "test" optimization to recognize "dec" as an add of 
negative one, as subtracts of immediates are canonicalized
to adds.

llvm-svn: 66180
 2009-03-05 19:32:48 +00:00
Dan Gohman 55d7b2ac4f Re-apply 66008, now that the unfoldMemoryOperand bug is fixed. 
llvm-svn: 66058
 2009-03-04 19:44:21 +00:00
Dan Gohman f8920d0c75 Correct this comment. 
llvm-svn: 66057
 2009-03-04 19:24:25 +00:00
Dan Gohman cc329b567d When using MachineInstr operand indices on SDNodes, the number 
of MachineInstr def operands must be subtracted out. This bug
was uncovered by the recent x86 EFLAGS optimization. Before
that, the only instructions that ever needed unfolding were
things like CMP32rm, where NumDefs is zero.

llvm-svn: 66056
 2009-03-04 19:23:38 +00:00
Evan Cheng 9edd616b59 Fix PR3666: isel calls to constant addresses. 
llvm-svn: 66024
 2009-03-04 06:48:53 +00:00
Dan Gohman 6728f892be Revert r66004 for now; it's causing a variety of test failures. 
llvm-svn: 66008
 2009-03-04 03:54:19 +00:00
Dan Gohman fe8d71f42a Teach the x86 backend to eliminate "test" instructions by using the EFLAGS 
result from add, sub, inc, and dec instructions in simple cases.

llvm-svn: 66004
 2009-03-04 02:33:24 +00:00
Evan Cheng b8905c4e2c Fix PR3701. 1. X86 target renamed eflags register to flags. This matches what llvm-gcc generates so codegen knows flags register is being clobbered by inline asm. 2. BURR scheduler should also check if inline asm nodes can clobber "live" physical registers. Previously it was only checking target nodes with implicit defs. 
llvm-svn: 65996
 2009-03-04 01:41:49 +00:00
Dan Gohman 3a72265d41 Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC 
instructions. These aren't used yet.

llvm-svn: 65965
 2009-03-03 19:53:46 +00:00
Bob Wilson 530e038940 Use early exit to reduce indentation. No functional change. 
llvm-svn: 65962
 2009-03-03 19:26:27 +00:00
Dan Gohman 92b551bc2b Fix a bunch of Doxygen syntax issues. Escape special characters, 
and put @file directives on their own comment line.

llvm-svn: 65920
 2009-03-03 02:55:14 +00:00
Bob Wilson 85cefe8567 Generalize BuildVectorSDNode::isConstantSplat to use APInts and handle 
arbitrary vector sizes.  Add an optional MinSplatBits parameter to specify
a minimum for the splat element size.  Update the PPC target to use the
revised interface.

llvm-svn: 65899
 2009-03-02 23:24:16 +00:00
Bob Wilson d8ea0e144e Combine PPC's GetConstantBuildVectorBits and isConstantSplat functions to a new 
method in a BuildVectorSDNode "pseudo-class".

llvm-svn: 65747
 2009-03-01 01:13:55 +00:00
Mon P Wang d844dc305e Added another darwin subtarget 
llvm-svn: 65662
 2009-02-28 00:25:30 +00:00
Rafael Espindola 000421eade Refactor TLS code and add some tests. The tests and expected results are: 
pic |  declaration | linkage  | visibility |

!pic |  declaration | external | default    | tls1.ll     tls2.ll     | local exec
 pic |  declaration | external | default    | tls1-pic.ll tls2-pic.ll | general dynamic
!pic | !declaration | external | default    | tls3.ll     tls4.ll     | initial exec
 pic | !declaration | external | default    | tls3-pic.ll tls4-pic.ll | general dynamic

!pic |  declaration | external | hidden     | tls7.ll     tls8.ll     | local exec
 pic |  declaration | external | hidden     | X                       | local dynamic
!pic | !declaration | external | hidden     | tls9.ll     tls10.ll    | local exec
 pic | !declaration | external | hidden     | X                       | local dynamic

!pic |  declaration | internal | default    | tls5.ll     tls6.ll     | local exec
 pic |  declaration | internal | default    | X                       | local dynamic

The ones marked with an X have not been implemented since local dynamic is not implemented.

llvm-svn: 65632
 2009-02-27 13:37:18 +00:00
Dale Johannesen 4609dbe222 Alignment values for i64 and f64 on ppc64 were wrong, 
possibly for the reason suggested by the comment.
No wonder it didn't work very well.  This unblocks
bootstrap with assertions on ppc.

llvm-svn: 65601
 2009-02-27 00:56:35 +00:00
Evan Cheng 40abb7b5d0 ADDS{D|S}rr_Int and MULS{D|S}rr_Int are not commutable. The users of these intrinsics expect the high bits will not be modified. 
llvm-svn: 65499
 2009-02-26 03:12:02 +00:00
Evan Cheng a49de9de2e Revert BuildVectorSDNode related patches: 65426, 65427, and 65296. 
llvm-svn: 65482
 2009-02-25 22:49:59 +00:00
Nick Lewycky 5c10a3aa7f Add a totally synthetic situation I came up with while looking at a bug in 
related code.

llvm-svn: 65437
 2009-02-25 06:52:48 +00:00
Scott Michel bb878288cb Remove all "cached" data from BuildVectorSDNode, preferring to retrieve 
results via reference parameters.

This patch also appears to fix Evan's reported problem supplied as a
reduced bugpoint test case.

llvm-svn: 65426
 2009-02-25 03:12:50 +00:00
Bill Wendling c5437ea429 Overhaul my earlier submission due to feedback. It's a large patch, but most of 
them are generic changes.

- Use the "fast" flag that's already being passed into the asm printers instead
  of shoving it into the DwarfWriter.

- Instead of calling "MI->getParent()->getParent()" for every MI, set the
  machine function when calling "runOnMachineFunction" in the asm printers.

llvm-svn: 65379
 2009-02-24 08:30:20 +00:00
Dan Gohman 318d7376ba Fast-isel can't do TLS yet, so it should fall back to SDISel 
if it sees TLS addresses.

llvm-svn: 65341
 2009-02-23 22:03:08 +00:00
Evan Cheng 9f8fddeed8 Only v1i16 (i.e. _m64) is returned via RAX / RDX. 
llvm-svn: 65313
 2009-02-23 09:03:22 +00:00
Nate Begeman e684da3e5d Generate better code for v8i16 shuffles on SSE2 
Generate better code for v16i8 shuffles on SSE2 (avoids stack)
Generate pshufb for v8i16 and v16i8 shuffles on SSSE3 where it is fewer uops.
Document the shuffle matching logic and add some FIXMEs for later further
  cleanups.
New tests that test the above.

Examples:

New:
_shuf2:
	pextrw	$7, %xmm0, %eax
	punpcklqdq	%xmm1, %xmm0
	pshuflw	$128, %xmm0, %xmm0
	pinsrw	$2, %eax, %xmm0

Old:
_shuf2:
	pextrw	$2, %xmm0, %eax
	pextrw	$7, %xmm0, %ecx
	pinsrw	$2, %ecx, %xmm0
	pinsrw	$3, %eax, %xmm0
	movd	%xmm1, %eax
	pinsrw	$4, %eax, %xmm0
	ret

=========

New:
_shuf4:
	punpcklqdq	%xmm1, %xmm0
	pshufb	LCPI1_0, %xmm0

Old:
_shuf4:
	pextrw	$3, %xmm0, %eax
	movsd	%xmm1, %xmm0
	pextrw	$3, %xmm1, %ecx
	pinsrw	$4, %ecx, %xmm0
	pinsrw	$5, %eax, %xmm0

========

New:
_shuf1:
	pushl	%ebx
	pushl	%edi
	pushl	%esi
	pextrw	$1, %xmm0, %eax
	rolw	$8, %ax
	movd	%xmm0, %ecx
	rolw	$8, %cx
	pextrw	$5, %xmm0, %edx
	pextrw	$4, %xmm0, %esi
	pextrw	$3, %xmm0, %edi
	pextrw	$2, %xmm0, %ebx
	movaps	%xmm0, %xmm1
	pinsrw	$0, %ecx, %xmm1
	pinsrw	$1, %eax, %xmm1
	rolw	$8, %bx
	pinsrw	$2, %ebx, %xmm1
	rolw	$8, %di
	pinsrw	$3, %edi, %xmm1
	rolw	$8, %si
	pinsrw	$4, %esi, %xmm1
	rolw	$8, %dx
	pinsrw	$5, %edx, %xmm1
	pextrw	$7, %xmm0, %eax
	rolw	$8, %ax
	movaps	%xmm1, %xmm0
	pinsrw	$7, %eax, %xmm0
	popl	%esi
	popl	%edi
	popl	%ebx
	ret

Old:
_shuf1:
	subl	$252, %esp
	movaps	%xmm0, (%esp)
	movaps	%xmm0, 16(%esp)
	movaps	%xmm0, 32(%esp)
	movaps	%xmm0, 48(%esp)
	movaps	%xmm0, 64(%esp)
	movaps	%xmm0, 80(%esp)
	movaps	%xmm0, 96(%esp)
	movaps	%xmm0, 224(%esp)
	movaps	%xmm0, 208(%esp)
	movaps	%xmm0, 192(%esp)
	movaps	%xmm0, 176(%esp)
	movaps	%xmm0, 160(%esp)
	movaps	%xmm0, 144(%esp)
	movaps	%xmm0, 128(%esp)
	movaps	%xmm0, 112(%esp)
	movzbl	14(%esp), %eax
	movd	%eax, %xmm1
	movzbl	22(%esp), %eax
	movd	%eax, %xmm2
	punpcklbw	%xmm1, %xmm2
	movzbl	42(%esp), %eax
	movd	%eax, %xmm1
	movzbl	50(%esp), %eax
	movd	%eax, %xmm3
	punpcklbw	%xmm1, %xmm3
	punpcklbw	%xmm2, %xmm3
	movzbl	77(%esp), %eax
	movd	%eax, %xmm1
	movzbl	84(%esp), %eax
	movd	%eax, %xmm2
	punpcklbw	%xmm1, %xmm2
	movzbl	104(%esp), %eax
	movd	%eax, %xmm1
	punpcklbw	%xmm1, %xmm0
	punpcklbw	%xmm2, %xmm0
	movaps	%xmm0, %xmm1
	punpcklbw	%xmm3, %xmm1
	movzbl	127(%esp), %eax
	movd	%eax, %xmm0
	movzbl	135(%esp), %eax
	movd	%eax, %xmm2
	punpcklbw	%xmm0, %xmm2
	movzbl	155(%esp), %eax
	movd	%eax, %xmm0
	movzbl	163(%esp), %eax
	movd	%eax, %xmm3
	punpcklbw	%xmm0, %xmm3
	punpcklbw	%xmm2, %xmm3
	movzbl	188(%esp), %eax
	movd	%eax, %xmm0
	movzbl	197(%esp), %eax
	movd	%eax, %xmm2
	punpcklbw	%xmm0, %xmm2
	movzbl	217(%esp), %eax
	movd	%eax, %xmm4
	movzbl	225(%esp), %eax
	movd	%eax, %xmm0
	punpcklbw	%xmm4, %xmm0
	punpcklbw	%xmm2, %xmm0
	punpcklbw	%xmm3, %xmm0
	punpcklbw	%xmm1, %xmm0
	addl	$252, %esp
	ret

llvm-svn: 65311
 2009-02-23 08:49:38 +00:00
Bill Wendling 9ee052bcdc Propagate debug loc info through prologue/epilogue. 
llvm-svn: 65298
 2009-02-23 00:42:30 +00:00
Scott Michel 9d31aca679 Introduce the BuildVectorSDNode class that encapsulates the ISD::BUILD_VECTOR 
instruction. The class also consolidates the code for detecting constant
splats that's shared across PowerPC and the CellSPU backends (and might be
useful for other backends.) Also introduces SelectionDAG::getBUID_VECTOR() for
generating new BUILD_VECTOR nodes.

llvm-svn: 65296
 2009-02-22 23:36:09 +00:00
Evan Cheng 2448aa1d8d Add a note. 
llvm-svn: 65275
 2009-02-22 08:13:45 +00:00
Evan Cheng e4ffc030e2 Be bug compatible with gcc by returning MMX values in RAX. 
llvm-svn: 65274
 2009-02-22 08:05:12 +00:00
Evan Cheng 91193c0094 Do not consider MMX_MOVD64rr a move instructions. The source register is in GR32, the destination is VR64. They are not compatible. 
llvm-svn: 65273
 2009-02-22 08:04:23 +00:00
Anton Korobeynikov 42aae86590 Drop bunch of half-working stuff in the ext_weak linkage support. 
Now we're using one gross, but quite robust hack :) (previous ones
did not work, for example, when ext_weak symbol was used deep inside
constant expression in the initializer).

The proper fix of this problem will require some quite huge asmprinter
changes and that's why was postponed. This fixes PR3629 by the way :)

llvm-svn: 65230
 2009-02-21 11:53:32 +00:00
Bill Wendling 82aa14fae8 Make sure this doesn't access .end() too. 
llvm-svn: 65213
 2009-02-21 01:11:36 +00:00
Bill Wendling 81ebf9a578 Make sure we don't dereference the .end() of the container. 
llvm-svn: 65211
 2009-02-21 01:07:26 +00:00
Bill Wendling 56759ee658 Propagate more debug loc infos. This also includes some code cleaning. 
llvm-svn: 65207
 2009-02-21 00:43:56 +00:00
Bill Wendling 5191934371 We need to propagate the debug location information even when dealing with the 
prologue/epilogue.

llvm-svn: 65206
 2009-02-21 00:32:08 +00:00
Evan Cheng 2a9bad5ac1 Support return of MMX values in 64-bit mode. 
llvm-svn: 65152
 2009-02-20 20:43:02 +00:00
Torok Edwin 87d5ca083b add note about sin 
llvm-svn: 65137
 2009-02-20 18:42:06 +00:00
Bill Wendling 0f4c581c4a Put code that generates debug labels into TableGen so that it can be used by 
everyone.

llvm-svn: 64978
 2009-02-18 23:12:06 +00:00
Dan Gohman 8cab4c44bb Add explicit keywords. 
llvm-svn: 64915
 2009-02-18 16:37:45 +00:00
Nate Begeman 18d85e7403 Add support to the JIT for true non-lazy operation. When a call to a function 
that has not been JIT'd yet, the callee is put on a list of pending functions
to JIT.  The call is directed through a stub, which is updated with the address
of the function after it has been JIT'd.  A new interface for allocating and
updating empty stubs is provided.

Add support for removing the ModuleProvider the JIT was created with, which
would otherwise invalidate the JIT's PassManager, which is initialized with the
ModuleProvider's Module.

Add support under a new ExecutionEngine flag for emitting the infomration 
necessary to update Function and GlobalVariable stubs after JITing them, by
recording the address of the stub and the name of the GlobalValue.  This allows
code to be copied from one address space to another, where libraries may live
at different virtual addresses, and have the stubs updated with their new
correct target addresses.

llvm-svn: 64906
 2009-02-18 08:31:02 +00:00
Dan Gohman 2af1f85f1f Factor out the code to add a MachineOperand to a MachineInstrBuilder. 
llvm-svn: 64891
 2009-02-18 05:45:50 +00:00
Evan Cheng a40d5e14ab GV with null value initializer shouldn't go to BSS if it's meant for a mergeable strings section. Currently it only checks for Darwin. Someone else please check if it should apply to other targets as well. 
llvm-svn: 64877
 2009-02-18 02:19:52 +00:00
Scott Michel cf0da6c597 Remove trailing whitespace to reduce later commit patch noise. 
(Note: Eventually, commits like this will be handled via a pre-commit hook that
 does this automagically, as well as expand tabs to spaces and look for 80-col
 violations.)

llvm-svn: 64827
 2009-02-17 22:15:04 +00:00
Chris Lattner cba4b6f83d add a horrible note 
llvm-svn: 64719
 2009-02-17 01:16:14 +00:00
Bill Wendling 3c50922ea0 --- Merging (from foreign repository) r64714 into '.': 
U    include/llvm/CodeGen/DebugLoc.h
U    lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
U    lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp

Enable debug location generation at -Os. This goes with the reapplication of the
r63639 patch.

llvm-svn: 64715
 2009-02-17 01:04:54 +00:00
Dan Gohman 2a4553ba5f Delete trailing whitespace. 
llvm-svn: 64694
 2009-02-16 23:14:14 +00:00
Dan Gohman f6ccacba36 MachineLICM now handles these cases. 
llvm-svn: 64620
 2009-02-15 23:24:52 +00:00