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37 Commits

Author SHA1 Message Date
Dan Gohman 69cc2cbbff Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning. 
llvm-svn: 60487
 2008-12-03 18:15:48 +00:00
Andrew Lenharth 9b254eed32 llvm.memory.barrier, and impl for x86 and alpha 
llvm-svn: 47204
 2008-02-16 01:24:58 +00:00
Chris Lattner a4ce4f6987 rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate. 
llvm-svn: 45667
 2008-01-06 23:38:27 +00:00
Chris Lattner a348f55ec6 Change the 'isStore' inferrer to look for 'SDNPMayStore' 
instead of "ISD::STORE".  This allows us to mark target-specific dag
nodes as storing (such as ppc byteswap stores).  This allows us to remove
more explicit isStore flags from the .td files.

Finally, add a warning for when a .td file contains an explicit 
isStore and tblgen is able to infer it.

llvm-svn: 45654
 2008-01-06 06:44:58 +00:00
Chris Lattner f3ebc3f3d2 Remove attribution from file headers, per discussion on llvmdev. 
llvm-svn: 45418
 2007-12-29 20:36:04 +00:00
Evan Cheng ac1591be42 No more noResults. 
llvm-svn: 40132
 2007-07-21 00:34:19 +00:00
Evan Cheng 94b5a80b93 Change instruction description to split OperandList into OutOperandList and 
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033
 2007-07-19 01:14:50 +00:00
Andrew Lenharth 2077814c91 Use this nifty Constraints thing and fix the inverted conditional moves 
llvm-svn: 36191
 2007-04-17 04:07:59 +00:00
Andrew Lenharth 692e4155aa Add all that branch mangling niftiness 
llvm-svn: 31313
 2006-10-31 16:49:55 +00:00
Andrew Lenharth 80528499cf Let the alpha breakage begin. First Formals and RET. next Calls 
llvm-svn: 28753
 2006-06-12 18:09:24 +00:00
Andrew Lenharth 16b96d2cb4 Alpha Scheduling classes 
llvm-svn: 26643
 2006-03-09 17:16:45 +00:00
Andrew Lenharth 4b1c726fbb Add immediate forms of cmov and remove some cruft 
llvm-svn: 25882
 2006-02-01 19:37:33 +00:00
Andrew Lenharth 0a01374299 minor renaming 
llvm-svn: 25640
 2006-01-26 03:24:15 +00:00
Andrew Lenharth 153f808f53 allow R28 to be used for frame calculations without entirely removing it from circulation 
llvm-svn: 25639
 2006-01-26 03:22:07 +00:00
Andrew Lenharth 34380b7675 stack and rpcc 
llvm-svn: 25369
 2006-01-16 21:22:38 +00:00
Andrew Lenharth 6bec63aac9 Move brcond over and fix some imm patterns. This may be the last change before changing the default alpha isel. 
llvm-svn: 25057
 2006-01-01 22:16:14 +00:00
Andrew Lenharth f520093eb3 add br pattern, unify JSR and BSR ISel instrs, and add BSR support for DAG 
llvm-svn: 25011
 2005-12-25 17:36:48 +00:00
Andrew Lenharth b9aaea3564 Unify the patterns for loads and stores. Now offset addressing should be 
supported.  This almost completes memory operations.

llvm-svn: 25002
 2005-12-24 07:34:33 +00:00
Andrew Lenharth 636e1aed43 move loads and stores over. Smart addr selection comming 
llvm-svn: 25000
 2005-12-24 03:41:56 +00:00
Andrew Lenharth 29b7ef0065 OK, this does wonders for broken stuff 
llvm-svn: 24624
 2005-12-06 20:40:34 +00:00
Andrew Lenharth e788bbf6ef added instructions with inverted immediates 
llvm-svn: 24614
 2005-12-06 00:33:53 +00:00
Andrew Lenharth 3c7c4d7508 These never trigger, but whatever 
llvm-svn: 24612
 2005-12-05 23:19:44 +00:00
Andrew Lenharth 6db615df14 All sorts of stuff. 
Getting in on the custom lowering thing, yay
evilness with fp setcc, yuck
trivial int select, hmmm
in memory args for functions, yay
DIV and REM, always handy.  They should be custom lowered though.

Lots more stuff compiles now (go go single source!).  Of course, none of it
probably works, but that is what the nightly tester can find out :)

llvm-svn: 24533
 2005-11-30 07:19:56 +00:00
Andrew Lenharth 0294e33ea4 massive DAGISel patch. lots and lots more stuff compiles now 
llvm-svn: 24483
 2005-11-22 04:20:06 +00:00
Andrew Lenharth 01aa56397d continued readcyclecounter support 
llvm-svn: 24300
 2005-11-11 16:47:30 +00:00
Andrew Lenharth 97a7fcfd2b whatever. Intermediate patch to see what breaks. Seems ok. 
llvm-svn: 24260
 2005-11-09 19:17:08 +00:00
Andrew Lenharth 7ac194560e Simplify instinfo, set random bits on more fp insts, and fix 1 opcode 
llvm-svn: 24014
 2005-10-26 17:41:46 +00:00
Andrew Lenharth 5a990417f8 Well, the Constant matching pattern works. Can't say much about calls or globals yet. 
llvm-svn: 23884
 2005-10-22 22:06:58 +00:00
Andrew Lenharth a6a23b5874 Inst cleanup. As a bonus, operands are in the correct order for cmovs. Expect new stuff to pass in the JIT tonight 
llvm-svn: 23852
 2005-10-20 23:58:36 +00:00
Andrew Lenharth d4c0ed74e4 added a few 1 operand form stuff. Seems to break regalloc on alpha. sigh 
llvm-svn: 23849
 2005-10-20 19:39:24 +00:00
Andrew Lenharth 7b69867052 ret 0; works, not much else 
still lots of uglyness.
Maybe calls will come soon.
Fixing the return value of things will be necessary to make alpha work.

llvm-svn: 23832
 2005-10-20 00:28:31 +00:00
Andrew Lenharth 1ec48e8683 support bsr, and more .td simplification 
llvm-svn: 22543
 2005-07-28 18:14:47 +00:00
Andrew Lenharth 02daecc7c6 simpilfy instruction encoding (and make the lines way shorter, aka Misha happification) 
llvm-svn: 22499
 2005-07-22 20:50:29 +00:00
Misha Brukman ffe9968b5a Make the rest of file header comments consistent in format and style 
llvm-svn: 20048
 2005-02-05 02:24:26 +00:00
Andrew Lenharth 5ae5f81720 initial fp support 
llvm-svn: 19847
 2005-01-26 21:54:09 +00:00
Andrew Lenharth 2f0f845534 Clean ups, and taught the instruction selector about immediate forms 
llvm-svn: 19816
 2005-01-24 19:44:07 +00:00
Andrew Lenharth a1b5ca2b9d Let me introduce you to the early stages of the llvm backend for the alpha processor 
llvm-svn: 19764
 2005-01-22 23:41:55 +00:00