83d2e066c1
Add a README entry noticed while investigating PR3216.
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llvm-svn: 62558
2009-01-20 01:07:33 +00:00
44cc554311
DIVREM isel deficiency: If sign bit is known zero, zero out DX/EDX/RDX instead of sign extending the low part (in AX/EAX/RAX) into it.
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llvm-svn: 62519
2009-01-19 19:06:11 +00:00
0346c04f39
Fix 80 col violations.
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llvm-svn: 62518
2009-01-19 18:57:29 +00:00
6c02498215
Handle ISD::DECLARE with PIC relocation model.
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llvm-svn: 62516
2009-01-19 18:31:51 +00:00
8f367e53c7
Minor tweak to LowerUINT_TO_FP_i32. Bias (after scalar_to_vector) has two uses so we should make it the second source operand of ISD::OR so 2-address pass won't have to be smart about commuting.
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%reg1024<def> = MOVSDrm %reg0, 1, %reg0, <cp#0>, Mem:LD(8,8) [ConstantPool + 0]
%reg1025<def> = MOVSD2PDrr %reg1024
%reg1026<def> = MOVDI2PDIrm <fi#-1>, 1, %reg0, 0, Mem:LD(4,16) [FixedStack-1 + 0]
%reg1027<def> = ORPSrr %reg1025<kill>, %reg1026<kill>
%reg1028<def> = MOVPD2SDrr %reg1027<kill>
%reg1029<def> = SUBSDrr %reg1028<kill>, %reg1024<kill>
%reg1030<def> = CVTSD2SSrr %reg1029<kill>
MOVSSmr <fi#0>, 1, %reg0, 0, %reg1030<kill>, Mem:ST(4,4) [FixedStack0 + 0]
%reg1031<def> = LD_Fp32m80 <fi#0>, 1, %reg0, 0, Mem:LD(4,16) [FixedStack0 + 0]
RET %reg1031<kill>, %ST0<imp-use,kill>
The reason 2-addr pass isn't smart enough to commute the ORPSrr is because it can't look pass the MOVSD2PDrr instruction.
llvm-svn: 62505
2009-01-19 08:19:57 +00:00
7e9ef4d776
Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't
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optimize it to a SINT_TO_FP when the sign bit is known zero. X86 isel should perform the optimization itself.
llvm-svn: 62504
2009-01-19 08:08:22 +00:00
f9291cf43c
Extend thi
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llvm-svn: 62415
2009-01-17 07:40:19 +00:00
bf38a5e540
Fix MatchAddress bug that's preventing negative displacement from being folded in 64-bit mode.
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llvm-svn: 62413
2009-01-17 07:09:27 +00:00
dd40f26877
Temporarily revert my last change. It is causing a bootstrap failure.
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llvm-svn: 62405
2009-01-17 04:23:51 +00:00
4d5275905e
Implement a special algorithm for converting uint_to_fp for i32 values on
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X86. This code:
void f() {
uint32_t x;
float y = (float)x;
}
used to be:
movl %eax, -8(%ebp)
movl [2^52 double], -4(%ebp)
movsd -8(%ebp), %xmm0
subsd [2^52 double], %xmm0
cvtsd2ss %xmm0, %xmm0
Is now:
movsd [2^52 double], %xmm0
movsd %xmm0, %xmm1
movd %ecx, %xmm2
orps %xmm2, %xmm1
subsd %xmm0, %xmm1
cvtsd2ss %xmm1, %xmm0
This is faster on X86. Note that there's an extra load of %xmm0 into %xmm1. That
will be fixed in a later coalescer fix.
llvm-svn: 62404
2009-01-17 03:56:04 +00:00
90cc7050f2
CMake: Add lib/Target/IA64/IA64Subtarget.cpp
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llvm-svn: 62394
2009-01-17 01:50:32 +00:00
41e9f6a854
Fix PPC ISD::Declare isel and eliminate the need for PPCTargetLowering::LowerGlobalAddress to check if isVerifiedDebugInfoDesc() is true. Given the recent changes, it would falsely return true for a lot of GlobalAddressSDNode's.
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llvm-svn: 62373
2009-01-16 22:57:32 +00:00
703a6c7274
Give IA64 a TargetSubtarget subclass, so that it can
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implement getSubtargetImpl.
llvm-svn: 62369
2009-01-16 22:49:36 +00:00
e04334730e
Add support for non-zero __builtin_return_address values on X86.
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llvm-svn: 62338
2009-01-16 19:25:27 +00:00
d243c0e3d9
ARMCompilationCallback should not save / restore vfp registers if vfp is not available.
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llvm-svn: 62299
2009-01-16 02:16:37 +00:00
ceac7c34f1
Initial hazard recognizer support in post-pass scheduling. This includes
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a new toy hazard recognizier heuristic which attempts to direct the
scheduler to avoid clumping large groups of loads or stores too densely.
llvm-svn: 62291
2009-01-16 01:33:36 +00:00
7e105f0b12
Generalize the HazardRecognizer interface so that it can be used
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to support MachineInstr-based scheduling in addition to
SDNode-based scheduling.
llvm-svn: 62284
2009-01-15 22:18:12 +00:00
f2831d6cd1
Fix Alpha test and support for private linkage.
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llvm-svn: 62282
2009-01-15 21:51:46 +00:00
ebfafee903
Expand insert/extract of a <4 x i32> with a variable index.
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llvm-svn: 62281
2009-01-15 21:10:20 +00:00
6de96a1b5d
Add the private linkage.
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llvm-svn: 62279
2009-01-15 20:18:42 +00:00
619ef48a52
Move a few containers out of ScheduleDAGInstrs::BuildSchedGraph
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and into the ScheduleDAGInstrs class, so that they don't get
destructed and re-constructed for each block. This fixes a
compile-time hot spot in the post-pass scheduler.
To help facilitate this, tidy and do some minor reorganization
in the scheduler constructor functions.
llvm-svn: 62275
2009-01-15 19:20:50 +00:00
dbb22a4483
Add load-folding table entries for BT*ri8 instructions.
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llvm-svn: 62267
2009-01-15 17:57:09 +00:00
0ad43ca6e5
Make getWidenVectorType const.
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llvm-svn: 62265
2009-01-15 17:34:08 +00:00
02b93136e9
Const-qualify getPreIndexedAddressParts and friends.
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llvm-svn: 62259
2009-01-15 16:29:45 +00:00
40119780a8
Don't fold address calculations which use negative offsets into
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the ADDRspii addressing mode.
llvm-svn: 62258
2009-01-15 11:32:30 +00:00
502b91a35c
Update the operands used when building LDAWSP instructions to match the .td
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changes in the last commit.
llvm-svn: 62257
2009-01-15 11:18:53 +00:00
a292fc6d6b
- Convert remaining i64 custom lowering into custom instruction emission
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sequences in SPUDAGToDAGISel.cpp and SPU64InstrInfo.td, killing custom
DAG node types as needed.
- i64 mul is now a legal instruction, but emits an instruction sequence
that stretches tblgen and the imagination, as well as violating laws of
several small countries and most southern US states (just kidding, but
looking at a function with 80+ parameters is really weird and just plain
wrong.)
- Update tests as needed.
llvm-svn: 62254
2009-01-15 04:41:47 +00:00
4359325ba8
Add pseudo instructions to the XCore for (load|store|load address) of a
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frame index. eliminateFrameIndex will replace these instructions with
(LDWSP|STWSP|LDAWSP) or (LDW|STW|LDAWF) if a frame pointer is in use.
This fixes PR 3324. Previously we used LDWSP, STWSP, LDAWSP before frame
pointer elimination. However since they were marked as implicitly using
SP they could not be rematerialised.
llvm-svn: 62238
2009-01-14 18:26:46 +00:00
b0a78f8fa1
fix memleaks
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llvm-svn: 62198
2009-01-13 23:35:49 +00:00
a63bede3c6
BT appears to be available on all >= i386 chips.
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llvm-svn: 62196
2009-01-13 23:27:15 +00:00
d3942af5cb
Don't use a BT instruction if the AND has multiple uses.
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llvm-svn: 62195
2009-01-13 23:25:30 +00:00
b8f5ba6781
Disable the register+memory forms of the bt instructions for now. Thanks
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to Eli for pointing out that these forms don't ignore the high bits of
their index operands, and as such are not immediately suitable for use
by isel.
llvm-svn: 62194
2009-01-13 23:23:30 +00:00
0fdf71cb9d
Add bt instructions that take immediate operands.
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llvm-svn: 62180
2009-01-13 20:33:23 +00:00
eb2591bbdd
Fix a few more JIT encoding issues in the BT instructions.
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llvm-svn: 62179
2009-01-13 20:32:45 +00:00
45da8b779c
Checking in conditionals, function call, arrays and libcalls implementation.
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llvm-svn: 62174
2009-01-13 19:18:47 +00:00
1a579351d2
make -march=cpp handle the nocapture attribute, make it assert if it
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sees attributes it doesn't know.
llvm-svn: 62155
2009-01-13 07:22:22 +00:00
5c6e1e3b7d
Use DebugInfo interface to lower dbg_* intrinsics.
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llvm-svn: 62127
2009-01-13 00:35:13 +00:00
dc020f9c3c
Rename getABITypeSize to getTypePaddedSize, as
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suggested by Chris.
llvm-svn: 62099
2009-01-12 20:38:59 +00:00
5a272e79e5
80 col violation.
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llvm-svn: 62024
2009-01-10 03:33:22 +00:00
5cbf223916
Removed trailing whitespace from Makefiles.
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llvm-svn: 61991
2009-01-09 16:44:42 +00:00
bdc0f8b627
Add load-folding table entries for MOVDQA.
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llvm-svn: 61972
2009-01-09 02:40:34 +00:00
e907a0a527
Whitespace and other minor adjustments to make SSE instructions have
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the same formatting as their corresponding SSE2 instructions, for
consistency.
llvm-svn: 61971
2009-01-09 02:27:34 +00:00
f646668799
Convert DwarfWriter into a pass.
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Now Users request DwarfWriter through getAnalysisUsage() instead of creating an instance of DwarfWriter object directly.
llvm-svn: 61955
2009-01-08 23:40:34 +00:00
6c2ee50e28
add some more crazy strlen and memcpy stuff I noticed in spec.
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llvm-svn: 61918
2009-01-08 07:34:55 +00:00
7cb3ae0505
add some notes about strlen craziness in eon.
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llvm-svn: 61917
2009-01-08 06:52:57 +00:00
b51cdfadda
Fix off-by-one error in traversing an array; this fixes a test.
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The error was reported by gcc-4.3.0 during compilation.
llvm-svn: 61896
2009-01-07 23:07:29 +00:00
8e8d1da35a
Add patterns to match conditional moves with loads folded
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into their left operand, rather than their right. Do this
by commuting the operands and inverting the condition.
llvm-svn: 61842
2009-01-07 01:00:24 +00:00
1e6e9a8b9b
Add load-folding table entries for cmovno too.
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llvm-svn: 61841
2009-01-07 00:44:53 +00:00
7e47cc7cda
Define instructions for cmovo and cmovno.
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llvm-svn: 61836
2009-01-07 00:35:10 +00:00
33e6fcd56f
X86_COND_C and X86_COND_NC are alternate mnemonics for
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X86_COND_B and X86_COND_AE, respectively.
llvm-svn: 61835
2009-01-07 00:15:08 +00:00
Dan Gohman