11d61613af
Fixed a bug introduced by my last commit: TargetGlobalValues should key on
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GlobalValue * and index pair. Update getGlobalAddress() for symmetry.
llvm-svn: 24524
2005-11-30 02:49:21 +00:00
0e0de2f3f0
Added an index field to GlobalAddressSDNode so it can represent X+12, etc.
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llvm-svn: 24523
2005-11-30 02:04:11 +00:00
d2cb70513d
Fixed a minor bug: - -offset != offset iff offset == MININT
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llvm-svn: 24522
2005-11-30 01:59:00 +00:00
048b26387b
Represent the encoding of the SPR instructions as they actually are, so
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that we can use the correct SPR numbers in the InstrInfo.td file. This is
necessary to support VRsave.
llvm-svn: 24521
2005-11-29 22:42:50 +00:00
72ab335858
Add more X86 ISel patterns.
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llvm-svn: 24520
2005-11-29 19:38:52 +00:00
c8af0cb893
Better error message when unrecognized opcode is seen.
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llvm-svn: 24519
2005-11-29 18:44:58 +00:00
3e7db9c6d5
Hook up one type, v4f32, to the VR RegisterClass for now.
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llvm-svn: 24517
2005-11-29 08:17:20 +00:00
c138118cdb
Add the remainder of the AltiVec 4 x float instructions. Further
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enhancements will be necessary to teach the code generator that since
there is no fmul, it will have to do vmaddfp, adding +0.0.
llvm-svn: 24516
2005-11-29 08:04:45 +00:00
435b402e1f
Add support for a new STRING and LOCATION node for line number support, patch
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contributed by Daniel Berlin, with a few cleanups here and there by me.
llvm-svn: 24515
2005-11-29 06:21:05 +00:00
4d0251ad55
Add the new vector types to tablegen
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llvm-svn: 24514
2005-11-29 06:19:38 +00:00
9c415364cf
No targets support line number info yet.
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llvm-svn: 24513
2005-11-29 06:16:21 +00:00
5a8726c575
Add support for a new STRING and LOCATION node for line number support, patch
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contributed by Daniel Berlin, with a few cleanups here and there by me.
llvm-svn: 24512
2005-11-29 06:15:39 +00:00
89b049af90
Add the majority of the vector machien value types we expect to support,
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and make a few changes to the legalization machinery to support more than
16 types.
llvm-svn: 24511
2005-11-29 05:45:29 +00:00
1d4af53444
Fixed a comment bug:
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createPPCPatternInstructionSelector -> createPPCISelPattern
llvm-svn: 24510
2005-11-29 04:59:46 +00:00
a31983137a
Add "SCC" to the lexicon. Patch provided by Marco Matthies, thanks!
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llvm-svn: 24509
2005-11-29 01:34:50 +00:00
45edf8a27d
Fix PR670 and test/Regression/Transforms/Mem2Reg/2005-11-28-Crash.ll
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llvm-svn: 24508
2005-11-29 01:07:12 +00:00
7cc680ab79
new testcase for pr670
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llvm-svn: 24507
2005-11-29 01:06:51 +00:00
d8bc778352
add Evan and Jim. Please edit your entries as desired.
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llvm-svn: 24506
2005-11-29 00:57:06 +00:00
c418b5d938
refix typo
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llvm-svn: 24505
2005-11-29 00:42:30 +00:00
7a18a25d33
don't say this is i128, because it isn't yet. Hopefully nate will change
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this to be something sane, but in the mean time it is unused, so safe to
make something bogus.
llvm-svn: 24504
2005-11-29 00:41:40 +00:00
d3bc8cb26d
revert my change for the time being, which broke the build
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llvm-svn: 24503
2005-11-29 00:24:08 +00:00
3e149a2c90
Fixed a punctuation error.
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llvm-svn: 24502
2005-11-28 23:25:41 +00:00
50986909dc
fix a typo :)
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llvm-svn: 24501
2005-11-28 22:42:15 +00:00
d251192910
a few more comments on the interfaces and functions
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llvm-svn: 24500
2005-11-28 18:10:59 +00:00
517caef495
Added documented rsprofiler interface. Also remove new profiler passes, the
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old ones have been updated to implement the interface.
llvm-svn: 24499
2005-11-28 18:00:38 +00:00
62ef23839c
Add the remove() function from the C library.
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llvm-svn: 24498
2005-11-28 15:49:15 +00:00
e8c6277a4f
Teach Visual Studio about new files.
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llvm-svn: 24497
2005-11-28 06:46:36 +00:00
7ff44ec372
Fix VC++ warning.
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llvm-svn: 24496
2005-11-28 06:45:57 +00:00
820c94e467
Add a missed optimization
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llvm-svn: 24495
2005-11-28 04:52:39 +00:00
1f47b25727
Use std:: where appropriate
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llvm-svn: 24494
2005-11-28 02:30:22 +00:00
93e59f6032
Random sampling (aka Arnold and Ryder) profiling. This is still preliminary, but it works on spec on x86 and alpha. The idea is to allow profiling passes to remember what profiling they inserted, then a random sampling framework is inserted which consists of duplicated basic blocks (without profiling), such that at each backedge in the program and entry into every function, the framework chooses whether to use the instrumented code or the instrumentation free code. The goal of such a framework is to make it reasonably cheap to do random sampling of very expensive profiling products (such as load-value profiling).
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The code is organized into 3 parts (2 passes)
1) a linked set of profiling passes, which implement an analysis group (linked, like alias analysis are). These insert profiling into the program, and remember what they inserted, so that at a later time they can be queried about any instruction.
2) a pass that handles inserting the random sampling framework. This also has options to control how random samples are choosen. Currently implemented are Global counters, register allocated global counters, and read cycle counter (see? there was a reason for it).
The profiling passes are almost identical to the existing ones (block, function, and null profiling is supported right now), and they are valid passes without the sampling framework (hence the existing passes can be unified with the new ones, not done yet).
Some things are a bit ugly still, but that should be fixed up soon enough.
Other todo? making the counter values not "magic 2^16 -1" values, but dynamically choosable.
llvm-svn: 24493
2005-11-28 00:58:09 +00:00
11fd6b22b1
Small tweaks noticed while on the plane.
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llvm-svn: 24492
2005-11-26 22:39:34 +00:00
5fc3794e71
since reg2mem requires it, might as well mention that it preserves it
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llvm-svn: 24491
2005-11-25 16:04:54 +00:00
0c88f150c6
add support for dynamic_stackalloc to the dag isel (thanks andrew ;)
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next up: support argument passing in memory, not just registers
llvm-svn: 24490
2005-11-25 07:49:25 +00:00
8492fd30ab
Some first bits of AltiVec stuff: Instruction Formats, Encodings, and
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Registers. Apologies to Jim if the scheduling info so far isn't accurate.
There's a few more things like VRsave support that need to be finished up
in my local tree before I can commit code that Does The Right Thing for
turning 4 x float into the various altivec packed float instructions.
llvm-svn: 24489
2005-11-23 05:29:52 +00:00
061029dee2
Reg2Mem is something a pass may depend on, so allow that
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llvm-svn: 24488
2005-11-22 22:14:23 +00:00
71b09bbb07
turns out, demotion and invokes and critical edges don't mix
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llvm-svn: 24487
2005-11-22 21:45:19 +00:00
d6a0308470
Fix warning, the better way. Really, this is what this instruction is for, so use it
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llvm-svn: 24486
2005-11-22 20:59:00 +00:00
03390557fa
Fix warning
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llvm-svn: 24485
2005-11-22 20:56:05 +00:00
d37c13154a
Check in code to scalarize arbitrarily wide packed types for some simple
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vector operations (load, add, sub, mul).
This allows us to codegen:
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = add <4 x float> %tmp1, %tmp1
store <4 x float> %tmp2, <4 x float> *%a
ret void
}
on ppc as:
_foo:
lfs f0, 12(r3)
lfs f1, 8(r3)
lfs f2, 4(r3)
lfs f3, 0(r3)
fadds f0, f0, f0
fadds f1, f1, f1
fadds f2, f2, f2
fadds f3, f3, f3
stfs f0, 12(r3)
stfs f1, 8(r3)
stfs f2, 4(r3)
stfs f3, 0(r3)
blr
llvm-svn: 24484
2005-11-22 18:16:00 +00:00
0294e33ea4
massive DAGISel patch. lots and lots more stuff compiles now
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llvm-svn: 24483
2005-11-22 04:20:06 +00:00
07890bbec4
Rather than attempting to legalize 1 x float, make sure the SD ISel never
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generates it. Make MVT::Vector expand-only, and remove the code in
Legalize that attempts to legalize it.
The plan for supporting N x Type is to continually epxand it in ExpandOp
until it gets down to 2 x Type, where it will be scalarized into a pair of
scalars.
llvm-svn: 24482
2005-11-22 01:29:36 +00:00
ac6cb46429
Use HasDotTypeDotSizeDirective instead of forELF
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llvm-svn: 24481
2005-11-21 23:06:54 +00:00
629d09757e
Add a new flag
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llvm-svn: 24480
2005-11-21 23:06:08 +00:00
78161dbc84
Remove a level of indentation by using a continue.
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llvm-svn: 24479
2005-11-21 22:48:18 +00:00
40f8c8450d
Simplify the subtarget info, allow the asmwriter to do some target sensing
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based on TargetType.
llvm-svn: 24478
2005-11-21 22:43:58 +00:00
99be8f766f
Use subtarget information computed by X86Subtarget instead of rolling our own.
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llvm-svn: 24477
2005-11-21 22:39:40 +00:00
3eb876117a
Make the X86 subtarget compute the basic target type: ELF, Cygwin, Darwin,
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or native Win32
llvm-svn: 24476
2005-11-21 22:31:58 +00:00
ebc39f5a9c
Add a forELF flag, allowing the removal of forCygwin and simplification of
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conditionals.
llvm-svn: 24475
2005-11-21 22:19:48 +00:00
505ee2b886
Add some more directives
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llvm-svn: 24474
2005-11-21 19:51:51 +00:00
Evan Cheng