09b2c4aee8
AMDGPU: Remove legacy rsq.clamped intrinsic
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Mesa still has a use of llvm.AMDGPU.rsq.f64 remaining.
Also fix mismatch with non-IEEE rsq selecting to IEEE rsq.
llvm-svn: 275617
2016-07-15 21:26:52 +00:00
ca7f5701f8
AMDGPU/R600: Delete/rename intrinsics no longer used by mesa
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Use the replacement pass to update the tests, and delete old names.
llvm-svn: 275375
2016-07-14 05:47:17 +00:00
648e422bd9
AMDGPU/R600: Remove intrinsics with no tests and no users
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Mesa removed this path, so nothing is using these anymore.
llvm-svn: 275372
2016-07-14 05:23:23 +00:00
2fa28c330c
AMDGPU/R600: Add implicitarg.ptr intrinsic
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Differential Revision: http://reviews.llvm.org/D21622
llvm-svn: 275024
2016-07-10 21:20:29 +00:00
4a105d73a9
AMDGPU/R600: Add PatFrags for selecting the correct vtx id for loads
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This moves of the r600 logic out of isGlobalLoad() and into the
TableGen files.
Differential Revision: http://reviews.llvm.org/D21710
llvm-svn: 274527
2016-07-05 00:12:51 +00:00
991dfd7b07
AMDGPU/R600: Add indentation to VTX and TEX fetch asm strings
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These are printed as part of Fetch clauses.
Differential Revision: http://reviews.llvm.org/D21730
llvm-svn: 274517
2016-07-04 19:45:00 +00:00
43e92fe306
AMDGPU: Cleanup subtarget handling.
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Split AMDGPUSubtarget into amdgcn/r600 specific subclasses.
This removes most of the static_casting of the basic codegen
classes everywhere, and tries to restrict the features
visible on the wrong target.
llvm-svn: 273652
2016-06-24 06:30:11 +00:00
9babdf4265
AMDGPU: Fix verifier errors in SILowerControlFlow
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The main sin this was committing was using terminator
instructions in the middle of the block, and then
not updating the block successors / predecessors.
Split the blocks up to avoid this and introduce new
pseudo instructions for branches taken with exec masking.
Also use a pseudo instead of emitting s_endpgm and erasing
it in the special case of a non-void return.
llvm-svn: 273467
2016-06-22 20:15:28 +00:00
f97de00745
AMDGPU/R600: Implement memory loads from constant AS
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Reviewers: tstellard
Subscribers: arsenm
Differential Revision: http://reviews.llvm.org/D19792
llvm-svn: 269479
2016-05-13 20:39:29 +00:00
79963e80b8
AMDGPU: Rename intrinsic to better match instruction name
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Also fixes missing f32 test.
llvm-svn: 260780
2016-02-13 01:03:00 +00:00
295875efda
AMDGPU: Remove 24-bit intrinsics
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The known bit matching code seems to work reasonably well,
so these shouldn't really be needed.
llvm-svn: 259180
2016-01-29 10:05:16 +00:00
7713162c32
AMDGPU: Remove more unused intrinsics
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Replace tests with lrp with basic IR expansion
llvm-svn: 258612
2016-01-23 05:42:38 +00:00
ee0930821a
AMDGPU: Remove random TGSI intrinsic
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I don't think this was ever used.
llvm-svn: 258514
2016-01-22 18:42:44 +00:00
0cbaa1762b
AMDGPU: Remove AMDGPU.fract intrinsic
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Mesa doesn't use this, and this is pattern matched already
from fsub x, (ffloor x)
llvm-svn: 258513
2016-01-22 18:42:38 +00:00
e9ffb45b60
Fix typos.
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Summary: This fixes a variety of typos in docs, code and headers.
Subscribers: jholewinski, sanjoy, arsenm, llvm-commits
Differential Revision: http://reviews.llvm.org/D12626
llvm-svn: 247495
2015-09-12 01:17:08 +00:00
45bb48ea19
R600 -> AMDGPU rename
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llvm-svn: 239657
2015-06-13 03:28:10 +00:00
1be1aa84ec
Revert "AMDGPU: Add core backend files for R600/SI codegen v6"
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This reverts commit 4ea70107c5e51230e9e60f0bf58a0f74aa4885ea.
llvm-svn: 160303
2012-07-16 18:19:53 +00:00
bcce80fa95
AMDGPU: Add core backend files for R600/SI codegen v6
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llvm-svn: 160270
2012-07-16 14:17:08 +00:00
Matt Arsenault