2ac3386ef3
Revert "For ARM stack frames that utilize variable sized objects and have either", it is breaking oggenc with Clang for ARMv6.
...
This reverts commit 8d6e29cfda270be483abf638850311670829ee65.
llvm-svn: 112962
2010-09-03 15:26:42 +00:00
24d039ebe3
test/CodeGen/X86: Add explicit -mtriple=(i686|x86_64)-linux for Win32 host.
...
llvm-svn: 112947
2010-09-03 03:24:08 +00:00
d6634a5b2e
AVX doesn't support mm operations neither its instrinsics.
...
The AVX versions of PALIGN and PABS* should only exist for
128-bit. Remove the unnecessary stuff.
llvm-svn: 112944
2010-09-03 02:08:45 +00:00
f65c9ef720
Replace NEON vabdl, vaba, and vabal intrinsics with combinations of the
...
vabd intrinsic and add and/or zext operations. In the case of vaba, this
also avoids the need for a DAG combine pattern to combine vabd with add.
Update tests. Auto-upgrade the old intrinsics.
llvm-svn: 112941
2010-09-03 01:35:08 +00:00
7bf4b82e97
update one more test
...
llvm-svn: 112910
2010-09-02 23:32:55 +00:00
7f2f0930a7
add a new "llvm-dis -show-annotations" option, which causes it to print
...
#uses comments, with a testcase.
llvm-svn: 112906
2010-09-02 23:21:44 +00:00
a5a645559c
Properly emit __chkstk call instead of __alloca on non-mingw windows targets.
...
Patch by Cameron Esfahani!
llvm-svn: 112902
2010-09-02 23:03:46 +00:00
65fb25a257
more test cleanup
...
llvm-svn: 112892
2010-09-02 22:38:56 +00:00
bb451461ec
remove some noise from tests.
...
llvm-svn: 112889
2010-09-02 22:35:33 +00:00
a18d7ec4fb
we are past the point where these tests are useful.
...
llvm-svn: 112887
2010-09-02 22:32:02 +00:00
7fd9aea67c
For ARM stack frames that utilize variable sized objects and have either
...
large local stack areas or require dynamic stack realignment, allocate a
base register via which to access the local frame. This allows efficient
access to frame indices not accessible via the FP (either due to being out
of range or due to dynamic realignment) or the SP (due to variable sized
object allocation). In particular, this greatly improves efficiency of access
to spill slots in Thumb functions which contain VLAs.
rdar://7352504
rdar://8374540
rdar://8355680
llvm-svn: 112883
2010-09-02 22:29:01 +00:00
affc0e42f0
fix more AST updating bugs, correcting miscompilation in PR8041
...
llvm-svn: 112878
2010-09-02 22:19:10 +00:00
3c9b5f394b
Don't narrow the load and store in a load+twiddle+store sequence unless
...
there are clearly no stores between the load and the store. This fixes
this miscompile reported as PR7833.
This breaks the test/CodeGen/X86/narrow_op-2.ll optimization, which is
safe, but awkward to prove safe. Move it to X86's README.txt.
llvm-svn: 112861
2010-09-02 21:18:42 +00:00
0ca17f7e8a
Fix an unnecessary XFAIL
...
llvm-svn: 112853
2010-09-02 20:19:24 +00:00
67dee4dcac
Fix typo. I accidentally edited the wrong file before my last commit.
...
llvm-svn: 112851
2010-09-02 19:52:06 +00:00
e39017cb97
Add AsmParser support for the ELF .previous directive. Patch by Roman Divacky.
...
llvm-svn: 112849
2010-09-02 18:53:37 +00:00
a8c896b704
Fix a bug in LazyValueInfo that CorrelatedValuePropagation exposed: In the LVI lattice, undef and the full set ConstantRange should not
...
be treated as equivalent.
llvm-svn: 112843
2010-09-02 18:23:58 +00:00
66c681a644
Now that register allocation properly considers reserved regs, simplify the
...
ARM register class allocation order functions to take advantage of that.
llvm-svn: 112841
2010-09-02 18:14:29 +00:00
75a6408f88
Convert VLD1 and VLD2 instructions to use pseudo-instructions until
...
after regalloc.
llvm-svn: 112825
2010-09-02 16:00:54 +00:00
8dda07428a
Print the number of uses of a function in the .ll since it can be informative
...
and there seems to be no reason not to.
llvm-svn: 112812
2010-09-02 08:52:23 +00:00
a224e5563e
test/loop-strength-reduce4: Add explicit triplet for Win32 host.
...
llvm-svn: 112802
2010-09-02 03:45:58 +00:00
54ce546865
test/twoaddr-coalesce: Do not use @main .
...
Win32 codegen emits implicit invoking __main into, to fail.
llvm-svn: 112801
2010-09-02 03:45:51 +00:00
38ab35a911
Remove NEON vmull, vmlal, and vmlsl intrinsics, replacing them with multiply,
...
add, and subtract operations with zero-extended or sign-extended vectors.
Update tests. Add auto-upgrade support for the old intrinsics.
llvm-svn: 112773
2010-09-01 23:50:19 +00:00
8af45a889d
deepen my MMX/SRoA hack to avoid hurting non-x86 codegen.
...
llvm-svn: 112763
2010-09-01 23:09:27 +00:00
fea81b4831
Using target specific nodes for shuffle nodes makes the mask
...
check more strict, breaking some cases not checked in the
testsuite, but also exposes some foldings not done before,
as this example:
movaps (%rdi), %xmm0
movaps (%rax), %xmm1
movaps %xmm0, %xmm2
movss %xmm1, %xmm2
shufps $36, %xmm2, %xmm0
now is generated as:
movaps (%rdi), %xmm0
movaps %xmm0, %xmm1
movlps (%rax), %xmm1
shufps $36, %xmm1, %xmm0
llvm-svn: 112753
2010-09-01 22:33:20 +00:00
4b6fd48bba
Teach RemoveCopyByCommutingDef to check all aliases, not just subregisters.
...
This caused a miscompilation in WebKit where %RAX had conflicting defs when
RemoveCopyByCommutingDef was commuting a %EAX use.
llvm-svn: 112751
2010-09-01 22:15:35 +00:00
78d95e0089
Apparently only Darwin passes long double misaligned. Compensate.
...
llvm-svn: 112748
2010-09-01 21:57:20 +00:00
0ad7d9c24e
Fix loop unswitching's assumption that a code path which either
...
infinite loops or exits will eventually exit. This fixes PR5373.
llvm-svn: 112745
2010-09-01 21:46:45 +00:00
6456efaffd
The output of opt -stats must be sent to stderr. Patch by NAKAMURA Takumi!
...
llvm-svn: 112724
2010-09-01 18:32:56 +00:00
39eccb4754
temporarily revert r112664, it is causing a decoding conflict, and
...
the testcases should be merged.
llvm-svn: 112711
2010-09-01 16:00:50 +00:00
d8e5dfccc1
COFF: Update tests to reflect changes in last commit.
...
llvm-svn: 112704
2010-09-01 14:15:31 +00:00
e13c04d6da
Attempt to fix buildbot.
...
llvm-svn: 112697
2010-09-01 05:19:06 +00:00
34e5361eb5
add a gross hack to work around a problem that Argiris reported
...
on llvmdev: SRoA is introducing MMX datatypes like <1 x i64>,
which then cause random problems because the X86 backend is
producing mmx stuff without inserting proper emms calls.
In the short term, force off MMX datatypes. In the long term,
the X86 backend should not select generic vector types to MMX
registers. This is being worked on, but won't be done in time
for 2.8. rdar://8380055
llvm-svn: 112696
2010-09-01 05:14:33 +00:00
b9ed4f252f
filecheckize
...
llvm-svn: 112695
2010-09-01 05:10:14 +00:00
110ed64fbb
Revert 112442 and 112440 until the compile time problems introduced
...
by 112440 are resolved.
llvm-svn: 112692
2010-09-01 01:45:53 +00:00
52bd0dc3bb
Testcase for llvm checkin 112674.
...
llvm-svn: 112675
2010-08-31 23:43:55 +00:00
030f02021b
licm is wasting time hoisting constant foldable operations,
...
instead of hoisting them, just fold them away. This occurs in the
testcase for PR8041, for example.
llvm-svn: 112669
2010-08-31 23:00:16 +00:00
6789f8b6ae
We have a chance for an optimization. Consider this code:
...
int x(int t) {
if (t & 256)
return -26;
return 0;
}
We generate this:
tst.w r0, #256
mvn r0, #25
it eq
moveq r0, #0
while gcc generates this:
ands r0, r0, #256
it ne
mvnne r0, #25
bx lr
Scandalous really!
During ISel time, we can look for this particular pattern. One where we have a
"MOVCC" that uses the flag off of a CMPZ that itself is comparing an AND
instruction to 0. Something like this (greatly simplified):
%r0 = ISD::AND ...
ARMISD::CMPZ %r0, 0 @ sets [CPSR]
%r0 = ARMISD::MOVCC 0, -26 @ reads [CPSR]
All we have to do is convert the "ISD::AND" into an "ARM::ANDS" that sets [CPSR]
when it's zero. The zero value will all ready be in the %r0 register and we only
need to change it if the AND wasn't zero. Easy!
llvm-svn: 112664
2010-08-31 22:41:22 +00:00
86ec8b3a3f
Reapply r112623. Included additional check for unused byval argument.
...
llvm-svn: 112659
2010-08-31 22:22:42 +00:00
a5e6b3eca4
Merge 2010-08-31-InfiniteRecursion.ll into crash.ll.
...
llvm-svn: 112635
2010-08-31 20:27:17 +00:00
529f248eb4
Revert r112623. It is causing self host build failures.
...
llvm-svn: 112631
2010-08-31 19:41:03 +00:00
8559932d36
Remember byval argument's frame index during argument lowering and use this info to emit debug info.
...
Fixes Radar 8367011.
llvm-svn: 112623
2010-08-31 18:50:09 +00:00
799a08ae48
Add a test for the duplicated-conditional situation illutrated by PR5652.
...
llvm-svn: 112621
2010-08-31 18:49:12 +00:00
e2295f1c80
merge two tests.
...
llvm-svn: 112617
2010-08-31 18:44:03 +00:00
3931c85956
Manually reduce this testcase.
...
llvm-svn: 112615
2010-08-31 18:16:29 +00:00
fbcd165b59
merge two tests and convert to filecheck.
...
llvm-svn: 112613
2010-08-31 18:05:08 +00:00
ada0623725
Add a micro-test for the transforms I added to JumpThreading.
...
I have not been able to find a way to test each in isolation, for a few reasons:
1) The ability to look-through non-i1 BinaryOperator's requires the ability to look through non-constant
ICmps in order for it to ever trigger.
2) The ability to do LVI-powered PHI value determination only matters in cases that ProcessBranchOnPHI
can't handle. Since it already handles all the cases without other instructions in the def-use chain
between the PHI and the branch, it requires the ability to look through ICmps and/or BinaryOperators
as well.
llvm-svn: 112611
2010-08-31 17:59:07 +00:00
ad9b6de3b6
Update test for 112609
...
llvm-svn: 112610
2010-08-31 17:58:47 +00:00
064b139c8d
Rename test directory to reflect new pass name.
...
llvm-svn: 112592
2010-08-31 07:50:31 +00:00
48d58ad64c
Rename ValuePropagation to a more descriptive CorrelatedValuePropagation.
...
llvm-svn: 112591
2010-08-31 07:48:34 +00:00
3997a07fb9
More Chris-inspired JumpThreading fixes: use ConstantExpr to correctly constant-fold undef, and be more careful with its return value.
...
This actually exposed an infinite recursion bug in ComputeValueKnownInPredecessors which theoretically already existed (in JumpThreading's
handling of and/or of i1's), but never manifested before. This patch adds a tracking set to prevent this case.
llvm-svn: 112589
2010-08-31 07:36:34 +00:00
376597c13e
Remove r111665, which implemented store-narrowing in InstCombine. Chris discovered a miscompilation in it, and it's not easily
...
fixable at the optimizer level. I'll investigate reimplementing it in DAGCombine.
llvm-svn: 112575
2010-08-31 04:41:06 +00:00
3a1d87a7ba
Fix borken test
...
llvm-svn: 112555
2010-08-30 23:41:49 +00:00
70b17c50e2
Combine these two tests, and make sure there's a newline at the end of the file.
...
llvm-svn: 112554
2010-08-30 23:37:41 +00:00
4cd8a126c3
Remove NEON vmovn intrinsic, replacing it with vector truncate operations.
...
Auto-upgrade the old intrinsic and update tests.
llvm-svn: 112507
2010-08-30 20:02:30 +00:00
34bfab0ad5
two changes:
...
1) nuke ConstDataCoalSection, which is dead.
2) revise my previous patch for rdar://8018335,
which was completely wrong. Specifically, it doesn't
make sense to mark __TEXT,__const_coal as PURE_INSTRUCTIONS,
because it is for readonly data. templates (it turns out)
go to const_coal_nt. The real fix for rdar://8018335 was
to give ConstTextCoalSection a section kind of ReadOnly
instead of Text.
llvm-svn: 112496
2010-08-30 18:12:35 +00:00
2f997cdedf
Partially revert r112480. Caused test failures.
...
llvm-svn: 112486
2010-08-30 15:34:08 +00:00
e53cf6f85d
coff-dump.py: Fix PR7996. Now it is compatible to Python-2.4.
...
llvm-svn: 112485
2010-08-30 15:19:56 +00:00
7983340465
Fix constant-over-index.ll test on windows.
...
llvm-svn: 112483
2010-08-30 15:08:02 +00:00
41c18853c8
Test: Fix LLVMC tests on CMake.
...
The CMake build didn't define TEST_COMPILE_CXX_CMD. The tests assumed gcc.
llvm-svn: 112480
2010-08-30 14:49:00 +00:00
68c30907cc
Correct bogus module triple specifications.
...
llvm-svn: 112469
2010-08-30 10:48:29 +00:00
263f804699
LICM does get dead instructions input to it. Instead of sinking them
...
out of loops, just delete them.
llvm-svn: 112451
2010-08-29 18:22:25 +00:00
3a08ed7904
Make IVUsers iterative instead of recursive.
...
This has the side effect of reversing the order of most of
IVUser's results.
llvm-svn: 112442
2010-08-29 16:40:03 +00:00
6665550bca
Make this test less dependent on register allocation choices.
...
llvm-svn: 112426
2010-08-29 14:49:42 +00:00
883fa863f8
Use exec.
...
llvm-svn: 112425
2010-08-29 14:49:00 +00:00
1e616572d9
Fix lowering of INSERT_VECTOR_ELT in SPU.
...
The IDX was treated as byte index, not element index.
llvm-svn: 112422
2010-08-29 12:41:50 +00:00
d0c054886c
Remove NEON vaddl, vaddw, vsubl, and vsubw intrinsics. Instead, use llvm
...
IR add/sub operations with one or both operands sign- or zero-extended.
Auto-upgrade the old intrinsics.
llvm-svn: 112416
2010-08-29 05:57:34 +00:00
c2887bc283
merge a bunch of shuffle tests into sse2.ll
...
llvm-svn: 112398
2010-08-29 03:19:04 +00:00
b1ff978406
add some nounwind's
...
llvm-svn: 112396
2010-08-29 03:07:47 +00:00
112b6ee3f2
fixme accomplished
...
llvm-svn: 112386
2010-08-28 20:40:28 +00:00
94656b1c8c
fix the buildvector->insertp[sd] logic to not always create a redundant
...
insertp[sd] $0, which is a noop. Before:
_f32: ## @f32
pshufd $1, %xmm1, %xmm2
pshufd $1, %xmm0, %xmm3
addss %xmm2, %xmm3
addss %xmm1, %xmm0
## kill: XMM0<def> XMM0<kill> XMM0<def>
insertps $0, %xmm0, %xmm0
insertps $16, %xmm3, %xmm0
ret
after:
_f32: ## @f32
movdqa %xmm0, %xmm2
addss %xmm1, %xmm2
pshufd $1, %xmm1, %xmm1
pshufd $1, %xmm0, %xmm3
addss %xmm1, %xmm3
movdqa %xmm2, %xmm0
insertps $16, %xmm3, %xmm0
ret
The extra movs are due to a random (poor) scheduling decision.
llvm-svn: 112379
2010-08-28 17:59:08 +00:00
bcb6090ad0
fix the BuildVector -> unpcklps logic to not do pointless shuffles
...
when the top elements of a vector are undefined. This happens all
the time for X86-64 ABI stuff because only the low 2 elements of
a 4 element vector are defined. For example, on:
_Complex float f32(_Complex float A, _Complex float B) {
return A+B;
}
We used to produce (with SSE2, SSE4.1+ uses insertps):
_f32: ## @f32
movdqa %xmm0, %xmm2
addss %xmm1, %xmm2
pshufd $16, %xmm2, %xmm2
pshufd $1, %xmm1, %xmm1
pshufd $1, %xmm0, %xmm0
addss %xmm1, %xmm0
pshufd $16, %xmm0, %xmm1
movdqa %xmm2, %xmm0
unpcklps %xmm1, %xmm0
ret
We now produce:
_f32: ## @f32
movdqa %xmm0, %xmm2
addss %xmm1, %xmm2
pshufd $1, %xmm1, %xmm1
pshufd $1, %xmm0, %xmm3
addss %xmm1, %xmm3
movaps %xmm2, %xmm0
unpcklps %xmm3, %xmm0
ret
This implements rdar://8368414
llvm-svn: 112378
2010-08-28 17:28:30 +00:00
2e5c14713c
Update ocaml test.
...
llvm-svn: 112364
2010-08-28 10:29:41 +00:00
13ee795c42
remove unions from LLVM IR. They are severely buggy and not
...
being actively maintained, improved, or extended.
llvm-svn: 112356
2010-08-28 04:09:24 +00:00
504e5100d3
remove the ABCD and SSI passes. They don't have any clients that
...
I'm aware of, aren't maintained, and LVI will be replacing their value.
nlewycky approved this on irc.
llvm-svn: 112355
2010-08-28 03:51:24 +00:00
d0214f3efe
handle the constant case of vector insertion. For something
...
like this:
struct S { float A, B, C, D; };
struct S g;
struct S bar() {
struct S A = g;
++A.B;
A.A = 42;
return A;
}
we now generate:
_bar: ## @bar
## BB#0: ## %entry
movq _g@GOTPCREL(%rip), %rax
movss 12(%rax), %xmm0
pshufd $16, %xmm0, %xmm0
movss 4(%rax), %xmm2
movss 8(%rax), %xmm1
pshufd $16, %xmm1, %xmm1
unpcklps %xmm0, %xmm1
addss LCPI1_0(%rip), %xmm2
pshufd $16, %xmm2, %xmm2
movss LCPI1_1(%rip), %xmm0
pshufd $16, %xmm0, %xmm0
unpcklps %xmm2, %xmm0
ret
instead of:
_bar: ## @bar
## BB#0: ## %entry
movq _g@GOTPCREL(%rip), %rax
movss 12(%rax), %xmm0
pshufd $16, %xmm0, %xmm0
movss 4(%rax), %xmm2
movss 8(%rax), %xmm1
pshufd $16, %xmm1, %xmm1
unpcklps %xmm0, %xmm1
addss LCPI1_0(%rip), %xmm2
movd %xmm2, %eax
shlq $32, %rax
addq $1109917696, %rax ## imm = 0x42280000
movd %rax, %xmm0
ret
llvm-svn: 112345
2010-08-28 01:50:57 +00:00
dd6601048e
optimize bitcasts from large integers to vector into vector
...
element insertion from the pieces that feed into the vector.
This handles a pattern that occurs frequently due to code
generated for the x86-64 abi. We now compile something like
this:
struct S { float A, B, C, D; };
struct S g;
struct S bar() {
struct S A = g;
++A.A;
++A.C;
return A;
}
into all nice vector operations:
_bar: ## @bar
## BB#0: ## %entry
movq _g@GOTPCREL(%rip), %rax
movss LCPI1_0(%rip), %xmm1
movss (%rax), %xmm0
addss %xmm1, %xmm0
pshufd $16, %xmm0, %xmm0
movss 4(%rax), %xmm2
movss 12(%rax), %xmm3
pshufd $16, %xmm2, %xmm2
unpcklps %xmm2, %xmm0
addss 8(%rax), %xmm1
pshufd $16, %xmm1, %xmm1
pshufd $16, %xmm3, %xmm2
unpcklps %xmm2, %xmm1
ret
instead of icky integer operations:
_bar: ## @bar
movq _g@GOTPCREL(%rip), %rax
movss LCPI1_0(%rip), %xmm1
movss (%rax), %xmm0
addss %xmm1, %xmm0
movd %xmm0, %ecx
movl 4(%rax), %edx
movl 12(%rax), %esi
shlq $32, %rdx
addq %rcx, %rdx
movd %rdx, %xmm0
addss 8(%rax), %xmm1
movd %xmm1, %eax
shlq $32, %rsi
addq %rax, %rsi
movd %rsi, %xmm1
ret
This resolves rdar://8360454
llvm-svn: 112343
2010-08-28 01:20:38 +00:00
e06905d1f0
Completely disable tail calls when fast-isel is enabled, as fast-isel
...
doesn't currently support dealing with this.
llvm-svn: 112341
2010-08-28 00:51:03 +00:00
cf7f941121
Add a prototype of a new peephole optimizing pass that uses LazyValue info to simplify PHIs and select's.
...
This pass addresses the missed optimizations from PR2581 and PR4420.
llvm-svn: 112325
2010-08-27 23:31:36 +00:00
13ce07fa92
Change ARM VFP VLDM/VSTM instructions to use addressing mode #4 , just like
...
all the other LDM/STM instructions. This fixes asm printer crashes when
compiling with -O0. I've changed one of the NEON tests (vst3.ll) to run
with -O0 to check this in the future.
Prior to this change VLDM/VSTM used addressing mode #5 , but not really.
The offset field was used to hold a count of the number of registers being
loaded or stored, and the AM5 opcode field was expanded to specify the IA
or DB mode, instead of the standard ADD/SUB specifier. Much of the backend
was not aware of these special cases. The crashes occured when rewriting
a frameindex caused the AM5 offset field to be changed so that it did not
have a valid submode. I don't know exactly what changed to expose this now.
Maybe we've never done much with -O0 and NEON. Regardless, there's no longer
any reason to keep a count of the VLDM/VSTM registers, so we can use
addressing mode #4 and clean things up in a lot of places.
llvm-svn: 112322
2010-08-27 23:18:17 +00:00
954e9557e3
tidy up test.
...
llvm-svn: 112321
2010-08-27 23:15:21 +00:00
b8b7d52631
no really, fix the test.
...
llvm-svn: 112317
2010-08-27 23:05:54 +00:00
c8908b4cdb
fix this test. It's not clear what it's really testing.
...
llvm-svn: 112316
2010-08-27 23:05:27 +00:00
6c1395f62a
Enhance the shift propagator to handle the case when you have:
...
A = shl x, 42
...
B = lshr ..., 38
which can be transformed into:
A = shl x, 4
...
iff we can prove that the would-be-shifted-in bits
are already zero. This eliminates two shifts in the testcase
and allows eliminate of the whole i128 chain in the real example.
llvm-svn: 112314
2010-08-27 22:53:44 +00:00
18d7fc8fc6
Implement a pretty general logical shift propagation
...
framework, which is good at ripping through bitfield
operations. This generalize a bunch of the existing
xforms that instcombine does, such as
(x << c) >> c -> and
to handle intermediate logical nodes. This is useful for
ripping up the "promote to large integer" code produced by
SRoA.
llvm-svn: 112304
2010-08-27 22:24:38 +00:00
606b76eba6
merge and filecheckize test
...
llvm-svn: 112289
2010-08-27 20:44:45 +00:00
c665156e9f
merge two tests
...
llvm-svn: 112288
2010-08-27 20:42:10 +00:00
7398434675
teach the truncation optimization that an entire chain of
...
computation can be truncated if it is fed by a sext/zext that doesn't
have to be exactly equal to the truncation result type.
llvm-svn: 112285
2010-08-27 20:32:06 +00:00
7413e87b6d
get this test passing on linux builders.
...
llvm-svn: 112280
2010-08-27 18:49:08 +00:00
90cd746e63
Add an instcombine to clean up a common pattern produced
...
by the SRoA "promote to large integer" code, eliminating
some type conversions like this:
%94 = zext i16 %93 to i32 ; <i32> [#uses=2]
%96 = lshr i32 %94, 8 ; <i32> [#uses=1]
%101 = trunc i32 %96 to i8 ; <i8> [#uses=1]
This also unblocks other xforms from happening, now clang is able to compile:
struct S { float A, B, C, D; };
float foo(struct S A) { return A.A + A.B+A.C+A.D; }
into:
_foo: ## @foo
## BB#0: ## %entry
pshufd $1, %xmm0, %xmm2
addss %xmm0, %xmm2
movdqa %xmm1, %xmm3
addss %xmm2, %xmm3
pshufd $1, %xmm1, %xmm0
addss %xmm3, %xmm0
ret
on x86-64, instead of:
_foo: ## @foo
## BB#0: ## %entry
movd %xmm0, %rax
shrq $32, %rax
movd %eax, %xmm2
addss %xmm0, %xmm2
movapd %xmm1, %xmm3
addss %xmm2, %xmm3
movd %xmm1, %rax
shrq $32, %rax
movd %eax, %xmm0
addss %xmm3, %xmm0
ret
This seems pretty close to optimal to me, at least without
using horizontal adds. This also triggers in lots of other
code, including SPEC.
llvm-svn: 112278
2010-08-27 18:31:05 +00:00
edf722add3
Add alignment arguments to all the NEON load/store intrinsics.
...
Update all the tests using those intrinsics and add support for
auto-upgrading bitcode files with the old versions of the intrinsics.
llvm-svn: 112271
2010-08-27 17:13:24 +00:00
6ebbd92380
Use LVI to eliminate conditional branches where we've tested a related condition previously. Update tests for this change.
...
This fixes PR5652.
llvm-svn: 112270
2010-08-27 17:12:29 +00:00
1844a71e66
X86: Fix an encoding issue with LOCK_ADD64mr, which could lead to very hard to find miscompiles with the integrated assembler.
...
llvm-svn: 112250
2010-08-27 01:30:14 +00:00
c188b96bbe
filecheckize
...
llvm-svn: 112235
2010-08-26 22:23:39 +00:00
387d6bcdcb
rename test.
...
llvm-svn: 112234
2010-08-26 22:20:47 +00:00
bfd2228182
optimize "integer extraction out of the middle of a vector" as produced
...
by SRoA. This is part of rdar://7892780, but needs another xform to
expose this.
llvm-svn: 112232
2010-08-26 22:14:59 +00:00
d4ebd6df5a
optimize bitcast(trunc(bitcast(x))) where the result is a float and 'x'
...
is a vector to be a vector element extraction. This allows clang to
compile:
struct S { float A, B, C, D; };
float foo(struct S A) { return A.A + A.B+A.C+A.D; }
into:
_foo: ## @foo
## BB#0: ## %entry
movd %xmm0, %rax
shrq $32, %rax
movd %eax, %xmm2
addss %xmm0, %xmm2
movapd %xmm1, %xmm3
addss %xmm2, %xmm3
movd %xmm1, %rax
shrq $32, %rax
movd %eax, %xmm0
addss %xmm3, %xmm0
ret
instead of:
_foo: ## @foo
## BB#0: ## %entry
movd %xmm0, %rax
movd %eax, %xmm0
shrq $32, %rax
movd %eax, %xmm2
addss %xmm0, %xmm2
movd %xmm1, %rax
movd %eax, %xmm1
addss %xmm2, %xmm1
shrq $32, %rax
movd %eax, %xmm0
addss %xmm1, %xmm0
ret
... eliminating half of the horribleness.
llvm-svn: 112227
2010-08-26 21:55:42 +00:00
3c19d3d5c3
filecheckize
...
llvm-svn: 112225
2010-08-26 21:51:41 +00:00
7717c616bd
rename test
...
llvm-svn: 112224
2010-08-26 21:50:56 +00:00
bd2ecc7e68
Make JumpThreading smart enough to properly thread StrSwitch when it's compiled with clang++.
...
llvm-svn: 112198
2010-08-26 17:40:24 +00:00
ca26f79051
Reapply r112091 and r111922, support for metadata linking, with a
...
fix: add a flag to MapValue and friends which indicates whether
any module-level mappings are being made. In the common case of
inlining, no module-level mappings are needed, so MapValue doesn't
need to examine non-function-local metadata, which can be very
expensive in the case of a large module with really deep metadata
(e.g. a large C++ program compiled with -g).
This flag is a little awkward; perhaps eventually it can be moved
into the ClonedCodeInfo class.
llvm-svn: 112190
2010-08-26 15:41:53 +00:00
af23e9a798
Add a hackaround for PR7993 which is causing failures on x86 builders that lack sse2.
...
llvm-svn: 112175
2010-08-26 06:57:07 +00:00
66afba7aa4
I think enough general codegen bugs are fixed to allow this to work
...
on random hosts, lets see!
llvm-svn: 112172
2010-08-26 05:52:42 +00:00
eb2cc0ce0e
implement SplitVecOp_CONCAT_VECTORS, fixing the included testcase with SSE1.
...
llvm-svn: 112171
2010-08-26 05:51:22 +00:00
825294b85f
Make sure this forces the x86 targets
...
llvm-svn: 112169
2010-08-26 05:25:05 +00:00
cc60609cb4
fix sse1 only codegen in x86-64 mode, which is something we
...
apparently try to support.
llvm-svn: 112168
2010-08-26 05:24:29 +00:00
95fe13c720
Revert r112091, "Remap metadata attached to instructions when remapping
...
individual ...", which depends on r111922, which I am reverting.
llvm-svn: 112157
2010-08-26 03:48:08 +00:00
08da771ec3
Enable pre-RA virtual frame base register allocation. rdar://8277890
...
llvm-svn: 112127
2010-08-26 00:58:06 +00:00
4629f423f8
Revert svn 107892 (with changes to work with trunk). It caused a crash if
...
a VLD result was not used (Radar 8355607). It should also fix pr7988, but
I haven't verified that yet.
llvm-svn: 112118
2010-08-26 00:13:36 +00:00
c7fb446a9d
temporarily disable this, which started failing on the llvm-i686-linux
...
builder. I will investigate tonight.
llvm-svn: 112113
2010-08-25 23:43:14 +00:00
75ff053497
Change handling of illegal vector types to widen when possible instead of
...
expanding: e.g. <2 x float> -> <4 x float> instead of -> 2 floats. This
affects two places in the code: handling cross block values and handling
function return and arguments. Since vectors are already widened by
legalizetypes, this gives us much better code and unblocks x86-64 abi
and SPU abi work.
For example, this (which is a silly example of a cross-block value):
define <4 x float> @test2(<4 x float> %A) nounwind {
%B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1>
%C = fadd <2 x float> %B, %B
br label %BB
BB:
%D = fadd <2 x float> %C, %C
%E = shufflevector <2 x float> %D, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
ret <4 x float> %E
}
Now compiles into:
_test2: ## @test2
## BB#0:
addps %xmm0, %xmm0
addps %xmm0, %xmm0
ret
previously it compiled into:
_test2: ## @test2
## BB#0:
addps %xmm0, %xmm0
pshufd $1, %xmm0, %xmm1
## kill: XMM0<def> XMM0<kill> XMM0<def>
insertps $0, %xmm0, %xmm0
insertps $16, %xmm1, %xmm0
addps %xmm0, %xmm0
ret
This implements rdar://8230384
llvm-svn: 112101
2010-08-25 22:49:25 +00:00
fd824487a3
Remap metadata attached to instructions when remapping individual
...
instructions, not when remapping modules.
llvm-svn: 112091
2010-08-25 21:36:50 +00:00
3d148ac089
X86: Fix misencode of RI64mi8. This fixes OpenSSL / x86_64-apple-darwin10 / clang -O3.
...
llvm-svn: 112089
2010-08-25 21:11:02 +00:00
01262e129e
DIGlobalVariable can be used to encode debug info for globals that are directly folded into a constant by FE.
...
llvm-svn: 112072
2010-08-25 18:52:02 +00:00
a54a1b0edf
ARM/Thumb2: Fix a misselect in getARMCmp, when attempting to adjust a signed
...
comparison that would overflow.
- The other under/overflow cases can't actually happen because the immediates
which would trigger them are legal (so we don't enter this code), but
adjusted the style to make it clear the transform is always valid.
llvm-svn: 112053
2010-08-25 16:58:05 +00:00
6b1533a1a9
Add another basic test cribbed from the x86 fast-isel tests.
...
llvm-svn: 112036
2010-08-25 07:57:29 +00:00
37d547aee6
Run this on thumb and arm.
...
llvm-svn: 112035
2010-08-25 07:53:15 +00:00
e58c03698e
Make this testcase actually executed with fast-isel on arm.
...
llvm-svn: 112033
2010-08-25 07:47:00 +00:00
0bc919fa35
Convert test to use filecheck and make it more specific
...
llvm-svn: 112016
2010-08-25 01:47:16 +00:00
4afea9e3c6
In the default address space, any GEP off of null results in a trap value if you try to load it. Thus,
...
any load in the default address space that completes implies that the base value that it GEP'd from
was not null.
llvm-svn: 112015
2010-08-25 01:16:47 +00:00
ccd28d0665
Fix COFF x86-64 relocations. PR7960.
...
Multiple symbol reloc handling part of the patch by Cameron Esfahani.
llvm-svn: 111963
2010-08-24 21:04:52 +00:00
c1a8958f76
XFAIL this on mingw, following remove_arguments_test.ll.
...
llvm-svn: 111962
2010-08-24 20:54:50 +00:00
b2f29edc30
Add a testcase for basic bugpointing in the presence of metadata.
...
llvm-svn: 111955
2010-08-24 20:23:51 +00:00
1c8d777c93
MC/X86: Tweak imul recognition, previous hack only applies for the imul form
...
taking immediates.
llvm-svn: 111950
2010-08-24 19:37:56 +00:00
09392785b4
MC/X86: Add custom hack for recognizing "imul $12, %eax" and friends.
...
llvm-svn: 111947
2010-08-24 19:24:18 +00:00
2476432639
MC/AsmParser: Change ParseExpression to use ParseIdentifier(), to support
...
dollars in identifiers.
llvm-svn: 111946
2010-08-24 19:13:42 +00:00
94b84a19b9
MC/X86: Warn on scale factors > 1 without index register, instead of erroring,
...
for 'as' compatibility.
llvm-svn: 111945
2010-08-24 19:13:38 +00:00
3b96ffdac1
MC/Parser: Accept leading dollar signs in identifiers.
...
- Implemented by manually splicing the tokens. If this turns out to be
problematically platform specific, a more elegant solution would be to
implement some context dependent lexing support.
llvm-svn: 111934
2010-08-24 18:12:12 +00:00
c88fda477a
Fix X86's isLegalAddressingMode to recognize that static addresses
...
need not be RIP-relative in small mode.
llvm-svn: 111917
2010-08-24 15:55:12 +00:00
7e25bc4145
Fix SPU BE to use all the available return registers.
...
llc used to assert on the added testcase.
llvm-svn: 111911
2010-08-24 11:50:48 +00:00
c828c5465d
Extend function-local metadata to be usable as attachments.
...
llvm-svn: 111895
2010-08-24 02:24:03 +00:00
02db8f6415
fix rdar://7997827 - Accept and ignore LL and ULL suffixes on integer literals.
...
Also fix 0b010 syntax to actually work while we're at it :-)
llvm-svn: 111876
2010-08-24 00:43:25 +00:00
aaed5ea9b7
llvmc: Make syntax more consistent.
...
CompilationGraph and LanguageMap definitions do not use special syntax anymore.
llvm-svn: 111862
2010-08-23 23:21:23 +00:00
58bd73a5a7
Add a new llvm.x86.int intrinsic, allowing access to the
...
x86 int and int3 instructions. Patch by Peter Housel!
llvm-svn: 111831
2010-08-23 19:39:25 +00:00
ebf42ac831
Try to escape the '$'s in these so they reach the underlying 'sh' invocation.
...
I have no idea how lit did the right thing here, but other test runners don't.
llvm-svn: 111805
2010-08-23 08:54:19 +00:00
42ef669d81
Fix x86 fast-isel's cmp+branch folding to avoid folding when the
...
comparison is in a different basic block from the branch. In such
cases, the comparison's operands may not have initialized virtual
registers available.
llvm-svn: 111709
2010-08-21 02:32:36 +00:00
be745d8c00
Replace some NEON vmovl intrinsic that I missed earlier.
...
llvm-svn: 111696
2010-08-20 23:22:43 +00:00
578ee4070c
Create the new linker type "linker_private_weak_def_auto".
...
It's similar to "linker_private_weak", but it's known that the address of the
object is not taken. For instance, functions that had an inline definition, but
the compiler decided not to inline it. Note, unlike linker_private and
linker_private_weak, linker_private_weak_def_auto may have only default
visibility. The symbols are removed by the linker from the final linked image
(executable or dynamic library).
llvm-svn: 111684
2010-08-20 22:05:50 +00:00
74c1f8ed7b
Test should pass on non-Darwin x86.
...
llvm-svn: 111678
2010-08-20 21:18:55 +00:00
bdc237c2ca
Don't run test on PPC darwin.
...
llvm-svn: 111668
2010-08-20 18:29:27 +00:00
84c29a096b
Re-apply r111568 with a fix for the clang self-host.
...
llvm-svn: 111665
2010-08-20 18:24:43 +00:00
fb4c5012eb
Fix vmcore.ml test.
...
llvm-svn: 111664
2010-08-20 18:24:35 +00:00
18277eafb0
llvmc: Fix alias generation.
...
llvm-svn: 111662
2010-08-20 18:16:26 +00:00
a931605647
Convert DbgInfoPrinter to use errs() instead of outs().
...
llvm-svn: 111659
2010-08-20 18:03:05 +00:00
8264a68b4c
Fix the running of ocaml tests.
...
llvm-svn: 111626
2010-08-20 14:51:26 +00:00
b4d48706ca
Expose LLVMSetOperand and LLVMGetNumOperands to llvm-c and ocaml.
...
llvm-svn: 111625
2010-08-20 14:51:22 +00:00
21b62ac673
Fix some Ocaml tests: the %t substitution now returns an absolute path.
...
llvm-svn: 111623
2010-08-20 14:20:17 +00:00
6c66144eb3
The %ocamlopt setting has embedded quotes. Copy the entire value instead
...
of stopping at the first embedded quote.
llvm-svn: 111622
2010-08-20 14:19:38 +00:00
18f47c7105
Update LLVMC tests for r111620.
...
llvm-svn: 111621
2010-08-20 13:03:33 +00:00
9a511c07e4
Replace the arm.neon.vmovls and vmovlu intrinsics with vector sign-extend and
...
zero-extend operations.
llvm-svn: 111614
2010-08-20 04:54:02 +00:00
3323651ec7
Previous revert failed to remove this file.
...
llvm-svn: 111582
2010-08-19 23:45:15 +00:00
43057cd56a
Revert r111568 to unbreak clang self-host.
...
llvm-svn: 111571
2010-08-19 23:25:16 +00:00
bb723b228a
When a set of bitmask operations, typically from a bitfield initialization, only modifies the low bytes of a value,
...
we can narrow the store to only over-write the affected bytes.
llvm-svn: 111568
2010-08-19 22:15:40 +00:00
361b9be7c6
It's possible to sink a def if its local uses are PHI's.
...
llvm-svn: 111537
2010-08-19 18:33:29 +00:00
0d7e9538db
tests: Haste makes waste.
...
llvm-svn: 111525
2010-08-19 16:47:54 +00:00
471a649c6b
tests: Ignore whitespace in llvm_supports_binding() and llvm_gcc_supports().
...
llvm-svn: 111524
2010-08-19 16:46:52 +00:00
d4b6ab9888
Fixed and reactivated a partial specialization test
...
llvm-svn: 111516
2010-08-19 12:42:38 +00:00
f547740d3f
fix PR7465, mishandling of lcall and ljmp: intersegment long
...
call and jumps.
llvm-svn: 111496
2010-08-19 01:18:43 +00:00
8d5f0208f2
Testcase for llvm-gcc checkin 111482.
...
llvm-svn: 111483
2010-08-19 00:09:07 +00:00
3decde9305
refix PR1143 by making basicaa analyze zexts of indices aggresively,
...
which I broke with a recent patch.
llvm-svn: 111452
2010-08-18 23:09:49 +00:00
492c2ea31e
Add a testcase to verify that commands don't crash when they hit
...
errors on stderr.
llvm-svn: 111440
2010-08-18 22:35:56 +00:00
82656fb0e1
When sending stats output to stdout for grepping, don't emit normal
...
output to standard output also.
llvm-svn: 111435
2010-08-18 22:22:44 +00:00
2470818942
When sending stats output to stdout for grepping, don't emit normal
...
output to standard output also.
llvm-svn: 111401
2010-08-18 20:32:46 +00:00
8e92d9b68d
MC/ELF: Allow null values in virtual sections, ELF doesn't use special
...
directives for putting contents in .bss, for example.
llvm-svn: 111376
2010-08-18 18:22:37 +00:00
e60b5161d1
Fix a bug with insertelement on SPU.
...
The previous algorithm in LowerVECTOR_SHUFFLE
didn't check all requirements for "monotonic" shuffles.
llvm-svn: 111361
2010-08-18 10:20:29 +00:00
ab49360f59
Remove all traces of v2[i,f]32 on SPU.
...
The "half vectors" are now widened to full size by the legalizer.
The only exception is in parameter passing, where half vectors are
expanded. This causes changes to some dejagnu tests.
llvm-svn: 111360
2010-08-18 10:04:39 +00:00
f3984d1ef6
Change SPU C calling convention to match that described in
...
"SPU Application Binary Interface Specification, v1.9" by
IBM.
Specifically: use r3-r74 to pass parameters and the return value.
llvm-svn: 111358
2010-08-18 09:50:30 +00:00
a25c05ed15
fix a buggy test
...
llvm-svn: 111354
2010-08-18 04:55:12 +00:00
a33edcb56c
fix PR7589: In brief:
...
gep P, (zext x) != gep P, (sext x)
DecomposeGEPExpression was getting this wrong, confusing
basicaa.
llvm-svn: 111352
2010-08-18 04:28:19 +00:00
c8e38eb60b
filecheckize and detrivialize.
...
llvm-svn: 111350
2010-08-18 04:25:43 +00:00
3c603024bb
Fix PR7755: knowing something about an inval for a pred
...
from the LHS should disable reconsidering that pred on the
RHS. However, knowing something about the pred on the RHS
shouldn't disable subsequent additions on the RHS from
happening.
llvm-svn: 111349
2010-08-18 03:14:36 +00:00
fb7eaff759
Expand ZERO_EXTEND operations for NEON vector types.
...
Testcase from Nick Lewycky.
llvm-svn: 111341
2010-08-18 01:45:52 +00:00
51edc7b7e1
Temporarily revert r110987 as it's causing some miscompares in
...
vector heavy code. I'll re-enable when we've tracked down the problem.
llvm-svn: 111318
2010-08-17 22:55:27 +00:00
ed2b005842
Tweak IVUsers' concept of "interesting" to exclude add recurrences
...
where the step value is an induction variable from an outer loop, to
avoid trouble trying to re-expand such expressions. This effectively
hides such expressions from indvars and lsr, which prevents them
from getting into trouble.
llvm-svn: 111317
2010-08-17 22:50:37 +00:00
efdc74ea59
Add nounwind.
...
llvm-svn: 111312
2010-08-17 22:35:20 +00:00
16f96445c3
Make fast scheduler handle asm clobbers correctly.
...
PR 7882. Follows suggestion by Amaury Pouly, thanks.
llvm-svn: 111306
2010-08-17 22:17:24 +00:00
14be4dff8e
Add some win64 coff goodness.
...
Patch by Cameron Esfahani!
llvm-svn: 111287
2010-08-17 21:05:54 +00:00
5047ca0c02
When rotating loops, put the original header at the bottom of the
...
loop, making the resulting loop significantly less ugly. Also, zap
its trivial PHI nodes, since it's easy.
llvm-svn: 111255
2010-08-17 17:39:21 +00:00
942b10f511
Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoid
...
printing "lsl #0". This fixes the remaining parts of pr7792. Make
corresponding changes for encoding/decoding these instructions.
llvm-svn: 111251
2010-08-17 17:23:19 +00:00
411dfad981
Allow more cases of undef shuffle indices and add tests for them.
...
llvm-svn: 111226
2010-08-17 05:54:34 +00:00
f259efde47
PHI elimination should not break back edge. It can cause some significant code placement issues. rdar://8263994
...
good:
LBB0_2:
mov r2, r0
. . .
mov r1, r2
bne LBB0_2
bad:
LBB0_2:
mov r2, r0
. . .
@ BB#3:
mov r1, r2
b LBB0_2
llvm-svn: 111221
2010-08-17 01:20:36 +00:00
eee4824f74
Add a testcase for svn 111208.
...
llvm-svn: 111212
2010-08-16 23:44:29 +00:00
804f6159f1
Generalize a pattern for PKHTB: an SRL of 16-31 bits will guarantee
...
that the high halfword is zero. The shift need not be exactly 16 bits.
llvm-svn: 111196
2010-08-16 22:26:55 +00:00
3fd1e0dcda
Convert test to FileCheck.
...
llvm-svn: 111195
2010-08-16 22:21:13 +00:00
8f553757c4
Convert a test to use FileCheck.
...
llvm-svn: 111153
2010-08-16 17:05:27 +00:00
250b754428
Instead, teach SimplifyCFG to trim non-address-taken blocks from
...
indirectbr destination lists.
llvm-svn: 111122
2010-08-16 14:41:14 +00:00
fb83b043eb
Revert r111058, the lint check for indirectbr successors that aren't
...
address-taken. This can occur normally, if the code which took the
address got DCEd.
llvm-svn: 111121
2010-08-16 14:39:19 +00:00
cbc55d9dc0
Test expects SSE, give him SSE.
...
llvm-svn: 111115
2010-08-15 23:32:03 +00:00
4566466b7f
Restore arch on these test, they fail on arm.
...
llvm-svn: 111109
2010-08-15 20:42:56 +00:00
339423c460
Mark as XFAIL on darwin 8. PR 7886.
...
llvm-svn: 111108
2010-08-15 19:40:29 +00:00
b1ec90bcf4
Update tests.
...
llvm-svn: 111096
2010-08-15 07:07:24 +00:00
aa445c0751
LoopSimplify shouldn't split loop backedges that use indirectbr. PR7867.
...
llvm-svn: 111061
2010-08-14 00:43:09 +00:00
4a63fad976
Teach SimplifyCFG how to simplify indirectbr instructions.
...
- Eliminate redundant successors.
- Convert an indirectbr with one successor into a direct branch.
Also, generalize SimplifyCFG to be able to be run on a function entry block.
It knows quite a few simplifications which are applicable to the entry
block, and it only needs a few checks to avoid trouble with the entry block.
llvm-svn: 111060
2010-08-14 00:29:42 +00:00
21e6dc6aa3
Add a lint check for an indirectbr destination which has not
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had its address taken.
llvm-svn: 111058
2010-08-13 23:56:28 +00:00
4577f37d49
Add a Thumb2 t2RSBrr instruction for disassembly only.
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This fixes another part of PR7792.
llvm-svn: 111057
2010-08-13 23:24:25 +00:00
3c9ed76ba5
Temporarily disable tail calls on ARM to work around some linker problems.
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llvm-svn: 111050
2010-08-13 22:43:33 +00:00
15b3c3d0ac
Move the Thumb2 SSAT and USAT optional shift operator out of the
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instruction opcode. This fixes part of PR7792.
llvm-svn: 111047
2010-08-13 21:48:10 +00:00
8d3c89e765
Revert 110491. While not wrong, it was based on a
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misanalysis and is undesirable.
llvm-svn: 111028
2010-08-13 18:43:45 +00:00
1d54a4ea1d
One more XFAIL.
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llvm-svn: 111010
2010-08-13 07:03:56 +00:00
49fd7d3a5f
More XFAILs.
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llvm-svn: 111008
2010-08-13 07:01:55 +00:00
143a33758c
Add an XFAIL.
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llvm-svn: 111004
2010-08-13 04:15:45 +00:00
ee1ef8c402
Remove -fexceptions from llvmc tests.
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llvm-svn: 110999
2010-08-13 02:29:35 +00:00
d2cc5fb971
llvmc: fix two tests, remove XFAILs.
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Tested on Linux and Darwin; please add platform-specific XFAILs/mail me a bug
report if this still fails.
llvm-svn: 110998
2010-08-13 02:29:24 +00:00
2a0ca3e937
Reapply this transformation now that it is passing the external test which it previously failed.
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llvm-svn: 110987
2010-08-13 00:17:53 +00:00
363226dfe8
fix PR7876: If ipsccp decides that a function's address is taken
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before it rewrites the code, we need to use that in the post-rewrite pass.
llvm-svn: 110962
2010-08-12 22:25:23 +00:00
8e8f1c133a
Cleaned up the for-disassembly-only entries in the arm instruction table so that
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the memory barrier variants (other than 'SY' full system domain read and write)
are treated as one instruction with option operand.
llvm-svn: 110951
2010-08-12 20:46:17 +00:00
7f704b31a9
- Teach SSEDomainFix to switch between different levels of AVX instructions. Here we guess that AVX will have domain issues, so just implement them for consistency and in the future we remove if it's unnecessary.
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- Make foldMemoryOperandImpl aware of 256-bit zero vectors folding and support the 128-bit counterparts of AVX too.
- Make sure MOV[AU]PS instructions are only selected when SSE1 is enabled, and duplicate the patterns to match AVX.
- Add a testcase for a simple 128-bit zero vector creation.
llvm-svn: 110946
2010-08-12 20:20:53 +00:00
86fa07ea05
Add a test for llvm-gcc svn 110632.
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llvm-svn: 110935
2010-08-12 17:31:41 +00:00
ac40d49c70
Temporarily revert 110737 and 110734, they were causing failures
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in an external testsuite.
llvm-svn: 110905
2010-08-12 07:01:22 +00:00
7306c86886
Begin to support some vector operations for AVX 256-bit intructions. The long
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term goal here is to be able to match enough of vector_shuffle and build_vector
so all avx intrinsics which aren't mapped to their own built-ins but to
shufflevector calls can be codegen'd. This is the first (baby) step, support
building zeroed vectors.
llvm-svn: 110897
2010-08-12 02:06:36 +00:00
74491bb52c
The autogened decoder was confusing the ARM STRBT for ARM USAT, because the .td
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entry for ARM STRBT is actually a super-instruction for A8.6.199 STRBT A1 & A2.
Recover by looking for ARM:USAT encoding pattern before delegating to the auto-
gened decoder.
Added a "usat" test case to arm-tests.txt.
llvm-svn: 110894
2010-08-12 01:40:54 +00:00
7d7b4d1b0f
MC/X86/AsmParser: Give an explicit error message when we reject an instruction
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because it could have an ambiguous suffix.
llvm-svn: 110890
2010-08-12 00:55:42 +00:00
48595bf2bc
This is x86 only test.
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llvm-svn: 110887
2010-08-12 00:17:38 +00:00
d59c73f998
Changed the format of DMBsy, DSBsy, and friends from Pseudo to MiscFrm.
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Added two test cases to arm-tests.txt.
llvm-svn: 110880
2010-08-11 23:35:12 +00:00
add513112a
Move the ARM SSAT and USAT optional shift amount operand out of the
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instruction opcode. This also fixes part of PR7792.
llvm-svn: 110875
2010-08-11 23:10:46 +00:00
1675ee7a02
Add testcases for all AVX 256-bit intrinsics added in the last couple days
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llvm-svn: 110854
2010-08-11 21:12:09 +00:00
29c8818ad9
Reapply r109881 using a more strict command line for llc.
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llvm-svn: 110833
2010-08-11 17:39:23 +00:00
a5f923b1a1
fix silly typo
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llvm-svn: 110831
2010-08-11 17:32:46 +00:00
2bf8bd1e19
Add a target triple, as the runtime library invocation varies a bit by
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platform. It's apparently "bl __muldf3" on linux, for example. Since that's
not what we're checking here, it's more robust to just force a triple. We
just wwant to check that the inline FP instructions are only generated
on cpus that have them."
llvm-svn: 110830
2010-08-11 17:31:12 +00:00
b0276814d5
Fix test and re-enable it.
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llvm-svn: 110829
2010-08-11 17:25:51 +00:00
4df4114870
Temporarily disable some failing tests, until they can be
...
properly investigated.
llvm-svn: 110825
2010-08-11 16:36:07 +00:00
4d5dc3e7e5
cortex m4 has floating point support, but only single precision.
...
llvm-svn: 110810
2010-08-11 15:44:15 +00:00
f3d783a6d2
Temporarily disable some failing tests, until they can be
...
properly investigated.
llvm-svn: 110808
2010-08-11 15:09:00 +00:00
6a98131468
Consider this code snippet:
...
float t1(int argc) {
return (argc == 1123) ? 1.234f : 2.38213f;
}
We would generate truly awful code on ARM (those with a weak stomach should look
away):
_t1:
movw r1, #1123
movs r2, #1
movs r3, #0
cmp r0, r1
mov.w r0, #0
it eq
moveq r0, r2
movs r1, #4
cmp r0, #0
it ne
movne r3, r1
adr r0, #LCPI1_0
ldr r0, [r0, r3]
bx lr
The problem was that legalization was creating a cascade of SELECT_CC nodes, for
for the comparison of "argc == 1123" which was fed into a SELECT node for the ?:
statement which was itself converted to a SELECT_CC node. This is because the
ARM back-end doesn't have custom lowering for SELECT nodes, so it used the
default "Expand".
I added a fairly simple "LowerSELECT" to the ARM back-end. It takes care of this
testcase, but can obviously be expanded to include more cases.
Now we generate this, which looks optimal to me:
_t1:
movw r1, #1123
movs r2, #0
cmp r0, r1
adr r0, #LCPI0_0
it eq
moveq r2, #4
ldr r0, [r0, r2]
bx lr
.align 2
LCPI0_0:
.long 1075344593 @ float 2.382130e+00
.long 1067316150 @ float 1.234000e+00
llvm-svn: 110799
2010-08-11 08:43:16 +00:00
5190f09291
Report error if codegen tries to instantiate a ARM target when the cpu does support it. e.g. cortex-m* processors.
...
llvm-svn: 110798
2010-08-11 07:17:46 +00:00
40921a4e62
Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.)
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llvm-svn: 110795
2010-08-11 06:51:54 +00:00
188b47b214
MC/ARM: Add basic support for handling predication by parsing it out of the mnemonic into a separate operand form.
...
llvm-svn: 110794
2010-08-11 06:37:20 +00:00
49e02fc414
Add Cortex-M0 support. It's a ARMv6m device (no ARM mode) with some 32-bit
...
instructions: dmb, dsb, isb, msr, and mrs.
llvm-svn: 110786
2010-08-11 06:30:38 +00:00
6e809de90c
- Add subtarget feature -mattr=+db which determine whether an ARM cpu has the
...
memory and synchronization barrier dmb and dsb instructions.
- Change instruction names to something more sensible (matching name of actual
instructions).
- Added tests for memory barrier codegen.
llvm-svn: 110785
2010-08-11 06:22:01 +00:00
79937dfc5b
Update test to match output of optimize compares for ARM.
...
llvm-svn: 110765
2010-08-11 01:05:02 +00:00
f7495f286a
When analyzing loop exit conditions combined with and and or, don't
...
make any assumptions about when the two conditions will agree on when
to permit the loop to exit. This fixes PR7845.
llvm-svn: 110758
2010-08-11 00:12:36 +00:00
871d4e1170
The optimize comparisons pass removes the "cmp" instruction this is checking for.
...
llvm-svn: 110739
2010-08-10 22:16:05 +00:00
3ec892c167
Add test for recent instcombine vector shuffle enhancement
...
llvm-svn: 110737
2010-08-10 21:58:00 +00:00
18cc4acb00
tests: Don't error out if HOME isn't present in t the environment.
...
llvm-svn: 110711
2010-08-10 19:36:25 +00:00
3f251fb26e
Re-apply r110655 with fixes. Epilogue must restore sp from fp if the function stack frame has a var-sized object.
...
Also added a test case to check for the added benefit of this patch: it's optimizing away the unnecessary restore of sp from fp for some non-leaf functions.
llvm-svn: 110707
2010-08-10 19:30:19 +00:00
0dd47bfca3
Revert r110655, "Fix ARM hasFP() semantics. It should return true whenever FP
...
register is", it breaks a couple test-suite tests.
llvm-svn: 110701
2010-08-10 18:32:02 +00:00
d215976208
MC/AsmParser: Fix a bug in macro argument parsing, which was dropping
...
parentheses from argument lists.
llvm-svn: 110692
2010-08-10 17:38:52 +00:00
5730846c2f
Fix test for more architectures. Patch by Tobias Grosser.
...
llvm-svn: 110685
2010-08-10 16:48:24 +00:00
7fbe6cb429
RegionInfo: Do not assert if a BB is not part of the dominance tree.
...
llvm-svn: 110665
2010-08-10 09:54:35 +00:00
fedeff8015
Fix failing testcase.
...
Those look like typos to me.
llvm-svn: 110664
2010-08-10 09:54:29 +00:00
b219746c80
Handle TAG_constant for integers.
...
llvm-svn: 110656
2010-08-10 07:11:13 +00:00
8d5d1c1331
Fix ARM hasFP() semantics. It should return true whenever FP register is
...
reserved, not available for general allocation. This eliminates all the
extra checks for Darwin.
This change also fixes the use of FP to access frame indices in leaf
functions and cleaned up some confusing code in epilogue emission.
llvm-svn: 110655
2010-08-10 06:26:49 +00:00
f99e7e6643
PR7853: fix a silly mistake introduced in r101899, and add a test to make sure
...
it doesn't regress again.
llvm-svn: 110597
2010-08-09 20:49:43 +00:00
999da1f3a0
Have SPU handle halfvec stores aligned by 8 bytes.
...
llvm-svn: 110576
2010-08-09 16:33:00 +00:00
cc4a9670d3
XFAIL for mingw that has no plugins.
...
llvm-svn: 110574
2010-08-09 15:14:06 +00:00
7f36ac54d7
Reject unrepresentable pointer types in intrinsics. Fixes PR7316.
...
llvm-svn: 110541
2010-08-08 06:12:09 +00:00
8aa19b05ee
Use %shlibext instead of .so
...
llvm-svn: 110529
2010-08-08 00:55:59 +00:00
92a4a833f9
Move the bugpoint test passes to a plugin in preparation for having bugpoint
...
use opt.
llvm-svn: 110520
2010-08-07 21:48:09 +00:00
a3bd31a923
Use sdmem and sse_load_f64 (etc.) for the vector
...
form of CMPSD (etc.) Matching a 128-bit memory
operand is wrong, the instruction uses only 64 bits
(same as ADDSD etc.) 8193553.
llvm-svn: 110491
2010-08-07 00:33:42 +00:00
5afa738d7f
Test case for r110459. Radar 8264751. Test case by Fariborz Jahanian!
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llvm-svn: 110467
2010-08-06 19:02:24 +00:00
Daniel Dunbar