1198d894d0
The order in which the predicate is added differs between Thumb and ARM mode. Fix predicate when in ARM mode and restore SelectIntrinsicCall.
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llvm-svn: 144494
2011-11-13 09:44:21 +00:00
a476e391f1
Temporarily disable SelectIntrinsicCall when in ARM mode. This is causing failures.
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llvm-svn: 144492
2011-11-13 05:14:43 +00:00
c8cfd3a8fb
Add support for emitting both signed- and zero-extend loads. Fix
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SimplifyAddress to handle either a 12-bit unsigned offset or the ARM +/-imm8
offsets (addressing mode 3). This enables a load followed by an integer
extend to be folded into a single load.
For example:
ldrb r1, [r0] ldrb r1, [r0]
uxtb r2, r1 =>
mov r3, r2 mov r3, r1
llvm-svn: 144488
2011-11-13 02:23:59 +00:00
6ddb767fb5
Remove the -color-ss-with-regs option.
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It was off by default.
The new register allocators don't have the problems that made it
necessary to reallocate registers during stack slot coloring.
llvm-svn: 144481
2011-11-13 00:31:23 +00:00
7ef502f6d1
Delete the 'standard' spiller with used the old spilling framework.
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The current register allocators all use the inline spiller.
llvm-svn: 144477
2011-11-12 23:29:02 +00:00
ce4ef9f8d5
Remove histogram tests.
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Counting the number of occurences of each opcode is not a useful test.
llvm-svn: 144474
2011-11-12 22:39:40 +00:00
0eac531bc2
RAGreedy is better about hinting now.
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Or maybe we are just getting lucky.
llvm-svn: 144473
2011-11-12 22:39:37 +00:00
8ec1a92afd
Linear scan is going away.
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llvm-svn: 144472
2011-11-12 22:39:34 +00:00
654d60888e
XFAIL test that depends on linear scan to remove dead code.
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Filed PR11364 to track the problem. Should the register allocator
eliminate dead code?
llvm-svn: 144471
2011-11-12 22:39:30 +00:00
fa3a8ee6e2
Remove obsolete test.
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This test was committed with a bugfix to RemoveCopyByCommutingDef, but
that optimization is no longer triggered by this test.
llvm-svn: 144470
2011-11-12 22:39:27 +00:00
80b3d299a9
Remove obsolete test.
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This test is for a very specific LocalRewriter bug. LocalRewriter is
going away.
llvm-svn: 144469
2011-11-12 22:39:24 +00:00
0c7d9d90ef
Remove obsolete test.
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I don't think this test does what is was supposed to do, and
LocalRewriter is going away anyway.
llvm-svn: 144463
2011-11-12 20:37:57 +00:00
126f9779c3
Eliminate more linear scan tests.
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llvm-svn: 144462
2011-11-12 20:35:26 +00:00
9d090daa33
Switch a couple -O0 tests to RABasic.
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llvm-svn: 144461
2011-11-12 20:11:04 +00:00
4deff7bc1d
Switch a few tests off linearscan.
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llvm-svn: 144460
2011-11-12 19:53:52 +00:00
6ac6aa782d
Delete old test of a VirtRegRewriter feature.
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This test doesn't expose the issue with RAGreedy.
I filed PR11363 to track the missing InlineSpiller feature.
llvm-svn: 144459
2011-11-12 19:53:48 +00:00
74d091b395
Remove old test that doesn't make sense.
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The test is checking that the output doesn't contains any 'mov '
strings. It does contain movl, though.
llvm-svn: 144458
2011-11-12 19:53:45 +00:00
3dc75f9e3b
Add more AVX2 shift lowering support. Move AVX2 variable shift to use patterns instead of custom lowering code.
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llvm-svn: 144457
2011-11-12 09:58:49 +00:00
d48ab84556
Don't try to loop on iterators that are potentially invalidated inside the loop. Fixes PR11361!
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llvm-svn: 144454
2011-11-12 03:09:12 +00:00
ecb453805d
Make sure scalarrepl picks the correct alloca when it rewrites a bitcast. Fixes PR11353.
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llvm-svn: 144442
2011-11-12 02:07:50 +00:00
e7cc8bff82
The dwarf standard says that the only differences between a out-of-line
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instance and a concrete inlined instance are the use of DW_TAG_subprogram
instead of DW_TAG_inlined_subroutine and the who owns the tree.
We were also omitting DW_AT_inline from the abstract roots. To fix this,
make sure we mark abstract instance roots with DW_AT_inline even when
we have only out-of-line instances referring to them with DW_AT_abstract_origin.
FileCheck is not a very good tool for tests like this, maybe we should add
a -verify mode to llvm-dwarfdump.
llvm-svn: 144441
2011-11-12 01:57:54 +00:00
9d448e4a42
Don't try to form pre/post-indexed loads/stores until after LegalizeDAG runs. Fixes PR11029.
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llvm-svn: 144438
2011-11-12 00:35:34 +00:00
609d113874
ARM optional size suffix for VLDR/VSTR syntax.
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llvm-svn: 144427
2011-11-11 23:34:43 +00:00
a7ebc5617d
Add support in fast-isel for selecting memset/memcpy/memmove intrinsics.
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llvm-svn: 144426
2011-11-11 23:31:03 +00:00
ab1a4a2301
Loosen test by using REs. Approved by Devang.
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llvm-svn: 144425
2011-11-11 23:25:38 +00:00
28c1d18434
Preserve MachineMemOperands in ARMLoadStoreOptimizer.
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Fixes PR8113.
llvm-svn: 144409
2011-11-11 22:18:09 +00:00
85a2343b01
ARM allow Q registers in vldm/vstm register lists.
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rdar://9672822
llvm-svn: 144407
2011-11-11 21:27:40 +00:00
a90cb76489
Move X86 specific test in X86 directory.
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llvm-svn: 144395
2011-11-11 18:13:19 +00:00
a39794b029
Move X86 specific test in X86 directory.
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llvm-svn: 144394
2011-11-11 18:10:38 +00:00
089cc53232
allow non-device function calls in PTX when natively handling device-side printf
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llvm-svn: 144388
2011-11-11 14:45:12 +00:00
ea28a34c43
Add lowering for AVX2 shift instructions.
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llvm-svn: 144380
2011-11-11 07:39:23 +00:00
7ddd63ce4e
Add support for using immediates with select instructions.
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rdar://10412592
llvm-svn: 144376
2011-11-11 06:20:39 +00:00
c4a001478c
Make sure to expand SIGN_EXTEND_INREG for NEON vectors. PR11319, round 3.
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llvm-svn: 144361
2011-11-11 03:16:38 +00:00
0a309292c4
Get rid of an optimization in SCCP which appears to have many issues. Specifically, it doesn't handle many cases involving undef correctly, and it is missing other checks which
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lead to it trying to re-mark a value marked as a constant with a different value. It also appears to trigger very rarely.
Fixes PR11357.
llvm-svn: 144352
2011-11-11 01:16:15 +00:00
2a3503e061
Add support for using MVN to materialize negative constants.
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rdar://10412592
llvm-svn: 144348
2011-11-11 00:36:21 +00:00
9bded9dc24
Thumb2 parsing for push/pop w/ hi registers in the reglist.
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rdar://10130228.
llvm-svn: 144331
2011-11-10 23:17:11 +00:00
79278365d3
Check in getOrCreateSubprogramDIE if a declaration exists and if so output
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it first.
This is a more general fix to pr11300.
llvm-svn: 144324
2011-11-10 22:34:29 +00:00
5a5ce63742
Thumb MUL assembly parsing for 3-operand form.
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Get the source register that isn't tied to the destination register correct,
even when the assembly source operand order is backwards.
rdar://10428630
llvm-svn: 144322
2011-11-10 22:10:12 +00:00
d1762e00e2
When in ARM mode, LDRH/STRH require special handling of negative offsets.
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For correctness, disable this for now.
rdar://10418009
llvm-svn: 144316
2011-11-10 21:09:49 +00:00
c14871cc67
ARM assembly parsing for LSR/LSL/ROR(immediate).
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More of rdar://9704684
llvm-svn: 144301
2011-11-10 19:18:01 +00:00
61db5a59f7
ARM assembly parsing for ASR(immediate).
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Start of rdar://9704684
llvm-svn: 144293
2011-11-10 16:44:55 +00:00
270354100a
test/CodeGen/X86/lsr-loop-exit-cond.ll: Try to appease linux and freebsd bots to specify explicit -mtriple=x86_64-darwin.
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I guess it expects -relocation-model=pic.
llvm-svn: 144290
2011-11-10 14:18:59 +00:00
d33b2d6b7a
Use a bigger hammer to fix PR11314 by disabling the "forcing two-address
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instruction lower optimization" in the pre-RA scheduler.
The optimization, rather the hack, was done before MI use-list was available.
Now we should be able to implement it in a better way, perhaps in the
two-address pass until a MI scheduler is available.
Now that the scheduler has to backtrack to handle call sequences. Adding
artificial scheduling constraints is just not safe. Furthermore, the hack
is not taking all the other scheduling decisions into consideration so it's just
as likely to pessimize code. So I view disabling this optimization goodness
regardless of PR11314.
llvm-svn: 144267
2011-11-10 07:43:16 +00:00
3fbd094ad9
For immediate encodings of icmp, zero or sign extend first. Then
...
determine if the value is negative and flip the sign accordingly.
rdar://10422026
llvm-svn: 144258
2011-11-10 01:30:39 +00:00
eef48b6938
Strip old implicit operands after foldMemoryOperand.
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The TII.foldMemoryOperand hook preserves implicit operands from the
original instruction. This is not what we want when those implicit
operands refer to the register being spilled.
Implicit operands referring to other registers are preserved.
This fixes PR11347.
llvm-svn: 144247
2011-11-10 00:17:03 +00:00
25bc090170
Thumb2 assembly parsing STMDB w/ optional .w suffix.
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rdar://10422955
llvm-svn: 144242
2011-11-09 23:44:23 +00:00
2d4055b683
Make sure we correctly unroll conversions between v2f64 and v2i32 on ARM.
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llvm-svn: 144241
2011-11-09 23:36:02 +00:00
856977cb15
DeadStoreElimination can now trim the size of a store if the end of the store is dead.
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Currently checks alignment and killing stores on a power of 2 boundary as this is likely
to trim the size of the earlier store without breaking large vector stores into scalar ones.
Fixes <rdar://problem/10140300>
llvm-svn: 144239
2011-11-09 23:07:35 +00:00
53218b6fcc
Add check so we don't try to perform an impossible transformation. Fixes issue from PR11319.
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llvm-svn: 144216
2011-11-09 22:25:12 +00:00
1938482bfa
AVX2: Add patterns for variable shift operations
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llvm-svn: 144212
2011-11-09 21:22:13 +00:00
Chad Rosier