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188 Commits

Author SHA1 Message Date
Owen Anderson ce2250fba4 Fill out support for Thumb2 encodings of NEON instructions. 
llvm-svn: 118854
 2010-11-11 23:12:55 +00:00
Owen Anderson 99a8cb4875 Add correct Thumb2 encodings for NEON vst[1,2,3,4] and vld[1,2,3,4]. 
llvm-svn: 118843
 2010-11-11 21:36:43 +00:00
Owen Anderson 7ffe3b35ac Add support for Thumb2 encodings of NEON data processing instructions, using the new PostEncoderMethod infrastructure. 
More tests to come.

llvm-svn: 118819
 2010-11-11 19:07:48 +00:00
Jim Grosbach 68685e644f Encoding for ARM LDRSH_POST. 
llvm-svn: 118794
 2010-11-11 16:55:29 +00:00
Jim Grosbach f18b951e18 Encoding for ARM LDRSH and LDRSH_PRE. Cannonicalize operand names. 
llvm-svn: 118767
 2010-11-11 01:55:59 +00:00
Jim Grosbach 607efcbc3e ARM STRH encoding information. 
llvm-svn: 118757
 2010-11-11 01:09:40 +00:00
Jim Grosbach c4dd2349c7 Move LDM predicate operand encoding into base clase. Add STM missing STM 
encoding bits.

llvm-svn: 118738
 2010-11-10 23:44:32 +00:00
Jim Grosbach cc4a491557 ARM LDM encoding for the mode (ia, ib, da, db) operand. 
llvm-svn: 118736
 2010-11-10 23:38:36 +00:00
Jim Grosbach 58ef598cd1 Fix ARM encoding of non-return LDM instructions. 
llvm-svn: 118732
 2010-11-10 23:18:49 +00:00
Jim Grosbach e39a9fcc0e Fix ARM encoding of LDM+Return instruction. 
llvm-svn: 118730
 2010-11-10 23:12:48 +00:00
Bill Wendling c002463ac4 Add encoding for VSTR. 
llvm-svn: 118220
 2010-11-04 00:59:42 +00:00
Owen Anderson 0ebd1fd594 Revert r118097 to fix buildbots. 
llvm-svn: 118121
 2010-11-02 23:47:29 +00:00
Owen Anderson 7c30390277 Since these fields are not exactly equivalent to the encoded field, rename them to something with semantic meaning. 
llvm-svn: 118097
 2010-11-02 22:41:42 +00:00
Owen Anderson 9f20daf3b4 Factor out a common encoding class for loads and stores with a lane parameter. 
llvm-svn: 118055
 2010-11-02 20:47:39 +00:00
Owen Anderson ad40234eff Add correct NEON encodings for the "multiple single elements" form of vld. 
llvm-svn: 117984
 2010-11-02 00:05:05 +00:00
Bill Wendling 418bd53008 Move the machine operand MC encoding patterns to the parent classes. 
llvm-svn: 117956
 2010-11-01 21:17:06 +00:00
Jim Grosbach fddf36d254 Add 'IsThumb' predicate to patterns marked as 'IsThumb1Only'. The latter gates 
codegen using the patterns; the latter gates the assembler recognizing the
instruction.

llvm-svn: 117931
 2010-11-01 17:08:58 +00:00
Bill Wendling 2623343625 Move instruction encoding bits into the parent class and remove the temporary 
*_Encode classes. These instructions are the only ones which use those classes,
so a subclass isn't necessary.

llvm-svn: 117906
 2010-11-01 06:00:39 +00:00
Chris Lattner 7ff334687d fix the !eq operator in tblgen to return a bit instead of an int. 
Use this to make the X86 and ARM targets set isCodeGenOnly=1 
automatically for their instructions that have Format=Pseudo,
resolving a hack in tblgen.

llvm-svn: 117862
 2010-10-31 19:22:57 +00:00
Jim Grosbach 74ef9e184e Encode the register list operands for ARM mode LDM/STM instructions. 
llvm-svn: 117753
 2010-10-30 00:37:59 +00:00
Jim Grosbach 3b7e05bb97 ARM encoding information for CLREX, SWP and SWPB. Add comment for sjlj pseudos and a FIXME for TLS. 
llvm-svn: 117702
 2010-10-29 20:21:36 +00:00
Jim Grosbach 4e57b52394 ARM mode LDREX*/STREX* binary encodings. 
llvm-svn: 117695
 2010-10-29 19:58:57 +00:00
Jim Grosbach 338de3ee56 Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like 
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752

llvm-svn: 117505
 2010-10-27 23:12:14 +00:00
Owen Anderson ed9652f959 Provide correct encodings for the get_lane and set_lane variants of vmov. 
llvm-svn: 117495
 2010-10-27 21:28:09 +00:00
Owen Anderson 40d24a4abf Provide correct NEON encodings for vdup. 
llvm-svn: 117475
 2010-10-27 19:25:54 +00:00
Jim Grosbach 1e4d9a17c2 First part of refactoring ARM addrmode2 (load/store) instructions to be more 
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.

llvm-svn: 117409
 2010-10-26 22:37:02 +00:00
Owen Anderson 3665fee8de Provide correct NEON encodings for vshl, register and immediate forms. 
llvm-svn: 117394
 2010-10-26 20:56:57 +00:00
Owen Anderson 284cb361d1 Add NEON encodings for vmov and vmvn of immediates. 
llvm-svn: 117374
 2010-10-26 17:40:54 +00:00
Evan Cheng b45591979b NEON vmov's are in Neon domain. 
llvm-svn: 117347
 2010-10-26 02:03:05 +00:00
Owen Anderson 2477446ee5 Add correct instruction encodings for vbic, vorn, and vmvn. 
llvm-svn: 117282
 2010-10-25 18:43:52 +00:00
Owen Anderson dff239c5f9 Provide correct NEON encodings for vand, veor, and vorr. 
llvm-svn: 117279
 2010-10-25 18:28:30 +00:00
Jim Grosbach 2c9ae05c67 ARM mode encoding information for CLZ, RBIT, REV*, and PKH*. 
llvm-svn: 117165
 2010-10-22 22:12:16 +00:00
Jim Grosbach 6956a60563 More ARM multiply instuction binary encodings. 
llvm-svn: 117121
 2010-10-22 18:35:16 +00:00
Jim Grosbach f98df0849f Parameterize a bit of ARM encoding information, simplifying some instruction 
definitions.

llvm-svn: 117114
 2010-10-22 17:42:06 +00:00
Jim Grosbach 22261600a8 More ARM multiply instruction encoding information. 
llvm-svn: 117108
 2010-10-22 17:16:17 +00:00
Owen Anderson 9e44cf2bb2 ARM encodes Q registers as 2xregno (i.e. the number of the D register that corresponds to the lower 
half of the Q register), rather than with just regno.  This allows us to unify the encodings for
a lot of different NEON instrucitons that differ only in whether they have Q or D register operands.

llvm-svn: 117056
 2010-10-21 20:21:49 +00:00
Bob Wilson 59351844e1 ARM instructions that are both predicated and set the condition codes 
have been printed with the "S" modifier after the predicate.  With ARM's
unified syntax, they are supposed to go in the other order.  We fixed this
for Thumb when we switched to unified syntax but missed changing it for
ARM.  Apparently we don't generate these instructions often because no one
noticed until now.  Thanks to Bill Wendling for the testcase!

llvm-svn: 116563
 2010-10-15 03:23:44 +00:00
Jim Grosbach b9386558a7 trailing whitespace 
llvm-svn: 116450
 2010-10-13 23:12:26 +00:00
Jim Grosbach 7e72ec6626 Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern 
and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.

llvm-svn: 116432
 2010-10-13 21:00:04 +00:00
Jim Grosbach 1e7db68774 Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions. 
llvm-svn: 116421
 2010-10-13 19:56:10 +00:00
Jim Grosbach d9d31dafda Add custom encoder for the 's' bit denoting whether an ARM arithmetic 
instruction should set the processor status flags or not. Remove the now
unnecessary special handling for the bit from the MCCodeEmitter.

llvm-svn: 116360
 2010-10-12 23:00:24 +00:00
Bill Wendling 98c29d732d Split out the "size" field from the encoding. The newer documentation has it as 
a separate bit in the coding.

llvm-svn: 116347
 2010-10-12 22:03:19 +00:00
Jim Grosbach 576640f0e3 Encoding for ARM-mode VADD.F32 instruction. 
llvm-svn: 116338
 2010-10-12 21:22:40 +00:00
Jim Grosbach 5476a274c8 More binary encoding stuff, taking advantage of the new "by name" operand 
matching in tblgen to do the predicate operand.

llvm-svn: 116213
 2010-10-11 18:51:51 +00:00
Jim Grosbach 233b3a2f95 Add a 'pattern' arg to the ARM PseudoNeonI class. 
llvm-svn: 115831
 2010-10-06 20:36:55 +00:00
Chris Lattner 04c342ea20 replace stuff like: 
let AsmString = !strconcat(
                     !strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)),
                     !strconcat("\t", asm));

with:

  let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);

:)

llvm-svn: 115720
 2010-10-06 00:05:18 +00:00
Jim Grosbach e929899a3f Increase the number of bits used internally by the ARM target to represent the 
addressing mode from four to five.

llvm-svn: 115645
 2010-10-05 18:14:55 +00:00
Bob Wilson 6b853c3ce3 Change VLDMQ and VSTMQ to be pseudo instructions. They are expanded after 
register allocation to VLDMD and VSTMD respectively.  This avoids using the
dregpair operand modifier.

llvm-svn: 114047
 2010-09-16 00:31:02 +00:00
Bob Wilson c597fd3b4a Convert some VTBL and VTBX instructions to use pseudo instructions prior to 
register allocation.  Remove the NEONPreAllocPass, which is no longer needed.
Yeah!!

llvm-svn: 113818
 2010-09-13 23:55:10 +00:00
Jim Grosbach abcbe2474d VFP/NEON load/store multiple instructions are addrmode4, not 5. 
llvm-svn: 113322
 2010-09-08 00:25:50 +00:00