Commit Graph

17890 Commits

Author SHA1 Message Date
Michael J. Spencer 9973738b65 Add pentium{3,4}m cpus. Patch by Alexander Best!
llvm-svn: 130749
2011-05-03 03:42:50 +00:00
Eric Christopher d2aa241378 xmm0 is an implicit parameter in this and so shouldn't be in the
string template.

Fixes rdar://8493866

llvm-svn: 130747
2011-05-03 01:28:32 +00:00
Dan Gohman 6136e94897 Add an unfolded offset field to LSR's Formula record. This is used to
model constants which can be added to base registers via add-immediate
instructions which don't require an additional register to materialize
the immediate.

llvm-svn: 130743
2011-05-03 00:46:49 +00:00
Eric Christopher 39b56b4b9f Apparently the check for direct calls is unnecessary.
llvm-svn: 130716
2011-05-02 20:16:33 +00:00
Rafael Espindola 5164e6e8b2 Add 130690 back.
llvm-svn: 130693
2011-05-02 15:58:16 +00:00
Rafael Espindola a392475865 Revert while I debug the tests that use march but not mtriple.
llvm-svn: 130691
2011-05-02 15:42:31 +00:00
Rafael Espindola c2aad4f2a3 Move ppc OS X to cfi too. I am building it on an old ppc mini, but it will take some time.
llvm-svn: 130690
2011-05-02 15:00:52 +00:00
Rafael Espindola fc8223670a Add r130623 back now that ELF has been fixed to work with -fno-dwarf2-cfi-asm.
llvm-svn: 130658
2011-05-01 15:44:13 +00:00
Chandler Carruth ddc91b25e3 Remove an unused variable from this function introduced in r130637,
likely a result of copy/paste.

llvm-svn: 130640
2011-05-01 06:14:10 +00:00
Rafael Espindola 750cb61553 GCC uses a different encoding of pointers in the FDE when using
-fno-dwarf2-cfi-asm. Implement the same behavior.

llvm-svn: 130637
2011-05-01 04:49:54 +00:00
Rafael Espindola 95215a76cd I forgot these files in the previous commit.
llvm-svn: 130635
2011-05-01 04:19:24 +00:00
Rafael Espindola fd05785324 Simplify the handling of pcrel relocations on ELF. Now we do the right thing
for all symbol differences and can drop the old EmitPCRelSymbolValue
method.

This also make getExprForFDESymbol on ELF equal to the one on MachO, and it
can be made non-virtual.

llvm-svn: 130634
2011-05-01 03:50:49 +00:00
Rafael Espindola b7c2286055 Revert the previous patch while I figure out how to make llvm-gcc
less agressive about disabling cfi on linux :-(

llvm-svn: 130626
2011-04-30 23:03:44 +00:00
Jakob Stoklund Olesen 2348cdd67f X86AsmPrinter doesn't know how to handle the X86II::MO_GOT_ABSOLUTE_ADDRESS flag
after folding ADD32ri to ADD32mi, so don't do that.

This only happens when the greedy register allocator gets itself in trouble and
spills %vreg9 here:

16L             %vreg9<def> = MOVPC32r 0, %ESP<imp-use>; GR32:%vreg9
48L             %vreg9<def> = ADD32ri %vreg9, <es:_GLOBAL_OFFSET_TABLE_>[TF=1], %EFLAGS<imp-def,dead>; GR32:%vreg9

That should never happen, the live range should be split instead.

llvm-svn: 130625
2011-04-30 23:00:05 +00:00
Rafael Espindola 5265bc483e Enable CFI on OS X.
Currently the output should be almost identical to the one produced by CodeGen
to make the transition easier.

The only two differences I know of are:

* Some files get an extra advance loc of size 0. This will be fixed when
relaxations are enabled.
* The optimization of declaring an EH symbol as an external variable is not
implemented. This is a subset of adding the nounwind attribute, so we if really
this at -O0 we should probably do it at the IL level.

llvm-svn: 130623
2011-04-30 22:29:54 +00:00
Rafael Espindola a3181d12c6 Add all the plumbing needed for MC to expand cfi to the old tables in
the final assembly. It is the same technique used when targeting
assemblers that don't support .loc.

llvm-svn: 130587
2011-04-30 03:44:37 +00:00
Eric Christopher e02e07c3a6 80-col.
llvm-svn: 130558
2011-04-29 23:12:01 +00:00
Eli Friedman 468dfabce0 Zap a couple now-unused functions.
llvm-svn: 130557
2011-04-29 22:56:48 +00:00
Eli Friedman 328bad02fa Switch to ImmLeaf (which can be used by FastISel) for a few more common ARM/Thumb2 patterns.
llvm-svn: 130552
2011-04-29 22:48:03 +00:00
Eric Christopher 7708746c33 Add FastEmitInst_ii for the arm fast isel generator. It doesn't use it, but
if it ever did it needs the def machinery.

llvm-svn: 130549
2011-04-29 22:07:50 +00:00
Eric Christopher 26b8ac4b8c Some cleanup and optimize fallthrough more.
llvm-svn: 130546
2011-04-29 21:56:31 +00:00
Eli Friedman 86caced370 Re-committing r130454, which does not in fact break anything.
Fix a rather obscure crash caused by ARM fast-isel generating code which redefines a register.
rdar://problem/9338332 .

llvm-svn: 130539
2011-04-29 21:22:56 +00:00
Eric Christopher 8d46b47787 Add trunc->branch support, this won't help with clang's i8->i1 truncations
for bools, but is a start.

llvm-svn: 130534
2011-04-29 20:02:39 +00:00
Daniel Dunbar dc3e4cc5ed MCExpr: Add FindAssociatedSection, which attempts to mirror the 'as' semantics
that associate sections with expressions.

llvm-svn: 130517
2011-04-29 18:00:03 +00:00
Andrew Trick e794e17524 Teach Thumb2 isel to fold and->rotr ==> ROR.
Generalization of Nate Begeman's patch!

llvm-svn: 130502
2011-04-29 14:18:15 +00:00
Benjamin Kramer 6708499b6d This is done.
llvm-svn: 130499
2011-04-29 14:09:57 +00:00
Chris Lattner 011eae7512 clean up after Sean's r127646 patch.
llvm-svn: 130475
2011-04-29 05:40:18 +00:00
Chris Lattner 1d0c25756e use the MachineInstrBuilder operator-> to simplify some code.
There are probably more instances of this floating around.

llvm-svn: 130474
2011-04-29 05:24:29 +00:00
Eric Christopher 9ade5e2495 Update comments and checks to match reality.
llvm-svn: 130464
2011-04-29 00:07:20 +00:00
Eric Christopher 501d2e2c14 Whitespace.
llvm-svn: 130463
2011-04-29 00:03:10 +00:00
Eli Friedman 517728b1ae Revert r130454; apparently this doesn't actually work.
llvm-svn: 130462
2011-04-28 23:55:14 +00:00
Eli Friedman e4ecd42926 Fix a rather obscure crash caused by ARM fast-isel generating code which redefines a register.
rdar://problem/9338332 .

llvm-svn: 130454
2011-04-28 23:03:25 +00:00
Daniel Dunbar a86188bf8e Target/X86/MC: Add an option for disabling arith relaxation, for my own testing
purposes.

llvm-svn: 130438
2011-04-28 21:23:31 +00:00
Eli Friedman 7cd5101ad3 fast-isel sret calls, try 2. We actually do need to do something on x86-32. rdar://problem/9303592 .
llvm-svn: 130429
2011-04-28 20:19:12 +00:00
Eli Friedman d5a80ca3c8 Revert r130348; causing buildbot issues on x86-32.
llvm-svn: 130412
2011-04-28 18:06:10 +00:00
Eric Christopher 4f012fd0a1 Be more layout aware here and swap the successor and branch condition
if it means we get a fallthrough.

llvm-svn: 130404
2011-04-28 16:52:09 +00:00
Rafael Espindola c5dac4df2e Add a getExprForPersonalitySymbol method to MCAsmInfo. Use it when
converting the symbol passed to .cfi_personality into bytes is the file.

llvm-svn: 130400
2011-04-28 16:09:09 +00:00
Eric Christopher a98cd22d96 Let the immediate leaf pattern take transforms and switch the signed
immediate patterns in arm to using the pattern.

Handles rdar://9299434

llvm-svn: 130386
2011-04-28 05:49:04 +00:00
Chris Lattner 2a75c72e1c move PR9803 to this readme.
llvm-svn: 130385
2011-04-28 05:33:16 +00:00
Devang Patel 3e021533cd Teach dwarf writer to handle complex address expression for .debug_loc entries.
This fixes clang generated blocks' variables' debug info.
Radar 9279956.

llvm-svn: 130373
2011-04-28 02:22:40 +00:00
Justin Holewinski 45c30df303 PTX: support for select_cc and fixes for setcc
- expansion of SELECT_CC into SETCC
- force SETCC result type to i1
- custom selection for handling i1 using SETCC

Patch by Dan Bailey

llvm-svn: 130358
2011-04-28 00:19:56 +00:00
Justin Holewinski 498f703d84 PTX: support for select
- selection of SELP instruction
- new selp.ll test

Patch by Dan Bailey

llvm-svn: 130357
2011-04-28 00:19:55 +00:00
Justin Holewinski e7d272e68b PTX: mov fix and rounding correction for cvt
- fix typo in MOV
- correct fp rounding on CVT
- new cvt.ll test

Patch by Dan Bailey

llvm-svn: 130356
2011-04-28 00:19:54 +00:00
Justin Holewinski f6880019d1 PTX: support for fneg
- selection of FNEG instruction
- new fneg.ll test

Patch by Dan Bailey

llvm-svn: 130355
2011-04-28 00:19:53 +00:00
Justin Holewinski 99e03f1943 PTX: support for zext loads and trunc stores
- expansion of EXTLOAD and TRUNCSTORE instructions

Patch by Dan Bailey

llvm-svn: 130354
2011-04-28 00:19:52 +00:00
Justin Holewinski 18e6ac83ea PTX: support for bitwise operations on predicates
- selection of bitwise preds (AND, OR, XOR)
- new bitwise.ll test

Patch by Dan Bailey

llvm-svn: 130353
2011-04-28 00:19:51 +00:00
Justin Holewinski 638f0eb116 PTX: patch to AsmPrinter
- immediate value cast as long not int
- handles initializer for constant array

Patch by Dan Bailey

llvm-svn: 130352
2011-04-28 00:19:50 +00:00
Eli Friedman 8bd572fc58 fast-isel sret. We actually don't need to do anything special on x86. :) rdar://problem/9303592 .
llvm-svn: 130348
2011-04-27 23:58:52 +00:00
Rafael Espindola ce83fc3463 Remove unnecessary argument.
llvm-svn: 130343
2011-04-27 23:17:57 +00:00
Rafael Espindola 08704349da Rename getPersonalityPICSymbol to getCFIPersonalitySymbol, document it, and
give it a bit more responsibility. Also implement it for MachO.

If hacked to use cfi, 32 bit MachO will produce

.cfi_personality 155, L___gxx_personality_v0$non_lazy_ptr

and 64 bit will produce

.cfi_presonality ___gxx_personality_v0

The general idea is that .cfi_personality gets passed the final symbol. It is
up to codegen to produce it if using indirect representation (like 32 bit
MachO), but it is up to MC to decide which relocations to create.

llvm-svn: 130341
2011-04-27 23:08:15 +00:00
Eli Friedman 406c471b69 Make the fast-isel code for literal 0.0 a bit shorter/faster, since 0.0 is common. rdar://problem/9303592 .
llvm-svn: 130338
2011-04-27 22:41:55 +00:00
Kevin Enderby 886894cb70 Fix a bug in the case that there is no add or subtract symbol and the offset
value is zero so it does not add a NULL expr operand.

llvm-svn: 130330
2011-04-27 21:02:27 +00:00
Devang Patel e3745fdcf3 Revert r130178. It turned out to be not the optimal path to emit complex location expressions.
llvm-svn: 130326
2011-04-27 20:29:27 +00:00
Eli Friedman bcc6914146 Refactor out code to fast-isel a memcpy operation with a small constant
length.  (I'm planning to use this to implement byval.)

llvm-svn: 130274
2011-04-27 01:45:07 +00:00
Eli Friedman 0eea0293d9 Fix an edge case involving branches in fast-isel on x86.
rdar://problem/9303306 .

llvm-svn: 130272
2011-04-27 01:34:27 +00:00
Chris Lattner 1b06c71668 Transform: "icmp eq (trunc (lshr(X, cst1)), cst" to "icmp (and X, mask), cst"
when X has multiple uses.  This is useful for exposing secondary optimizations,
but the X86 backend isn't ready for this when X has a single use.  For example,
this can disable load folding.

This is inching towards resolving PR6627.

llvm-svn: 130238
2011-04-26 20:18:20 +00:00
Jim Grosbach d4b733e4d8 ARM and Thumb2 support for atomic MIN/MAX/UMIN/UMAX loads.
rdar://9326019

llvm-svn: 130234
2011-04-26 19:44:18 +00:00
Jakob Stoklund Olesen 803a200077 Add a TRI::getLargestLegalSuperClass hook to provide an upper limit on register class inflation.
The hook will be used by the register allocator when recomputing register
classes after removing constraints.

Thumb1 code doesn't allow anything larger than tGPR, and x86 needs to ensure
that the spill size doesn't change.

llvm-svn: 130228
2011-04-26 18:52:33 +00:00
Rafael Espindola 80cb3cb1d6 Print all the moves at a given label instead of just the first one.
Remove previous DwarfCFI hack.

llvm-svn: 130187
2011-04-26 03:58:56 +00:00
Devang Patel cae2fbd6fc Let dwarf writer allocate extra space in the debug location expression. This space, if requested, will be used for complex addresses of the Blocks' variables.
llvm-svn: 130178
2011-04-26 00:12:46 +00:00
Chris Lattner 6e29892430 add a missed bitfield instcombine.
llvm-svn: 130137
2011-04-25 18:44:26 +00:00
Akira Hatanaka 0e7ee666b7 Lower BlockAddress node when relocation-model is static.
llvm-svn: 130131
2011-04-25 17:10:45 +00:00
Chandler Carruth 9b73c8e293 Remove some hard coded CR-LFs. Some of these were the entire files, one of
these was just one line of a file. Explicitly set the eol-style property on the
files to try and ensure this fix stays.

llvm-svn: 130125
2011-04-25 07:11:23 +00:00
Duncan Sands 56ca6292dc Fix comment typo. Noticed by Liu.
llvm-svn: 130120
2011-04-25 06:21:43 +00:00
Sebastian Redl 5519ff9d4e Fix Target/ARM/Thumb1FrameLowering.h header guard.
llvm-svn: 130097
2011-04-24 15:47:01 +00:00
Jay Foad 1a180156b6 Remove unused STL header includes.
llvm-svn: 130068
2011-04-23 19:53:52 +00:00
Benjamin Kramer 3db054650b Silence an overzealous uninitialized variable warning from GCC.
llvm-svn: 130053
2011-04-23 08:21:06 +00:00
Andrew Trick 0ed5778a1e Thumb2 and ARM add/subtract with carry fixes.
Fixes Thumb2 ADCS and SBCS lowering: <rdar://problem/9275821>.
t2ADCS/t2SBCS are now pseudo instructions, consistent with ARM, so the
assembly printer correctly prints the 's' suffix.

Fixes Thumb2 adde -> SBC matching to check for live/dead carry flags.

Fixes the internal ARM machine opcode mnemonic for ADCS/SBCS.
Fixes ARM SBC lowering to check for live carry (potential bug).

llvm-svn: 130048
2011-04-23 03:55:32 +00:00
Andrew Trick 1a1f8d4640 whitespace
llvm-svn: 130046
2011-04-23 03:24:11 +00:00
Johnny Chen 57c892860e Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) should
print out ldr, not ldr.n.

rdar://problem/9267772

llvm-svn: 130008
2011-04-22 19:12:43 +00:00
Benjamin Kramer 341c11da3b DAGCombine: fold "(zext x) == C" into "x == (trunc C)" if the trunc is lossless.
On x86 this allows to fold a load into the cmp, greatly reducing register pressure.
  movzbl	(%rdi), %eax
  cmpl	$47, %eax
->
  cmpb	$47, (%rdi)

This shaves 8k off gcc.o on i386. I'll leave applying the patch in README.txt to Chris :)

llvm-svn: 130005
2011-04-22 18:47:44 +00:00
Devang Patel 3c39ec2933 Add asserts.
llvm-svn: 129995
2011-04-22 16:44:29 +00:00
Benjamin Kramer 4c81624735 X86: Try to use a smaller encoding by transforming (X << C1) & C2 into (X & (C2 >> C1)) & C1. (Part of PR5039)
This tends to happen a lot with bitfield code generated by clang. A simple example for x86_64 is
uint64_t foo(uint64_t x) { return (x&1) << 42; }
which used to compile into bloated code:
	shlq	$42, %rdi               ## encoding: [0x48,0xc1,0xe7,0x2a]
	movabsq	$4398046511104, %rax    ## encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00]
	andq	%rdi, %rax              ## encoding: [0x48,0x21,0xf8]
	ret                             ## encoding: [0xc3]

with this patch we can fold the immediate into the and:
	andq	$1, %rdi                ## encoding: [0x48,0x83,0xe7,0x01]
	movq	%rdi, %rax              ## encoding: [0x48,0x89,0xf8]
	shlq	$42, %rax               ## encoding: [0x48,0xc1,0xe0,0x2a]
	ret                             ## encoding: [0xc3]

It's possible to save another byte by using 'andl' instead of 'andq' but I currently see no way of doing
that without making this code even more complicated. See the TODOs in the code.

llvm-svn: 129990
2011-04-22 15:30:40 +00:00
Evan Cheng c0d2004e3c In Thumb2 mode, lower frame indix references to:
add <rd>, sp, #<imm8>
ldr <rd>, [sp, #<imm8>]
When the offset from sp is multiple of 4 and in range of 0-1020.
This saves code size by utilizing 16-bit instructions.

rdar://9321541

llvm-svn: 129971
2011-04-22 01:42:52 +00:00
Rafael Espindola 5395f44fe8 Compute the size of the FDE encoding instead of hard coding it. Update
X8664_ELFTargetObjectFile::getFDEEncoding to match reality.

llvm-svn: 129959
2011-04-22 00:08:43 +00:00
Rafael Espindola 6aea59268a Remove unused argument.
llvm-svn: 129955
2011-04-21 23:39:26 +00:00
Devang Patel 94ad6ac13c Fix DWARF description of Q registers.
llvm-svn: 129952
2011-04-21 23:22:35 +00:00
Devang Patel 3712c14be9 Fix DWARF description of S registers.
llvm-svn: 129947
2011-04-21 22:48:26 +00:00
Devang Patel 46bda61a81 As per ARM docs, register Dx is described as DW_OP_regx(256+x) in DWARF.
llvm-svn: 129922
2011-04-21 17:51:06 +00:00
Justin Holewinski d74d88a861 PTX: Expand useable register space
llvm-svn: 129913
2011-04-21 16:08:02 +00:00
Che-Liang Chiou 14c48e5d66 ptx: fix parameter ordering
This patch depends on the prior fix r129908 that changes to use std::find,
rather than std::binary_search, on unordered array.

Patch by Dan Bailey

llvm-svn: 129909
2011-04-21 10:56:58 +00:00
Che-Liang Chiou cdc51569ee ptx: PTXMachineFunctionInfo no longer sort registers and so should not use std::binary_search
llvm-svn: 129908
2011-04-21 10:16:20 +00:00
Evan Cheng 5f1ba4cd2d Remove -use-divmod-libcall. Let targets opt in when they are available.
llvm-svn: 129884
2011-04-20 22:20:12 +00:00
Eli Friedman c93d399eed Revert r129846; it's breaking a buildbot. See
http://google1.osuosl.org:8011/builders/llvm-x86_64-linux-checks/builds/825/steps/test.llvm.stage2/logs/st.ll

llvm-svn: 129869
2011-04-20 19:00:08 +00:00
Jakob Stoklund Olesen 0e34c1dfac Prefer cheap registers for busy live ranges.
On the x86-64 and thumb2 targets, some registers are more expensive to encode
than others in the same register class.

Add a CostPerUse field to the TableGen register description, and make it
available from TRI->getCostPerUse. This represents the cost of a REX prefix or a
32-bit instruction encoding required by choosing a high register.

Teach the greedy register allocator to prefer cheap registers for busy live
ranges (as indicated by spill weight).

llvm-svn: 129864
2011-04-20 18:19:48 +00:00
Stuart Hastings 7850af6ea0 Excise unintended hunk in 129858. <rdar://problem/7662569>
llvm-svn: 129862
2011-04-20 18:09:26 +00:00
Stuart Hastings 45fe3c38c5 ARM byval support. Will be enabled by another patch to the FE. <rdar://problem/7662569>
llvm-svn: 129858
2011-04-20 16:47:52 +00:00
Justin Holewinski 7d8895e767 PTX: Add intrinsics to list of built-in intrinsics, which allows them to be
used by Clang.  To help Clang integration, the PTX target has been split
     into two targets: ptx32 and ptx64, depending on the desired pointer size.

- Add GCCBuiltin class to all intrinsics
- Split PTX target into ptx32 and ptx64

llvm-svn: 129851
2011-04-20 15:37:17 +00:00
Che-Liang Chiou 6586f84685 ptx: add integer div and rem instruction
Patched by Dan Bailey

llvm-svn: 129848
2011-04-20 09:28:55 +00:00
Che-Liang Chiou 5a952b3c67 ptx: add floating-point comparison to setp
Patched by Dan Bailey

llvm-svn: 129847
2011-04-20 09:28:20 +00:00
Che-Liang Chiou 49160f9a71 ptx: fix parameter ordering
Patched by Dan Bailey

llvm-svn: 129846
2011-04-20 09:27:19 +00:00
Nick Lewycky 4dae63e35b This should always be signed chars, so use int8_t. This fixes a miscompile when
llvm is built with unsigned chars where an immediate such as 0xff would be zero
extended to 64-bits, turning "cmp $0xff,%eax" into
"cmp $0xffffffffffffffff,%eax".

llvm-svn: 129845
2011-04-20 03:19:42 +00:00
Rafael Espindola e473aaf540 Remove unused arguments.
llvm-svn: 129844
2011-04-20 03:08:09 +00:00
Daniel Dunbar cd01ed5bd6 ADT/Triple: Renambe isOSX... methods to isMacOSX for consistency with the OS
triple component.

llvm-svn: 129838
2011-04-20 00:14:25 +00:00
Johnny Chen dc62e59776 Fix typo in the comment.
llvm-svn: 129837
2011-04-19 23:58:52 +00:00
Daniel Dunbar 2b9b0e3748 ADT/Triple: Move a variety of clients to using isOSDarwin() and isOSWindows()
predicates.

llvm-svn: 129816
2011-04-19 21:14:45 +00:00
Daniel Dunbar 100455a3c8 Target/X86: Eliminate uses of getDarwinVers().
llvm-svn: 129813
2011-04-19 21:04:12 +00:00
Daniel Dunbar 44b530369d Target/X86: Add getTargetTriple() accessor.
llvm-svn: 129812
2011-04-19 21:01:47 +00:00
Daniel Dunbar e3de896b5e Target/PPC: Kill off DarwinVers, which is now dead.
llvm-svn: 129811
2011-04-19 20:59:24 +00:00
Daniel Dunbar f954a0f028 Target/PPC: Eliminate a use of getDarwinVers().
llvm-svn: 129810
2011-04-19 20:57:03 +00:00
Daniel Dunbar a37aab2515 Target/PPC: Add a TargetTriple field.
llvm-svn: 129809
2011-04-19 20:54:28 +00:00
Daniel Dunbar 9483bb6bf3 Target: Eliminate a use of getDarwinMajorNumber().
llvm-svn: 129803
2011-04-19 20:44:08 +00:00
Eric Christopher c721b0db6d Remove some duplicate op action entries and reorganize.
llvm-svn: 129781
2011-04-19 18:49:19 +00:00
Bob Wilson 0858c3aaed This patch combines several changes from Evan Cheng for rdar://8659675.
Making use of VFP / NEON floating point multiply-accumulate / subtraction is
difficult on current ARM implementations for a few reasons.
1. Even though a single vmla has latency that is one cycle shorter than a pair
   of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause
   additional pipeline stall. So it's frequently better to single codegen
   vmul + vadd.
2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to
   stall for 4 cycles. We need to schedule them apart.
3. A vmla followed vmla is a special case. Obvious issuing back to back RAW
   vmla + vmla is very bad. But this isn't ideal either:
     vmul
     vadd
     vmla
   Instead, we want to expand the second vmla:
     vmla
     vmul
     vadd
   Even with the 4 cycle vmul stall, the second sequence is still 2 cycles
   faster.

Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough
but it isn't the optimial solution. This patch attempts to make it possible to
use vmla / vmls in cases where it is profitable.

A. Add missing isel predicates which cause vmla to be codegen'ed.
B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to
   compute a fmul and a fmla.
C. Add additional isel checks for vmla, avoid cases where vmla is feeding into
   fp instructions (except for the #3 exceptional case).
D. Add ARM hazard recognizer to model the vmla / vmls hazards.
E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the
   vmla / vmls will trigger one of the special hazards.

Enable these fp vmlx codegen changes for Cortex-A9.

llvm-svn: 129775
2011-04-19 18:11:57 +00:00
Bob Wilson d04a83f8f2 Add -mcpu=cortex-a9-mp. It's cortex-a9 with MP extension. rdar://8648637.
llvm-svn: 129774
2011-04-19 18:11:52 +00:00
Bob Wilson a2881ee8a4 Avoid some 's' 16-bit instruction which partially update CPSR
(and add false dependency) when it isn't dependent on last CPSR defining
instruction. rdar://8928208

llvm-svn: 129773
2011-04-19 18:11:49 +00:00
Bob Wilson df612ba006 Avoid write-after-write issue hazards for Cortex-A9.
Add a avoidWriteAfterWrite() target hook to identify register classes that
suffer from write-after-write hazards. For those register classes, try to avoid
writing the same register in two consecutive instructions.

This is currently disabled by default.  We should not spill to avoid hazards!
The command line flag -avoid-waw-hazard can be used to enable waw avoidance.

llvm-svn: 129772
2011-04-19 18:11:45 +00:00
Bob Wilson 3e5944d96b Some single-precision VFP instructions can execute in either the VPF or Neon
pipelines, at least on Cortex-A9.

llvm-svn: 129771
2011-04-19 18:11:38 +00:00
Bob Wilson f33715e554 Improvements for the Cortex-A9 scheduling itineraries.
llvm-svn: 129770
2011-04-19 18:11:36 +00:00
Eli Friedman ee92a6b332 Add support for FastISel'ing varargs calls.
llvm-svn: 129765
2011-04-19 17:22:22 +00:00
Chris Lattner 91328b317b Implement support for x86 fastisel of small fixed-sized memcpys, which are generated
en-mass for C++ PODs.  On my c++ test file, this cuts the fast isel rejects by 10x 
and shrinks the generated .s file by 5%

llvm-svn: 129755
2011-04-19 05:52:03 +00:00
Chris Lattner 34a08c2344 tidy up
llvm-svn: 129753
2011-04-19 05:15:59 +00:00
Chris Lattner 5f4b783426 Implement support for fast isel of calls of i1 arguments, even though they are illegal,
when they are a truncate from something else.  This eliminates fully half of all the 
fastisel rejections on a test c++ file I'm working with, which should make a substantial
improvement for -O0 compile of c++ code.

This fixed rdar://9297003 - fast isel bails out on all functions taking bools

llvm-svn: 129752
2011-04-19 05:09:50 +00:00
Chris Lattner d7f7c93914 Handle i1/i8/i16 constant integer arguments to calls by prepromoting them.
Before we would bail out on i1 arguments all together, now we just bail on
non-constant ones.  Also, we used to emit extraneous code.  e.g. test12 was:

	movb	$0, %al
	movzbl	%al, %edi
	callq	_test12

and test13 was:
	movb	$0, %al
	xorl	%edi, %edi
	movb	%al, 7(%rsp)
	callq	_test13f

Now we get:

	movl	$0, %edi
	callq	_test12
and:
	movl	$0, %edi
	callq	_test13f

llvm-svn: 129751
2011-04-19 04:42:38 +00:00
Chris Lattner c59290a34c be layout aware, to produce:
testb	$1, %al
	je	LBB0_2
## BB#1:                                ## %if.then
	movb	$0, %al

instead of:

	testb	$1, %al
	jne	LBB0_1
	jmp	LBB0_2
LBB0_1:                                 ## %if.then
	movb	$0, %al

how 'bout that.

llvm-svn: 129749
2011-04-19 04:26:32 +00:00
Chris Lattner 2c8a4c3b1b fix rdar://9297006 - fast isel bails out on trunc to i1 -> bools cry,
a common cause of fast isel rejects on c++ code.

llvm-svn: 129748
2011-04-19 04:22:17 +00:00
Evan Cheng 7d6cd4902e Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That
is, it assumes addresses are 64-bit aligned (which should be the more common
case). If the alignment is found not to be aligned, then getOperandLatency()
would adjust the operand latency computation by one to compensate for it.
rdar://9294833

llvm-svn: 129742
2011-04-19 01:21:49 +00:00
Evan Cheng 4079133796 Do not lose mem_operands while lowering VLD / VST intrinsics.
llvm-svn: 129738
2011-04-19 00:04:03 +00:00
Jim Grosbach ddac5dd269 Trim a few unneeded includes.
llvm-svn: 129723
2011-04-18 21:35:54 +00:00
Eric Christopher 2e3fbaab39 Invert the meaning of printAliasInstr's return value. It now returns
true on success and false on failure. Update callers.

llvm-svn: 129722
2011-04-18 21:28:11 +00:00
Sean Callanan 5d73033e0f Small fix to the ARM AsmParser to ensure that a
superclass variable is instantiated properly.

llvm-svn: 129713
2011-04-18 20:20:44 +00:00
Chris Lattner 80254a53cc Add a new bit that ImmLeaf's can opt into, which allows them to duck out of
the generated FastISel.  X86 doesn't need to generate code to match ADD16ri8 
since ADD16ri will do just fine.  This is a small codesize win in the generated
instruction selector.

llvm-svn: 129692
2011-04-18 06:36:55 +00:00
Chris Lattner c479e0631f switch the rest of the x86 immediate patterns over to ImmLeaf,
simplifying them and exposing more information to tblgen.  It would be nice
if other target authors adopted this as well, particularly arm since it has fastisel.

llvm-svn: 129676
2011-04-17 22:12:55 +00:00
Chris Lattner 2ff8c1a25f now that predicates have a decent abstraction layer on them, introduce a new
kind of predicate: one that is specific to imm nodes.  The predicate function
specified here just checks an int64_t directly instead of messing around with
SDNode's.  The virtue of this is that it means that fastisel and other things
can reason about these predicates.

llvm-svn: 129675
2011-04-17 22:05:17 +00:00
Chris Lattner 514e292b72 Rework our internal representation of node predicates to expose more
structure and fix some fixmes.  We now have a TreePredicateFn class
that handles all of the decoding of these things.  This is an internal
cleanup that has no impact on the code generated by tblgen.

llvm-svn: 129670
2011-04-17 21:38:24 +00:00
Chris Lattner b53ccb8e36 1. merge fast-isel-shift-imm.ll into fast-isel-x86-64.ll
2. implement rdar://9289501 - fast isel should fold trivial multiplies to shifts
3. teach tblgen to handle shift immediates that are different sizes than the 
   shifted operands, eliminating some code from the X86 fast isel backend.
4. Have FastISel::SelectBinaryOp use (the poorly named) FastEmit_ri_ function
   instead of FastEmit_ri to simplify code.

llvm-svn: 129666
2011-04-17 20:23:29 +00:00
Chris Lattner eb729d48ff fix an x86 fast isel issue where we'd completely give up on folding an address
when we have a global variable base an an index.  Instead, just give up on
folding the global variable.

Before we'd geenrate:

_test:                                  ## @test
## BB#0:
	movq	_rtx_length@GOTPCREL(%rip), %rax
	leaq	(%rax), %rax
	addq	%rdi, %rax
	movzbl	(%rax), %eax
	ret

now we generate:

_test:                                  ## @test
## BB#0:
	movq	_rtx_length@GOTPCREL(%rip), %rax
	movzbl	(%rax,%rdi), %eax
	ret

The difference is even more significant when there is a scale
involved.

This fixes rdar://9289558 - total fail with addr mode formation at -O0/x86-64

llvm-svn: 129664
2011-04-17 17:47:38 +00:00
Chris Lattner 4832660b4d fix an oversight which caused us to compile the testcase (and other
less trivial things) into a dummy lea.  Before we generated:

_test:                                  ## @test
	movq	_G@GOTPCREL(%rip), %rax
	leaq	(%rax), %rax
	ret

now we produce:

_test:                                  ## @test
	movq	_G@GOTPCREL(%rip), %rax
	ret

This is part of rdar://9289558

llvm-svn: 129662
2011-04-17 17:12:08 +00:00
Chris Lattner 4b026b962a tidy up and reduce indentation.
llvm-svn: 129661
2011-04-17 17:05:12 +00:00
Eli Friedman 55f7bf3289 Remove working entry from README.
llvm-svn: 129654
2011-04-17 02:36:27 +00:00
Francois Pichet 47f86e6c60 MSVC needs the return 0 to compile.
llvm-svn: 129640
2011-04-16 13:59:23 +00:00
Rafael Espindola a83b177035 Put each personality function in a section. This fixes the gnu ld warning:
error in foo.o; no .eh_frame_hdr table will be created.

llvm-svn: 129635
2011-04-16 03:51:21 +00:00
Stuart Hastings ebddfe60a0 Correct result when a branch condition is live across a block
boundary.  <rdar://problem/8933028>

llvm-svn: 129634
2011-04-16 03:31:26 +00:00
Johnny Chen 48592ee5af Thumb2 BFC was insufficiently encoded.
rdar://problem/9292717

llvm-svn: 129619
2011-04-15 22:52:15 +00:00
Johnny Chen 761e1e3512 A8.6.315 VLD3 (single 3-element structure to all lanes)
The a bit must be encoded as 0.

rdar://problem/9292625

llvm-svn: 129618
2011-04-15 22:49:08 +00:00
Akira Hatanaka e24891251c Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality.
llvm-svn: 129612
2011-04-15 21:51:11 +00:00
Cameron Zwarich 9c65e4d69c Add ORR and EOR to the CMP peephole optimizer. It's hard to get isel to generate
a case involving EOR, so I only added a test for ORR.

llvm-svn: 129610
2011-04-15 21:24:38 +00:00
Akira Hatanaka d56f2d910b Fix lines that exceed 80 columns. There is no change in functionality.
llvm-svn: 129608
2011-04-15 21:06:38 +00:00
Akira Hatanaka aef55c8801 Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality.
llvm-svn: 129606
2011-04-15 21:00:26 +00:00
Cameron Zwarich 0829b3065a The AND instruction leaves the V flag unmodified, so it falls victim to the same
problem as all of the other instructions we fold with CMPs.

llvm-svn: 129602
2011-04-15 20:45:00 +00:00
Rafael Espindola 7583dbdc88 Fix cmake build.
llvm-svn: 129601
2011-04-15 20:34:45 +00:00
Cameron Zwarich 93eae1571c Add missing register forms of instructions to the ARM CMP-folding code. This
fixes <rdar://problem/9287901>.

llvm-svn: 129599
2011-04-15 20:28:28 +00:00
Akira Hatanaka 279169771b Add pass that expands pseudo instructions into target instructions after register allocation. Define pseudos that get expanded into mtc1 or mfc1 instructions.
llvm-svn: 129594
2011-04-15 19:52:08 +00:00
Evan Cheng a2e61292f0 Increase SubtargetFeatureKV Value and Implies fields to 64 bits since some targets are getting very close to 32 subtarget features. Also teach tablegen to error when there are more than 64 features to guard against undefined behavior. rdar://9282332
llvm-svn: 129590
2011-04-15 19:35:46 +00:00
Rafael Espindola a01cdb0e37 Add 129518 back with a fix for when we are producing eh just because of debug info.
Change ELF systems to use CFI for producing the EH tables. This reduces the
size of the clang binary in Debug builds from 690MB to 679MB.

llvm-svn: 129571
2011-04-15 15:11:06 +00:00
Chris Lattner 0ab5e2cded Fix a ton of comment typos found by codespell. Patch by
Luis Felipe Strano Moraes!

llvm-svn: 129558
2011-04-15 05:18:47 +00:00
NAKAMURA Takumi b5e3e9dd27 Revert r129518, "Change ELF systems to use CFI for producing the EH tables. This reduces the"
It broke several builds.

llvm-svn: 129557
2011-04-15 03:35:57 +00:00
Evan Cheng 12bb05b75b Fix another fcopysign lowering bug. If src is f64 and destination is f32, don't
forget to right shift the source by 32 first. rdar://9287902

llvm-svn: 129556
2011-04-15 01:31:00 +00:00
Johnny Chen 681fef5986 For t2BFI, both Inst{26} and Inst{5} "should" be 0.
Ref: I.1 Instruction encoding diagrams and pseudocode
llvm-svn: 129552
2011-04-15 00:35:08 +00:00
Michael J. Spencer 30088ba110 Add 3DNow! intrinsics.
llvm-svn: 129551
2011-04-15 00:32:41 +00:00
Johnny Chen 421316178e The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions
(single element or n-element structure to all lanes).

llvm-svn: 129550
2011-04-15 00:10:45 +00:00
Evan Cheng 44887f9c7e Follow up on r127913. Fix Thumb revsh isel. rdar://9286766
llvm-svn: 129548
2011-04-14 23:27:44 +00:00
Johnny Chen 4251b151b1 Add sanity checkings for Thumb2 Load/Store Register Exclusive family of operations.
llvm-svn: 129531
2011-04-14 19:13:28 +00:00
Chris Lattner 6f195469b1 move PR9661 out to here.
llvm-svn: 129527
2011-04-14 18:47:18 +00:00
Rafael Espindola aa2a7cd828 Change ELF systems to use CFI for producing the EH tables. This reduces the
size of the clang binary in Debug builds from 690MB to 679MB.

llvm-svn: 129518
2011-04-14 15:18:53 +00:00
Michael J. Spencer b88784c185 Fix whitespace and tabs.
llvm-svn: 129517
2011-04-14 14:33:36 +00:00
Chris Lattner 1d313c6f6d add a minor missed dag combine that is blocking mid-level optimization
improvements, that will lead to fixing PR6627.

llvm-svn: 129504
2011-04-14 04:21:42 +00:00
Bill Wendling 410ec4aad1 As Dan pointed out, movzbl, movsbl, and friends are nicer than their alias
(movzx/movsx) because they give more information. Revert that part of the patch.

llvm-svn: 129498
2011-04-14 01:46:37 +00:00
Bill Wendling 7e07d6fb69 Have the X86 back-end emit the alias instead of what's being aliased. In most
cases, it's much nicer and more informative reading the alias.

llvm-svn: 129497
2011-04-14 01:11:51 +00:00
Bill Wendling 6dd69d9241 Add an option to not print the alias of an instruction. It defaults to "print
the alias".

llvm-svn: 129485
2011-04-13 23:36:21 +00:00
Johnny Chen d0fb04f437 Thumb disassembler did not handle tBRIND (indirect branch) properly.
rdar://problem/9280370

llvm-svn: 129480
2011-04-13 21:59:01 +00:00
Johnny Chen b6a37bff21 Check for unallocated instruction encodings when disassembling Thumb Branch instructions (tBcc and t2Bcc).
rdar://problem/9280470

llvm-svn: 129471
2011-04-13 21:35:49 +00:00
Johnny Chen ffa6378fd6 The LDR*T/STR*T (unpriviledged load/store) operations don't take SP or PC as Rt.
rdar://problem/9279440

llvm-svn: 129469
2011-04-13 21:04:32 +00:00
Cameron Zwarich 415b5e8341 Fix a typo in an ARM-specific DAG combine. This fixes <rdar://problem/9278274>.
llvm-svn: 129468
2011-04-13 21:01:19 +00:00
Cameron Zwarich 9398197ef1 Fix a regression caused by r102515 where explicit alignment on globals is
ignored. There was a test to catch this, but it was just blindly updated in
a large change. This fixes another part of <rdar://problem/9275290>.

llvm-svn: 129466
2011-04-13 20:36:04 +00:00
Johnny Chen 70591cbc60 Check the corner cases for t2LDRSHi12 correctly and mark invalid encodings as such.
rdar://problem/9276651

llvm-svn: 129462
2011-04-13 19:46:05 +00:00
Johnny Chen 0d306a7840 Fix a bug where for t2MOVCCi disassembly, the TIED_TO register operand was not properly handled.
rdar://problem/9276427

llvm-svn: 129456
2011-04-13 17:51:02 +00:00
Johnny Chen b2f9fa1fce Forgot to add this change for http://llvm.org/viewvc/llvm-project?view=rev&revision=129387.
llvm-svn: 129451
2011-04-13 16:56:08 +00:00
Cameron Zwarich 70be27e913 Fix an obvious problem with an alignment computation. AsmPrinter actually does
the max itself, so it is not easy to write a test case for this, but I added a
test case that would fail if the code in AsmPrinter were removed.

llvm-svn: 129432
2011-04-13 09:02:43 +00:00
Cameron Zwarich 8001850ee8 Fix a typo.
llvm-svn: 129429
2011-04-13 06:39:16 +00:00
Cameron Zwarich cdf59f7016 If a global variable has a specified alignment that is less than the preferred
alignment for its type, use the minimum of the specified alignment and the ABI
alignment. This fixes <rdar://problem/9275290>.

llvm-svn: 129428
2011-04-13 06:03:16 +00:00
Bill Wendling b902f1dd88 Reapply r129401 with patch for clang.
llvm-svn: 129419
2011-04-13 00:36:11 +00:00
Johnny Chen 3c2f74c9f3 Add sanity check for Ld/St Dual forms of Thumb2 instructions.
rdar://problem/9273947

llvm-svn: 129411
2011-04-12 23:31:00 +00:00
Jakob Stoklund Olesen 987164043c Add @earlyclobber constraints to the writeback register of all ARM store instructions.
The ARMARM specifies these instructions as unpredictable when storing the
writeback register. This shouldn't affect code generation much since storing a
pointer to itself is quite rare.

llvm-svn: 129409
2011-04-12 23:27:48 +00:00
Bill Wendling dbfde42468 Revert r129401 for now. Clang is using the old way of doing things.
llvm-svn: 129403
2011-04-12 22:59:27 +00:00
Bill Wendling 47c24875a1 Remove the unaligned load intrinsics in favor of using native unaligned loads.
Now that we have a first-class way to represent unaligned loads, the unaligned
load intrinsics are superfluous.

First part of <rdar://problem/8460511>.

llvm-svn: 129401
2011-04-12 22:46:31 +00:00
Johnny Chen 960eef3db3 The Thumb2 RFE instructions need to have their second halfword fully specified.
In addition, the base register is not rGPR, but GPR with th exception that:

    if n == 15 then UNPREDICTABLE

rdar://problem/9273836

llvm-svn: 129391
2011-04-12 21:41:51 +00:00
Johnny Chen 01637b9acb Add bad register checks for Thumb2 Ld/St instructions.
rdar://problem/9269047

llvm-svn: 129387
2011-04-12 21:17:51 +00:00
Johnny Chen ab86a519f8 The Thumb2 Ld, St, and Preload instructions with the i12 forms should have its Inst{23}
be specified as '1' (add = TRUE).

Also add a utility function for Thumb2.

llvm-svn: 129377
2011-04-12 18:48:00 +00:00
Johnny Chen d0e2be39ea Print out a debug message when the reglist fails the sanity check for Thumb Ld/St Multiple.
llvm-svn: 129365
2011-04-12 17:09:04 +00:00
Cameron Zwarich fbcd69b96a Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and ARM
stores of arguments in the same cache line. This fixes the second half of
<rdar://problem/8674845>.

llvm-svn: 129345
2011-04-12 02:24:17 +00:00
Johnny Chen 672ef14a62 A8.6.16 B
Encoding T1 (tBcc)
if cond == '1110' then UNDEFINED;

rdar://problem/9268681

llvm-svn: 129325
2011-04-12 00:14:49 +00:00
Johnny Chen dc8bf9ec08 Thumb disassembler was erroneously rejecting "blx sp" instruction.
rdar://problem/9267838

llvm-svn: 129320
2011-04-11 23:33:30 +00:00
Wesley Peck f30a0e2d80 Fix an error in the MBlaze delay slot filler.
llvm-svn: 129313
2011-04-11 22:45:02 +00:00
Wesley Peck 1914c39bd4 Add scheduling information for the MBlaze backend.
llvm-svn: 129311
2011-04-11 22:31:52 +00:00
Wesley Peck e3685217d0 Don't crash on invalid instructions when disassembling MBlaze code.
This fixes http://llvm.org/bugs/show_bug.cgi?id=9653

llvm-svn: 129303
2011-04-11 21:35:21 +00:00
Johnny Chen f79d5365de Fix the bug where the immediate shift amount for Thumb logical shift instructions are incorrectly disassembled.
rdar://problem/9266265

llvm-svn: 129298
2011-04-11 21:14:35 +00:00
Owen Anderson 5140802cd9 Fix another using-CPSR-twice bug in my ADCS/SBCS cleanups, and make proper use of the Commutable bit.
llvm-svn: 129294
2011-04-11 20:12:19 +00:00
Johnny Chen 74adbddade Trivial comment fix.
llvm-svn: 129288
2011-04-11 18:51:50 +00:00
Johnny Chen 66fab75920 Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as
invalid instructions.

llvm-svn: 129286
2011-04-11 18:34:12 +00:00
Kevin Enderby 9377a52c12 Adding support for printing operands symbolically to llvm's public 'C'
disassembler API.  Hooked this up to the ARM target so such tools as Darwin's
otool(1) can now print things like branch targets for example this:
  blx _puts
instead of this:
  blx #-36
And even print the expression encoded in the Mach-O relocation entried for
things like this:
  movt r0, :upper16:((_foo-_bar)+1234)

llvm-svn: 129284
2011-04-11 18:08:50 +00:00
Jay Foad 7c14a558fe Don't include Operator.h from InstrTypes.h.
llvm-svn: 129271
2011-04-11 09:35:34 +00:00
Nicolas Geoffray 9137ee85de Bugfix in the Cpp backend after API change on PHINode::Create.
llvm-svn: 129248
2011-04-10 17:39:40 +00:00
Chris Lattner fc4fe00a65 fix rdar://8735979 - "int 3" doesn't match to "int3". Unfortunately,
InstAlias doesn't allow matching immediate operands, so we have to write
C++ code to do this.

llvm-svn: 129223
2011-04-09 19:41:05 +00:00
Matt Beaumont-Gay 4e1796e8d1 Fix an apparent typo that made GCC complain
llvm-svn: 129160
2011-04-08 21:59:49 +00:00
Evan Cheng 74d92c1924 Change -arm-trap-func= into a non-arm specific option. Now Intrinsic::trap is lowered into a call to the specified trap function at sdisel time.
llvm-svn: 129152
2011-04-08 21:37:21 +00:00
Johnny Chen f2faf4e53a Check opcoe (dmb, dsb) instead of bitfields matching.
llvm-svn: 129148
2011-04-08 20:03:46 +00:00
Johnny Chen a9570f77d5 Hanlde the checking of bad regs for SMMLAR properly, instead of asserting.
PR9650
rdar://problem/9257565

llvm-svn: 129147
2011-04-08 19:41:22 +00:00
Johnny Chen 875e0e4626 Sanity check the option operand for DMB/DSB.
PR9648
rdar://problem/9257634

llvm-svn: 129146
2011-04-08 19:18:07 +00:00
Jim Grosbach a5dcd98a47 Mark hasExtraDefRegAllocReq=1 on LDRD.
The previous cleanup of LDRD got overzealous and removed it, causing post-RA
scheduling to get overzealous in breaking antidependencies and invalidate these instructions. Hilarity and invalid assembly ensued.

rdar://9244161

llvm-svn: 129144
2011-04-08 18:47:05 +00:00
Johnny Chen 7e51b4640f Add sanity checking for bad register specifier(s) for the DPFrm instructions.
Add more test cases to exercise the logical branches related to the above change.

llvm-svn: 129117
2011-04-08 00:29:09 +00:00
Bill Wendling bc3f79044a Replace the old algorithm that emitted the "print the alias for an instruction"
with the newer, cleaner model. It uses the IAPrinter class to hold the
information that is needed to match an instruction with its alias. This also
takes into account the available features of the platform.

There is one bit of ugliness. The way the logic determines if a pattern is
unique is O(N**2), which is gross. But in reality, the number of items it's
checking against isn't large. So while it's N**2, it shouldn't be a massive time
sink.

llvm-svn: 129110
2011-04-07 21:20:06 +00:00
Evan Cheng 9a3f2772f0 Add option to emit @llvm.trap as a function call instead of a trap instruction. rdar://9249183.
llvm-svn: 129107
2011-04-07 20:31:12 +00:00
Akira Hatanaka 052163e6d3 Fix indentation.
llvm-svn: 129105
2011-04-07 20:25:10 +00:00
Akira Hatanaka 94ee37e487 Update ATUsed every time after expandRegLargeImmPair is called.
llvm-svn: 129104
2011-04-07 20:23:26 +00:00
Mon P Wang 27f3330132 Fixed encoding for VEXTqf
llvm-svn: 129101
2011-04-07 19:56:12 +00:00
Akira Hatanaka d6f1c58914 Fix handling of functions with internal linkage.
llvm-svn: 129099
2011-04-07 19:51:44 +00:00
Johnny Chen 04efb8f6ce Add sanity checking for invalid register encodings for signed/unsigned extend instructions.
Add some test cases.

llvm-svn: 129098
2011-04-07 19:28:58 +00:00
Johnny Chen 07606661f9 Add sanity checking for invalid register encodings for saturating instructions.
llvm-svn: 129096
2011-04-07 19:02:08 +00:00
Johnny Chen 194a2267ad Add some more comments about checkings of invalid register numbers.
And two test cases.

llvm-svn: 129090
2011-04-07 18:33:19 +00:00
Tanya Lattner 266792a55a Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal vector type (vectors of size 3). Also included test cases.
llvm-svn: 129074
2011-04-07 15:24:20 +00:00
Johnny Chen 313ec7953a Sanity check MSRi for invalid mask values and reject it as invalid.
rdar://problem/9246844

llvm-svn: 129050
2011-04-07 01:37:34 +00:00
Johnny Chen c0e86fb965 The ARM disassembler was not recognizing USADA8 instruction. Need to add checking for register values
for USAD8 and USADA8.

rdar://problem/9247060

llvm-svn: 129047
2011-04-07 01:05:52 +00:00
Evan Cheng a7c7b54dde Change -arm-divmod-libcall to a target neutral option.
llvm-svn: 129045
2011-04-07 00:58:44 +00:00
Johnny Chen d4cced54b3 Should also check SMLAD for invalid register values.
rdar://problem/9246650

llvm-svn: 129042
2011-04-07 00:50:25 +00:00
Owen Anderson bdff1c997a Teach the ARM peephole optimizer that RSB, RSC, ADC, and SBC can be used for folded comparisons, just like ADD and SUB.
llvm-svn: 129038
2011-04-06 23:35:59 +00:00
Owen Anderson f9bd6bad8a Cleanups from Jim: remove redundant constraints and a dead FIXME.
llvm-svn: 129036
2011-04-06 22:45:55 +00:00
Jim Grosbach 6ade7e0bac Tidy up.
llvm-svn: 129034
2011-04-06 22:35:47 +00:00
Johnny Chen bd9a4f8d07 A8.6.393
The ARM disassembler should reject invalid (type, align) encodings as invalid instructions.

So, instead of:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------

	vst2.32	{d0, d2}, [r3, :256], r3

we now have:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------

mc-input.txt:1:1: warning: invalid instruction encoding
0xb3 0x9 0x3 0xf4
^

llvm-svn: 129033
2011-04-06 22:14:48 +00:00
Johnny Chen 2ac486e387 A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP"
Since these "Advanced SIMD and VFP" instructions have more specfic encoding bits
specified, if coproc == 10 or 11, we should reject the insn as invalid.

rdar://problem/9239922
rdar://problem/9239596

llvm-svn: 129027
2011-04-06 20:49:02 +00:00
Johnny Chen 8bca174f48 Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong.
Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000,
in class NVLaneOp.

rdar://problem/9240648

llvm-svn: 129015
2011-04-06 18:27:46 +00:00
Rafael Espindola b4dd95b4f9 Add another case we are not optimizing.
llvm-svn: 129012
2011-04-06 17:35:32 +00:00
Rafael Espindola 7a3b244d45 The original issue has been fixed by not doing unnecessary sign extensions.
Change the test to force a sign extension and expose the problem again.

llvm-svn: 129011
2011-04-06 17:19:35 +00:00
Johnny Chen 0ec0e98a6a Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function.
Add more complete sanity check for LdStFrm instructions where if IBit (Inst{25})
is 1, Inst{4} should be 0.  Otherwise, we should reject the insn as invalid.

rdar://problem/9239347
rdar://problem/9239467

llvm-svn: 128977
2011-04-06 01:18:32 +00:00
Owen Anderson 867846b1f0 Reapply r128946 (pseudoization of various instructions), and fix the extra imp-def of CPSR it was adding.
llvm-svn: 128965
2011-04-05 23:55:28 +00:00
Johnny Chen f6e327c6a3 Fix a typo in the handling of PKHTB opcode, plus add sanity check for illegal register
encodings for DisassembleArithMiscFrm().

rdar://problem/9238659

llvm-svn: 128958
2011-04-05 23:28:00 +00:00
Bob Wilson d135c696c0 Clean up some code for clarity.
llvm-svn: 128953
2011-04-05 23:03:25 +00:00
Owen Anderson 61e7a935bd Revert r128946 while I figure out why it broke the buildbots.
llvm-svn: 128951
2011-04-05 23:03:06 +00:00
Johnny Chen c3656d29f6 A7.3 register encoding
Qd -> bit[12] == 0
    Qn -> bit[16] == 0
    Qm -> bit[0]  == 0

If one of these bits is 1, the instruction is UNDEFINED.

rdar://problem/9238399
rdar://problem/9238445

llvm-svn: 128949
2011-04-05 22:57:07 +00:00
Owen Anderson 3501655ad9 Give RSBS and RSCS the pseudo treatment.
llvm-svn: 128946
2011-04-05 22:42:54 +00:00
Johnny Chen 9da60e016b ARM disassembler was erroneously accepting an invalid RSC instruction.
Added checks for regs which should not be 15.

rdar://problem/9237734

llvm-svn: 128945
2011-04-05 22:18:07 +00:00
Johnny Chen 25883487a1 ARM disassembler was erroneously accepting an invalid LSL instruction.
For register-controlled shifts, we should check that the encoding constraint
Inst{7} = 0 and Inst{4} = 1 is satisfied.

rdar://problem/9237693

llvm-svn: 128941
2011-04-05 21:49:44 +00:00
Owen Anderson 77aa266de8 Fix bugs in the pseuo-ization of ADCS/SBCS pointed out by Jim, as well as doing the expansion earlier (using a custom inserter) to allow for the chance of predicating these instructions.
llvm-svn: 128940
2011-04-05 21:48:57 +00:00
Johnny Chen e9c644d4a0 The r128085 checkin modified the operand ordering for MRC/MRC2 instructions.
Modify DisassembleCoprocessor() of ARMDisassemblerCore.cpp to react to the change.

rdar://problem/9236873

llvm-svn: 128922
2011-04-05 20:32:23 +00:00
Johnny Chen 151582492d ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error.
llvm-svn: 128913
2011-04-05 19:42:11 +00:00
Jim Grosbach d9dce561b6 Make second source operand of LDRD pre/post explicit.
Finish what r128736 started.

llvm-svn: 128903
2011-04-05 18:40:13 +00:00
Johnny Chen 33d3a9fadc Constants with multiple encodings (ARM):
An alternative syntax is available for a modified immediate constant that permits the programmer to specify
the encoding directly. In this syntax, #<const> is instead written as #<byte>,#<rot>, where:

    <byte> is the numeric value of abcdefgh, in the range 0-255
    <rot> is twice the numeric value of rotation, an even number in the range 0-30.

llvm-svn: 128897
2011-04-05 18:02:46 +00:00
Johnny Chen 268d63f307 Check for invalid register encodings for UMAAL and friends where:
if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
    if dHi == dLo then UNPREDICTABLE;

rdar://problem/9230202

llvm-svn: 128895
2011-04-05 17:43:10 +00:00
Owen Anderson f7678b83d2 Convert ADCS and SBCS instructions into pseudos that are expanded to the ADC/ABC with the appropriate S-bit input value.
llvm-svn: 128892
2011-04-05 17:24:25 +00:00
Bill Wendling dd4dcd549b Revamp the SjLj "dispatch setup" intrinsic.
It needed to be moved closer to the setjmp statement, because the code directly
after the setjmp needs to know about values that are on the stack. Also, the
'bitcast' of the function context was causing a dead load. This wouldn't be too
horrible, except that at -O0 it wasn't optimized out, and because it wasn't
using the correct base pointer (if there is a VLA), it would try to access a
value from a garbage address.
<rdar://problem/9130540>

llvm-svn: 128873
2011-04-05 01:37:43 +00:00
Eric Christopher b968f4defe Just use BL all the time. It's safer that way.
Fixes rdar://9184526

llvm-svn: 128869
2011-04-05 00:39:26 +00:00
Johnny Chen 9b3ccba636 Fix SRS/SRSW encoding bits.
rdar://problem/9230801 ARM disassembler discrepancy: erroneously accepting SRS

Plus add invalid-RFEorLDMIA-arm.txt test which should have been checked in with
http://llvm.org/viewvc/llvm-project?view=rev&revision=128859.

llvm-svn: 128864
2011-04-05 00:16:18 +00:00
Johnny Chen 782a60c117 A8.6.105 MUL
Inst{15-12} should be specified as 0b0000.

rdar://problem/9231168 ARM disassembler discrepancy: erroneously accepting MUL

llvm-svn: 128862
2011-04-04 23:57:05 +00:00
Johnny Chen a6129b4a7f RFE encoding should also specify the "should be" encoding bits.
rdar://problem/9229922 ARM disassembler discrepancy: erroneously accepting RFE

Also LDC/STC instructions are predicated while LDC2/STC2 instructions are not, fixed while
doing regression testings.

llvm-svn: 128859
2011-04-04 23:39:08 +00:00
Joerg Sonnenberger 418f186a4b Make OpcodeMask an unsigned long long literal to deal with overflow.
llvm-svn: 128847
2011-04-04 21:38:17 +00:00
Johnny Chen 8372006296 Fix incorrect alignment for NEON VST2b32_UPD.
rdar://problem/9225433

llvm-svn: 128841
2011-04-04 20:35:31 +00:00
Jakob Stoklund Olesen 13ce236c4c Insert code in the right location when lowering PowerPC atomics.
This causes defs to dominate uses, no instructions after terminators, and other
goodness.

llvm-svn: 128836
2011-04-04 17:57:29 +00:00
Bruno Cardoso Lopes bda3632bcd - Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHT
also fix the encoding of the later.
- Add a new encoding bit to describe the index mode used in AM3.
- Teach printAddrMode3Operand to check by the addressing mode which
  index mode to print.
- Testcases.

llvm-svn: 128832
2011-04-04 17:18:19 +00:00
Akira Hatanaka 5ec2ead9b0 Move transformation of JmpLink and related nodes done during instruction selection to Legalize phase.
llvm-svn: 128830
2011-04-04 17:11:07 +00:00
Jakob Stoklund Olesen 86e1a65ce5 PowerPC atomic pseudos clobber CR0, they don't read it.
llvm-svn: 128829
2011-04-04 17:07:09 +00:00