542f9a2bcf
Add XCore intrinsic for crc32.
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llvm-svn: 132336
2011-05-31 14:47:36 +00:00
394f516d16
Fix ssat and ssat16 encodings for ARM and Thumb. The bit position value
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must be encoded decremented by one. Only add encoding tests for ssat16
because ssat can't be parsed yet.
llvm-svn: 132324
2011-05-31 03:33:27 +00:00
98fc4c8bbc
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor,
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nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions.
The intrinsics are implemented by creating pseudo-instructions, which are
then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter.
Patch by Sasa Stankovic.
llvm-svn: 132323
2011-05-31 02:54:07 +00:00
bf3c1251e0
This patch implements the thread local storage. Implemented are General
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Dynamic, Initial Exec and Local Exec TLS models.
Patch by Sasa Stankovic
llvm-svn: 132322
2011-05-31 02:53:58 +00:00
08600bcf65
Use the dwarf->llvm mapping to print register names in the cfi
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directives.
Fixes PR9826.
llvm-svn: 132317
2011-05-30 20:20:15 +00:00
cd0d2fd21f
Split ppc dwarf regnums into ppc64 and ppc32 flavours.
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llvm-svn: 132315
2011-05-30 18:24:44 +00:00
ddffa0e160
Introduce the DwarfRegAlias class for declaring that two registers have the
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same dwarf number. This will be used for creating a dwarf number to register
mapping.
The only case that needs this so far is the XMM/YMM registers that unfortunately
do have the same numbers.
llvm-svn: 132314
2011-05-30 17:49:59 +00:00
ea8ca34e3a
Mark the 32 bit registers as invalid in 64 bit mode. In 64 bit mode they are
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subregisters of the 64 bit ones.
llvm-svn: 132313
2011-05-30 16:04:54 +00:00
595fd7a058
Remove the DwarfNumbers from the subregisters. They should use DW_OP_bit_piece
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and for now the generic dwarf emission will automatically use the superregister
numbers.
llvm-svn: 132312
2011-05-30 15:56:04 +00:00
7d84ece09b
On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume.
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This is important for the correct lowering of unwind instructions
(which doesn't matter at all) and llvm.eh.resume calls (which does).
Take 2, now with more basic competence.
llvm-svn: 132295
2011-05-29 19:50:32 +00:00
e64371b932
I didn't mean to commit these residues of a personal project.
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llvm-svn: 132293
2011-05-29 19:41:56 +00:00
085d891d80
On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume.
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This is important for the correct lowering of unwind instructions
(which doesn't matter at all) and llvm.eh.resume calls (which does).
llvm-svn: 132291
2011-05-29 19:39:04 +00:00
0f17990f28
Fix to match the dwarf register numbers that gdb uses.
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llvm-svn: 132278
2011-05-29 03:58:16 +00:00
ccfd392c13
Dwarf register 0 is r0, remove incorrect entries.
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llvm-svn: 132276
2011-05-29 03:17:01 +00:00
fd75d45b88
Remove the dwarf numbers from the D registers. They don't have dwarf numbers
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and should probably be encoded as
DW_OP_reg 32 DW_OP_piece 4 DW_OP_reg 33
llvm-svn: 132274
2011-05-29 02:21:01 +00:00
6528a54946
Fix ARM fast isel to correctly flag memory operands to stores. This fixes
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-verify-machineinstrs failures on several tests.
llvm-svn: 132268
2011-05-28 20:34:49 +00:00
325110f30d
Add support for ARM ldrexd/strexd intrinsics. They both use i32 register pairs
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to load/store i64 values. Since there's no current support to explicitly
declare such restrictions, implement it by using specific hardcoded register
pairs during isel.
llvm-svn: 132248
2011-05-28 04:07:29 +00:00
368976f5cc
This actually starts at offset 0, not 1.
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llvm-svn: 132246
2011-05-28 03:16:22 +00:00
a6664cdbf0
Change the set of callee-saved registers for non-MIPS32 architectures specified
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in MipsRegisterInfo::getCalleeSavedRegs so that both registers paired for a
double precision register get saved.
llvm-svn: 132243
2011-05-28 01:41:05 +00:00
d00e8ad803
Implement the 'M' output modifier for arm inline asm. This is fairly
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register allocation dependent and will occasionally break. WIP in the
register allocator to model paired/etc registers.
rdar://9119939
llvm-svn: 132242
2011-05-28 01:40:44 +00:00
b406843fe5
Define a wrapper node for target constant nodes (tglobaladdr, etc.).
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Need this to prevent emitting illegal conditional move instructions.
llvm-svn: 132240
2011-05-28 01:07:07 +00:00
19fea7a840
Add 132187 back now that the real problem is fixed.
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llvm-svn: 132238
2011-05-28 00:24:37 +00:00
1d553a2cc4
Fix the remaining atomic intrinsics to use the right register classes on Thumb2,
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and add some basic tests for them.
llvm-svn: 132235
2011-05-27 23:54:00 +00:00
787dfadc7c
ARM asm parser wasn't able to parse a "mov" instruction while in Thumb
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mode (only the "mov.w" variant). Now, when parsing "mov" in thumb mode,
default to the Thumb 1 versions/encodings.
llvm-svn: 132233
2011-05-27 23:46:09 +00:00
a5149b5cea
It looks like 132187 might have broken the llvm-gcc bootstrap. Revert while I check.
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llvm-svn: 132230
2011-05-27 23:36:02 +00:00
75d99e4b70
Add a GR32_NOREX_NOSP register class and fix a bug where getMatchingSuperRegClass()
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was saying that the matching superregister class of GR32_NOREX in GR64_NOREX_NOSP
is GR64_NOREX, which drops the NOSP constraint. This fixes PR10032.
llvm-svn: 132225
2011-05-27 22:26:04 +00:00
d23bfb8a7a
Make size computation less brittle.
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llvm-svn: 132222
2011-05-27 22:05:41 +00:00
518bcd0ef4
Don't use movw / movt for iOS static codegen for now to workaround some tools issues. rdar://9514789
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llvm-svn: 132211
2011-05-27 20:11:27 +00:00
6019944901
Delete MethodBodies that only filtered reserved registers.
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The register allocators know to filter reserved registers from the allocation
orders, so we don't need all of this boilerplate.
llvm-svn: 132199
2011-05-27 18:27:13 +00:00
fe84bd659c
Fix a silly mistake (which trips over an assertion) in r132099. rdar://9515076
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llvm-svn: 132194
2011-05-27 18:02:04 +00:00
0373d007e9
Remove DwarfRegNum from the individual bits of the condition register.
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These should be DW_OP_bit_piece of CR (64).
llvm-svn: 132192
2011-05-27 16:15:27 +00:00
ecb5573047
Remove DwarfRegNum from CARRY. I should be encoded with DW_OP_bit_piece.
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llvm-svn: 132190
2011-05-27 16:01:08 +00:00
2daba3380d
Remove dwarf numbers from subregs. We should use DW_OP_bit_piece to
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refer to them.
I tested this with both check-all and the gdb testsuite.
llvm-svn: 132187
2011-05-27 15:08:24 +00:00
9b67db8ea7
Make the branch encoding for tBcc more obvious that it's a 4-byte opcode
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followed by a conditional and imm8.
llvm-svn: 132179
2011-05-27 03:50:53 +00:00
bd59e89331
Fix comment.
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llvm-svn: 132178
2011-05-27 03:46:51 +00:00
b362884ca9
Renamed llvm.x86.sse42.crc32 intrinsics; crc64 doesn't exist.
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crc32.[8|16|32] have been renamed to .crc32.32.[8|16|32] and
crc64.[8|16|32] have been renamed to .crc32.64.[8|64].
llvm-svn: 132163
2011-05-26 23:13:19 +00:00
077964a03c
Use MachineFrameInfo::hasCalls instead of MipsFunctionInfo::hasCall to check if
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a function has any function calls.
llvm-svn: 132140
2011-05-26 20:30:31 +00:00
e3a07a3b42
Fix some dwarf register numbers.
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llvm-svn: 132136
2011-05-26 19:25:47 +00:00
aa560006ed
Add support for C++ exception handling.
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llvm-svn: 132131
2011-05-26 18:59:03 +00:00
33a73c7755
Reorganize these slightly according to operand type.
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llvm-svn: 132128
2011-05-26 18:22:26 +00:00
8062bf36b4
Set HasSetDirective to true.
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llvm-svn: 132127
2011-05-26 18:16:18 +00:00
493a12bf5e
Reverting 132105: it broke some LLVM-GCC DejaGNU tests.
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llvm-svn: 132108
2011-05-26 04:09:49 +00:00
26ddb12118
Mark tBX as an indirect branch rather than a return.
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llvm-svn: 132107
2011-05-26 03:41:12 +00:00
276f231c2f
Correctly handle a one-word struct passed byval on x86_64.
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rdar://problem/6920088
llvm-svn: 132105
2011-05-26 02:44:56 +00:00
c70355195c
Rewrite fast-isel integer cast handling to handle more cases, and to be simpler and more consistent.
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The practical effects here are that x86-64 fast-isel can now handle trunc from i8 to i1, and ARM fast-isel can handle many more constructs involving integers narrower than 32 bits (including loads, stores, and many integer casts).
rdar://9437928 .
llvm-svn: 132099
2011-05-25 23:49:02 +00:00
fa63d3096d
Define WeakRefDirective.
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llvm-svn: 132098
2011-05-25 23:30:30 +00:00
a946f476d3
Convert tBX_CALL / tBXr9_CALL to actual pseudoinstructions.
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llvm-svn: 132086
2011-05-25 21:53:50 +00:00
8f2cd0254d
Clean up comment a bit.
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llvm-svn: 132083
2011-05-25 21:19:19 +00:00
8c5e4192e6
Implement the 'm' modifier. Note that it only works for memory operands.
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Part of rdar://9119939
llvm-svn: 132081
2011-05-25 20:51:58 +00:00
f1412e4d2f
Remove MipsTargetLowering::LowerFP_TO_SINT. Patterns for fp_to_sint have already
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been defined in MipsInstrFPU.td.
llvm-svn: 132076
2011-05-25 20:08:05 +00:00
Richard Osborne