Commit Graph

4 Commits

Author SHA1 Message Date
Bill Wendling 37e9adb091 Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.

No functionality change intended.

llvm-svn: 183561
2013-06-07 20:28:55 +00:00
Christian Konig f1fd5fad93 R600/SI: fix inserting waits for all defines
Unfortunately the previous fix for inserting waits for unordered
defines wasn't sufficient, cause it's possible that even ordered
defines are only partially used (or not used at all).

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 177271
2013-03-18 11:33:45 +00:00
Christian Konig 862fd9fa2c R600/SI: fix inserting waits for unordered defines
Signed-off-by: Christian König <christian.koenig@amd.com>
llvm-svn: 176342
2013-03-01 09:46:04 +00:00
Tom Stellard c4cabef782 R600: Proper insert S_WAITCNT instructions
Some instructions like memory reads/writes are executed
asynchronously, so we need to insert S_WAITCNT instructions
to block before accessing their results. Previously we have
just inserted S_WAITCNT instructions after each async
instruction, this patch fixes this and adds a prober
insertion pass.

Patch by: Christian König

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Christian König <deathsimple@vodafone.de>
llvm-svn: 172846
2013-01-18 21:15:53 +00:00