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163 Commits

Author SHA1 Message Date
Chris Lattner c3d36efbb5 silence warning when asserts disabled. 
llvm-svn: 61013
 2008-12-14 21:37:33 +00:00
Dan Gohman ae3ba45eb2 Add a sanity-check to tablegen to catch the case where isSimpleLoad 
is set but mayLoad is not set. Fix all the problems this turned up.

Change code to not use isSimpleLoad instead of mayLoad unless it
really wants isSimpleLoad.

llvm-svn: 60459
 2008-12-03 02:30:17 +00:00
Andrew Lenharth 7d8b884b12 This shouldn't be necessary 
llvm-svn: 59090
 2008-11-11 23:19:51 +00:00
Chris Lattner 2753955fc0 Change CALLSEQ_BEGIN and CALLSEQ_END to take TargetConstant's as 
parameters instead of raw Constants.  This prevents the constants from
being selected by the isel pass, fixing PR2735.

llvm-svn: 57385
 2008-10-11 22:08:30 +00:00
Dan Gohman effb894453 Rename ConstantSDNode::getValue to getZExtValue, for consistency 
with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.

llvm-svn: 56159
 2008-09-12 16:56:44 +00:00
Dan Gohman 8823b0d245 Tablegen generated code already tests the opcode value, so it's not 
necessary to use dyn_cast in these predicates.

llvm-svn: 55055
 2008-08-20 15:24:22 +00:00
Dan Gohman 2ce6f2ad5e Rename SDOperand to SDValue. 
llvm-svn: 54128
 2008-07-27 21:46:04 +00:00
Mon P Wang 6a490371c9 Added MemOperands to Atomic operations since Atomics touches memory. 
Added abstract class MemSDNode for any Node that have an associated MemOperand
Changed atomic.lcs => atomic.cmp.swap, atomic.las => atomic.load.add, and
atomic.lss => atomic.load.sub

llvm-svn: 52706
 2008-06-25 08:15:39 +00:00
Evan Cheng 0e7b00d79f Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF. 
llvm-svn: 48380
 2008-03-15 00:03:38 +00:00
Bill Wendling 97925ec704 Final de-tabification. 
llvm-svn: 47663
 2008-02-27 06:33:05 +00:00
Andrew Lenharth 95528943e9 Atomic op support. If any gcc test uses __sync builtins, it might start failing on archs that haven't implemented them yet 
llvm-svn: 47430
 2008-02-21 06:45:13 +00:00
Andrew Lenharth 9b254eed32 llvm.memory.barrier, and impl for x86 and alpha 
llvm-svn: 47204
 2008-02-16 01:24:58 +00:00
Chris Lattner 9a249b0ce5 rename SDTRet -> SDTNone. 
Move definition of 'trap' sdnode up from x86 instrinfo to targetselectiondag.td.

llvm-svn: 46017
 2008-01-15 22:02:54 +00:00
Chris Lattner 94de7bc3aa get def use info more correct. 
llvm-svn: 45821
 2008-01-10 05:12:37 +00:00
Chris Lattner a4ce4f6987 rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate. 
llvm-svn: 45667
 2008-01-06 23:38:27 +00:00
Chris Lattner a348f55ec6 Change the 'isStore' inferrer to look for 'SDNPMayStore' 
instead of "ISD::STORE".  This allows us to mark target-specific dag
nodes as storing (such as ppc byteswap stores).  This allows us to remove
more explicit isStore flags from the .td files.

Finally, add a warning for when a .td file contains an explicit 
isStore and tblgen is able to infer it.

llvm-svn: 45654
 2008-01-06 06:44:58 +00:00
Chris Lattner f3ebc3f3d2 Remove attribution from file headers, per discussion on llvmdev. 
llvm-svn: 45418
 2007-12-29 20:36:04 +00:00
Evan Cheng 6e68381e02 Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled. 
llvm-svn: 44960
 2007-12-12 23:12:09 +00:00
Andrew Lenharth b960acebde something wrong with this opt 
llvm-svn: 44370
 2007-11-27 18:31:30 +00:00
Bill Wendling 77b13af9a6 Unifacalize the CALLSEQ{START,END} stuff. 
llvm-svn: 44045
 2007-11-13 09:19:02 +00:00
Bill Wendling f359fed9f9 Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stack 
adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in
the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If
not, then there is the potential for the stack to be changed while the stack's
being used by another instruction (like a call).

This can only result in tears...

llvm-svn: 44037
 2007-11-13 00:44:25 +00:00
Owen Anderson 933b5b7e62 Add a flag for indirect branch instructions. 
Target maintainers: please check that the instructions for your target are correctly marked.

llvm-svn: 44012
 2007-11-12 07:39:39 +00:00
Evan Cheng 3e18e504ae Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. 
llvm-svn: 41863
 2007-09-11 19:55:27 +00:00
Evan Cheng ac1591be42 No more noResults. 
llvm-svn: 40132
 2007-07-21 00:34:19 +00:00
Evan Cheng 94b5a80b93 Change instruction description to split OperandList into OutOperandList and 
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033
 2007-07-19 01:14:50 +00:00
Andrew Lenharth 2077814c91 Use this nifty Constraints thing and fix the inverted conditional moves 
llvm-svn: 36191
 2007-04-17 04:07:59 +00:00
Andrew Lenharth c4bdea012b FTOIT and ITOFT are bit converts, and if we drop 21264s, are always available 
llvm-svn: 33492
 2007-01-24 21:09:16 +00:00
Andrew Lenharth 76a61eb054 Be sure to grab weak functions too, and make implicit defs comments 
llvm-svn: 32308
 2006-12-07 17:39:14 +00:00
Chris Lattner b974b0a3e1 silence warnings. 
llvm-svn: 31394
 2006-11-03 01:18:29 +00:00
Andrew Lenharth d8b59f67f6 fix 2006-11-01-vastart.ll 
llvm-svn: 31371
 2006-11-02 03:05:26 +00:00
Andrew Lenharth dfbf91e59d more shotenning 
llvm-svn: 31331
 2006-10-31 23:46:56 +00:00
Andrew Lenharth 8b20fa42da Let us play simplify the td file (and fix a few missed sub and mul patterns). 
llvm-svn: 31322
 2006-10-31 19:52:12 +00:00
Andrew Lenharth 692e4155aa Add all that branch mangling niftiness 
llvm-svn: 31313
 2006-10-31 16:49:55 +00:00
Evan Cheng ab51cf2e78 Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode. 
llvm-svn: 30945
 2006-10-13 21:14:26 +00:00
Chris Lattner 0e0ee36f45 adjcallstack up/down clobbers the sp 
llvm-svn: 30910
 2006-10-12 18:00:14 +00:00
Chris Lattner 6487854b3f Use cute tblgen tricks to make zap handling more powerful. Specifically, 
when the dag combiner simplifies an and mask, notice this and allow those bits
to be missing from the zap mask.

This compiles Alpha/zapnot4.ll into:

        sll $16,3,$0
        zapnot $0,3,$0
        ret $31,($26),1

instead of:

        ldah $0,1($31)
        lda $0,-8($0)
        sll $16,3,$1
        and $1,$0,$0
        ret $31,($26),1

It would be *really* nice to replace the hunk of code in the
AlphaISelDAGToDAG.cpp file that matches (and (srl (x, C), c2) into
(SRL (ZAPNOTi)) with a similar pattern, but I've spent enough time poking
at alpha.  Make andrew will do this.

llvm-svn: 30875
 2006-10-11 05:13:56 +00:00
Chris Lattner 9f86f7c2ab Remove dead/redundant instructions. These are handled by ZAPNOTi 
llvm-svn: 30872
 2006-10-11 04:12:39 +00:00
Evan Cheng e71fe34d75 Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes. 
llvm-svn: 30844
 2006-10-09 20:57:25 +00:00
Andrew Lenharth f007f21c8a catch constants more often 
llvm-svn: 30534
 2006-09-20 15:05:49 +00:00
Andrew Lenharth 3aa3ad780e Jump tables on Alpha 
llvm-svn: 30463
 2006-09-18 18:01:03 +00:00
Evan Cheng 81b645a76b CALLSEQ_* produces chain even if that's not needed. 
llvm-svn: 29603
 2006-08-11 09:03:33 +00:00
Evan Cheng 2af3a67902 Remove a duplicate pattern/ 
llvm-svn: 29413
 2006-07-31 18:42:49 +00:00
Andrew Lenharth 80528499cf Let the alpha breakage begin. First Formals and RET. next Calls 
llvm-svn: 28753
 2006-06-12 18:09:24 +00:00
Andrew Lenharth b47461350c ignore ordered/unordered for now 
llvm-svn: 28679
 2006-06-04 00:25:51 +00:00
Andrew Lenharth df7abf8b74 support x * (c1 + c2) where c1 and c2 are pow2s. special case for c2 == 4 
llvm-svn: 27370
 2006-04-03 04:19:17 +00:00
Andrew Lenharth 4e2c073a33 mul by const conversion sequences. more coming soon 
llvm-svn: 27368
 2006-04-03 03:18:59 +00:00
Andrew Lenharth 70236fc12f fcopysign for mixed mode 
llvm-svn: 26651
 2006-03-09 17:56:33 +00:00
Andrew Lenharth 4a87e7d9a3 alpha and llvm have different oppinions on which arg is the sign bit 
llvm-svn: 26647
 2006-03-09 17:41:50 +00:00
Andrew Lenharth 16b96d2cb4 Alpha Scheduling classes 
llvm-svn: 26643
 2006-03-09 17:16:45 +00:00
Andrew Lenharth ed7a293b44 fcopysign and get rid of dsnode cruft. custom PA runtimes make this better in some senses 
llvm-svn: 26641
 2006-03-09 14:58:25 +00:00