f80969f29b
These targets don't like setcc
...
llvm-svn: 21884
2005-05-12 02:06:00 +00:00
99fa5bc1fa
Necessary changes to codegen cttz efficiently on PowerPC
...
1. Teach LegalizeDAG how to better legalize CTTZ if the target doesn't have
CTPOP, but does have CTLZ
2. Teach PPC32 how to do sub x, const -> add x, -const for valid consts
3. Teach PPC32 how to do and (xor a, -1) b -> andc b, a
4. Teach PPC32 that ISD::CTLZ -> PPC::CNTLZW
llvm-svn: 21880
2005-05-11 23:43:56 +00:00
96726a46c7
Fixed issue that broke ssa.
...
llvm-svn: 21878
2005-05-11 21:45:03 +00:00
9c64b0cc18
fix some GCC 4 warnings
...
llvm-svn: 21877
2005-05-11 21:40:40 +00:00
72002e87cc
Added support for decomposing constant expressions containing shr and shl
...
instructions.
Review of this commit would be greatly appreciated.
llvm-svn: 21876
2005-05-11 21:16:42 +00:00
25163d8d60
add the popcount instruction and support this in the isel
...
the primary user of this will probably end up being find-first-set-bit/find-
last-set-bit, which i'll get around to...
llvm-svn: 21860
2005-05-11 05:16:09 +00:00
669c3b17eb
No really IA*64* :)
...
llvm-svn: 21858
2005-05-11 05:03:56 +00:00
05ad4b8369
X86 has more than just 32-bit registers
...
llvm-svn: 21857
2005-05-11 05:00:34 +00:00
d8145bcd5b
Convert feature of the simple isel over for the pattern isel to use.
...
llvm-svn: 21840
2005-05-10 03:53:18 +00:00
915594d884
Silence some VC++ warnings
...
llvm-svn: 21838
2005-05-10 02:22:38 +00:00
70ea07cfd2
Implement READPORT/WRITEPORT, implementing the last X86 regression tests
...
that were failing with the pattern selector. Note that the support that
existed in the simple selector was clearly broken in several ways though
(which has also been fixed).
llvm-svn: 21831
2005-05-09 21:17:38 +00:00
e53158e21d
do not emit illegal instructions
...
llvm-svn: 21830
2005-05-09 21:06:04 +00:00
46b5ca4310
Fix the syntax of the i/o instructions, these are obviously unused.
...
llvm-svn: 21829
2005-05-09 20:49:20 +00:00
6c6a39a7b8
legalize readio/writeio into load/stores, fixing CodeGen/X86/io.llx with
...
the pattern isel.
llvm-svn: 21828
2005-05-09 20:37:29 +00:00
4ccd1f603c
restore some non-dead code I removed last night breaking double casts to
...
uint
llvm-svn: 21821
2005-05-09 18:37:02 +00:00
129c5fea44
fold and (shl X, C1), C2 -> rlwinm when possible. Many other cases are possible,
...
include and (srl) and the inverses (shl and) etc.
llvm-svn: 21820
2005-05-09 17:39:48 +00:00
74a01fa211
fix and cleanup constmul code a bit, this fixes mediabench/toast and
...
probably a couple of other tests.
llvm-svn: 21814
2005-05-09 13:18:34 +00:00
daa064d8fd
Wrap long lines, remove dead code that is now handled by legalize
...
llvm-svn: 21811
2005-05-09 05:40:26 +00:00
e62661185c
Fix FP -> bool casts
...
llvm-svn: 21810
2005-05-09 05:33:18 +00:00
6972c31ab5
Fix X86/2005-05-08-FPStackifierPHI.ll: ugly gross hack.
...
llvm-svn: 21801
2005-05-09 03:36:39 +00:00
18335f8925
clean up the CBE output a bit
...
llvm-svn: 21740
2005-05-06 06:58:42 +00:00
561b7eb9e1
add tail marker as a comment
...
llvm-svn: 21739
2005-05-06 06:53:07 +00:00
b8e94c3499
fix typo
...
llvm-svn: 21693
2005-05-04 19:25:37 +00:00
aed06a0e92
Well, add support for ct* for 21264 only.
...
21164 is broken until expand works.
llvm-svn: 21692
2005-05-04 19:12:09 +00:00
5e177826fd
Implement count leading zeros (ctlz), count trailing zeros (cttz), and count
...
population (ctpop). Generic lowering is implemented, however only promotion
is implemented for SelectionDAG at the moment.
More coming soon.
llvm-svn: 21676
2005-05-03 17:19:30 +00:00
7acd5d5f06
support multiplication by constant negative integers
...
this constmul code is still buggy though, so beware. mul by 7427 is currently
broken, for example. will fix it when I get a moment :)
llvm-svn: 21652
2005-05-02 07:27:14 +00:00
0e73188c10
add support for bools to SELECT, this fixes Prolangs-C/bison from the
...
testsuite, however 09-vor is still dead (hopefully for other reasons!)
llvm-svn: 21651
2005-05-02 06:41:13 +00:00
9d43c75a55
SMS for superblocks.
...
llvm-svn: 21643
2005-05-01 01:27:47 +00:00
bdfb9e61a0
Added extra constructor for superblocks.
...
llvm-svn: 21642
2005-05-01 01:25:53 +00:00
4d0ee754e3
Fixed bug in searchPath function for finding nodes between two recurrences.
...
Changed dependence analyzer to only use dep distances of 2 or less.
This is experimental.
Changed MSchedGraph to be able to represent more then one BB (first steps).
llvm-svn: 21641
2005-04-30 23:07:59 +00:00
537332eba8
I was sure I had thought about this and there was a reason it should work.
...
But it is entirely possible I am just crazy.
llvm-svn: 21640
2005-04-30 14:19:13 +00:00
c8a6633dea
Eliminate some random whitespace
...
llvm-svn: 21637
2005-04-30 04:44:07 +00:00
9993823876
Doesn't support these nodes
...
llvm-svn: 21634
2005-04-30 04:26:56 +00:00
9c6bbafc15
This target doesn't support the FSIN/FCOS/FSQRT nodes yet
...
llvm-svn: 21633
2005-04-30 04:26:06 +00:00
db68d39a01
Add support for FSIN/FCOS when unsafe math ops are enabled. Patch contributed by
...
Morten Ofstad!
llvm-svn: 21632
2005-04-30 04:25:35 +00:00
3b20386551
Add support for llvm.sqrt and sin/cos if unsafe math optimizations are enabled.
...
llvm-svn: 21631
2005-04-30 04:12:40 +00:00
4a2cc6603d
Expose an option allowing unsafe math optimizations. Patch contributed by
...
Morten Ofstad!
llvm-svn: 21630
2005-04-30 04:09:52 +00:00
014d2c42e7
Add support for FSQRT node, patch contributed by Morten Ofstad
...
llvm-svn: 21610
2005-04-28 22:07:18 +00:00
61827484c7
Add some new X86 instrs, patch contributed by Morten Ofstad
...
llvm-svn: 21608
2005-04-28 21:50:05 +00:00
effaec5436
Codegen fabs/fabsf as FABS. Patch contributed by Morten Ofstad
...
llvm-svn: 21607
2005-04-28 21:48:42 +00:00
4a73c2cfdc
Implement Value* tracking for loads and stores in the selection DAG. This enables one to use alias analysis in the backends.
...
(TRUNK)Stores and (EXT|ZEXT|SEXT)Loads have an extra SDOperand which is a SrcValueSDNode which contains the Value*. Note that if the operation is introduced by the backend, it will still have the operand, but the value* will be null.
llvm-svn: 21599
2005-04-27 20:10:01 +00:00
b071bef66a
clean up some warnings
...
llvm-svn: 21590
2005-04-27 11:57:39 +00:00
e06ef80244
constmul bugfix: multiply by 27611 was broken
...
llvm-svn: 21564
2005-04-26 09:42:50 +00:00
bbd0cd71a8
clean up the code! (oops) lots more cleaning left, however.
...
llvm-svn: 21563
2005-04-26 08:43:47 +00:00
81ebb57771
* Add code to reduce multiplies by constant integers to shifts, adds and
...
subtracts. This is a very rough and nasty implementation of Lefevre's
"pattern finding" algorithm. With a few small changes though, it should
end up beating most other methods in common use, regardless of the size
of the constant (currently, it's often one or two shifts worse)
TODO: rewrite it so it's not hideously ugly (this is a translation from
perl, which doesn't help ;)
bypass most of it for multiplies by 2^n+1
(eventually) teach it that some combinations of shift+add are
cheaper than others (e.g. shladd on ia64, scaled adds on alpha)
get it to try multiple booth encodings in search of the cheapest
routine
make it work for negative constants
This is hacked up as a DAG->DAG transform, so once I clean it up I hope
it'll be pulled out of here and put somewhere else. The only thing backends
should really have to worry about for now is where to draw the line
between using this code vs. going ahead and doing an integer multiply
anyway.
llvm-svn: 21560
2005-04-26 07:23:02 +00:00
ff7b16c1d6
Shut GCC 4.0 up about classes that have virtual functions but a non-virtual
...
destructor. Just add the do-nothing virtual destructor.
llvm-svn: 21524
2005-04-25 02:55:55 +00:00
fd8c2265fa
Convert tabs to spaces
...
llvm-svn: 21457
2005-04-22 18:06:01 +00:00
e73e76dc42
Convert tabs to spaces
...
llvm-svn: 21452
2005-04-22 17:54:37 +00:00
e4481c7c82
Implement the --enable-targets= feature of the configure script. The make
...
variable TARGETS_TO_BUILD is used to determine which targets in lib/Target
are built and which libraries are linked into llc. This effectively
implements the feature. One item remains: disabling targets in the dejagnu
test suite.
llvm-svn: 21450
2005-04-22 17:20:11 +00:00
8f4081a8c9
keep track of max depth stats
...
llvm-svn: 21446
2005-04-22 13:35:18 +00:00
42ed14860b
Updated dependence analyzer. Fixed numerous bugs. Same stage scheduling, etc.
...
llvm-svn: 21444
2005-04-22 06:32:48 +00:00
c88330ad13
* Remove trailing whitespace
...
* Convert tabs to spaces
llvm-svn: 21426
2005-04-21 23:38:14 +00:00
b440243e94
Remove trailing whitespace
...
llvm-svn: 21425
2005-04-21 23:30:14 +00:00
89b8c8d215
Remove trailing whitespace
...
llvm-svn: 21424
2005-04-21 23:13:11 +00:00
10468d8a3c
Remove trailing whitespace
...
llvm-svn: 21422
2005-04-21 22:55:34 +00:00
3590ef1164
Match another form of eqv
...
llvm-svn: 21413
2005-04-21 21:09:11 +00:00
486a1ec909
Handle stores of global address as stores of immediates. Instead of:
...
test1:
movl $N, %eax
movl %eax, G
ret
emit:
test1:
movl $N, G
ret
llvm-svn: 21407
2005-04-21 19:11:03 +00:00
adcfc1748b
Handle (store &GV -> mem) as a store immediate. This often occurs for
...
printf format strings and other stuff. Instead of generating this:
movl $l1__2E_str_1, %eax
movl %eax, (%esp)
we now emit:
movl $l1__2E_str_1, (%esp)
llvm-svn: 21406
2005-04-21 19:03:24 +00:00
ea548c0cb1
Remove trailing whitespace, patch by Markus Oberhumer.
...
llvm-svn: 21379
2005-04-20 16:05:03 +00:00
53c40624f9
Add completely untested support for mtcrf/mfcrf encoding
...
llvm-svn: 21353
2005-04-19 05:41:52 +00:00
baa9be572b
switch over the rest of the formats that use RC to use isDOT
...
llvm-svn: 21352
2005-04-19 05:21:30 +00:00
f9172e14c9
Convert the XForm instrs and XSForm instruction over to use isDOT
...
llvm-svn: 21351
2005-04-19 05:15:18 +00:00
5b78da4571
Now that the ppc64 and vmx operands of I are always 0, forward substitute
...
them away.
llvm-svn: 21350
2005-04-19 05:05:22 +00:00
116a9e5a34
convert over bform and iform instructions
...
llvm-svn: 21349
2005-04-19 05:00:59 +00:00
b2367e398e
Convert over DForm and DSForm instructions
...
llvm-svn: 21348
2005-04-19 04:59:28 +00:00
15709c2c33
Convert XLForm and XForm instructions over to use PPC64 when appropriate.
...
llvm-svn: 21347
2005-04-19 04:51:30 +00:00
d790d22f22
Convert XO XS and XFX forms to use isPPC64
...
llvm-svn: 21346
2005-04-19 04:40:07 +00:00
c7cb8c77fb
Turn PPC64 and VMX into classes that can be added to instructions instead of
...
bits that must be passed up the inheritance hierarchy. Convert MForm and AForm
instructions over
llvm-svn: 21345
2005-04-19 04:32:54 +00:00
2331c061ee
Next round of PPC CR optimizations. For the following code:
...
int %bar(float %a, float %b, float %c, float %d) {
entry:
%tmp.1 = setlt float %a, %d
%tmp.2 = setlt float %b, %d
%or = or bool %tmp.1, %tmp.2
%tmp.3 = setgt float %c, %d
%tmp.4 = or bool %or, %tmp.3
%tmp.5 = and bool %tmp.4, true
%retval = cast bool %tmp.5 to int
ret int %retval
}
We now emit:
_bar:
.LBB_bar_0: ; entry
fcmpu cr0, f1, f4
fcmpu cr1, f2, f4
cror 0, 0, 4
fcmpu cr1, f3, f4
cror 28, 0, 5
mfcr r2
rlwinm r3, r2, 29, 31, 31
blr
Instead of:
_bar:
.LBB_bar_0: ; entry
fcmpu cr7, f1, f4
mfcr r2
rlwinm r2, r2, 29, 31, 31
fcmpu cr7, f2, f4
mfcr r3
rlwinm r3, r3, 29, 31, 31
or r2, r2, r3
fcmpu cr7, f3, f4
mfcr r3
rlwinm r3, r3, 30, 31, 31
or r3, r2, r3
blr
llvm-svn: 21321
2005-04-18 07:48:09 +00:00
602a45f415
Change codegen for setcc to read the bit directly out of the condition
...
register. Added support in the .td file for the g5-specific variant
of cr -> gpr moves that executes faster, but we currently don't
generate it.
llvm-svn: 21314
2005-04-18 02:43:24 +00:00
f281f791b5
Handle ExternalSymbol operands in the PPC JIT
...
llvm-svn: 21312
2005-04-18 00:46:10 +00:00
779c5cbb44
Make pattern isel default for ppc
...
Add new ppc beta option related to using condition registers
Make pattern isel control flag (-enable-pattern-isel) global and tristate
0 == off
1 == on
2 == target default
llvm-svn: 21309
2005-04-15 22:12:16 +00:00
00ce283b3f
fix calls
...
llvm-svn: 21303
2005-04-14 17:34:20 +00:00
7ae3aba5aa
a 21264 fix, and fix the operator precidence on an and -> zap check (should fix hundreds of test cases
...
llvm-svn: 21302
2005-04-14 16:24:00 +00:00
0a7c2b9078
print negative 64 bit immediates as negative numbers, makes things a little
...
easier on the eyes, not that numbers like 18446744073709541376 are bad or
anything
llvm-svn: 21300
2005-04-14 10:08:01 +00:00
dfbbcc098b
oops, this stopped us turning movl r4=0xFFFFFFFF;; and rX, r4 into zxt4
...
llvm-svn: 21299
2005-04-14 10:06:35 +00:00
53d3eccbe2
Implement multi-way branches through logical ops on condition registers.
...
This can generate considerably shorter code, reducing the size of crafty
by almost 1%. Also fix the printing of mcrf. The code is currently
disabled until it gets a bit more testing, but should work as-is.
llvm-svn: 21298
2005-04-14 09:45:08 +00:00
f6b666fb06
we have zextloads, not sextloads!
...
llvm-svn: 21296
2005-04-14 08:37:32 +00:00
65a82c562e
Add the necessary support to codegen condition register logical ops with
...
register allocated condition registers. Make sure that the printed
output is gas compatible.
llvm-svn: 21295
2005-04-14 03:20:38 +00:00
be21011911
Start allocating condition registers. Almost all explicit uses of CR0 are
...
now gone. Next step is to get rid of the remaining ones and then start
allocating bools to CRs where appropriate.
llvm-svn: 21294
2005-04-13 23:15:44 +00:00
dd1bb81d04
Implement the fold shift X, zext(Y) -> shift X, Y at the target level,
...
where it is safe to do so.
llvm-svn: 21293
2005-04-13 22:14:14 +00:00
4ddd81657b
Disbale the broken fold of shift + sz[ext] for now
...
Move the transform for select (a < 0) ? b : 0 into the dag from ppc isel
Enable the dag to fold and (setcc, 1) -> setcc for targets where setcc
always produces zero or one.
llvm-svn: 21291
2005-04-13 21:23:31 +00:00
93341a0f82
WOW, function calls still seem to work after this.
...
llvm-svn: 21286
2005-04-13 17:17:28 +00:00
c3621316ee
prepare for func call optimization
...
llvm-svn: 21285
2005-04-13 16:19:50 +00:00
2f2312575b
* add the shladd instruction
...
* fold left shifts of 1, 2, 3 or 4 bits into adds
This doesn't save much now, but should get a serious workout once
multiplies by constants get converted to shift/add/sub sequences.
Hold on! :)
llvm-svn: 21282
2005-04-13 06:12:04 +00:00
c7287c8eda
add matches for SxADDL and company, as well as simplify the SxADDQ code
...
llvm-svn: 21281
2005-04-13 05:19:55 +00:00
e7ef27bcfe
* if ANDing with a constant of the form:
...
0x00000..00FFF..FF
^ ^
^ ^
any number of
0's followed by
some number of
1's
then we use dep.z to just paste zeros over the input. For the special
cases where this is zxt1/zxt2/zxt4, we use those instructions instead,
because we're all about readability!!!
that's what it's about!! readability!
*twitch* ;D
llvm-svn: 21279
2005-04-13 04:50:54 +00:00
8eb82fb524
added all flavors of zap for anding
...
llvm-svn: 21276
2005-04-13 03:47:03 +00:00
60c23bd169
Fix some mysteriously missing {}'s which cause the miscompilation of
...
Olden/mst, Ptrdist/bc, Obsequi, etc.
llvm-svn: 21274
2005-04-13 03:29:53 +00:00
e0efd1fa72
remove one more occurance of this that snuck in
...
llvm-svn: 21271
2005-04-13 02:46:17 +00:00
857624f47a
Remove support for ZERO_EXTEND_INREG. This pessimizes code, genering stuff
...
like this:
ldah $1,1($31)
lda $1,-1($1)
and $0,$1,$24
instead of this:
zap $0,252,$24
To get this back, the selector should recognize the ISD::AND case where this
happens and emit the appropriate ZAP instruction.
llvm-svn: 21270
2005-04-13 02:43:40 +00:00
7f4c4179a6
Remove special handling of ZERO_EXTEND_INREG. This pessimizes code, causing
...
things like this:
mov r9 = 65535;;
and r8 = r8, r9;;
To be emitted instead of:
zxt2 r8 = r8;;
To get this back, the selector for ISD::AND should recognize this case.
llvm-svn: 21269
2005-04-13 02:41:52 +00:00
83075510ee
Elimate handling of ZERO_EXTEND_INREG. This causes the PPC backend to emit
...
andi instructions instead of rlwinm instructions for zero extend, but they
seem like they would take the same time.
llvm-svn: 21268
2005-04-13 02:40:26 +00:00
248fe6bda2
Z_E_I is gone
...
llvm-svn: 21267
2005-04-13 02:39:05 +00:00
af1c0f7a00
Fold shift by size larger than type size to undef
...
Make llvm undef values generate ISD::UNDEF nodes
llvm-svn: 21261
2005-04-12 23:12:17 +00:00
818eb6ddd2
Implement setcc op, -1 sequences
...
Remove dead setcc op, 0 sequences
Coming later: generalization of op, imm
llvm-svn: 21260
2005-04-12 21:22:28 +00:00
fd469bddac
* OK, after changing to use liveIn/liveOut instead of IDEFs,
...
to avoid redundant mov out3=r44 type instructions, we need to
tell the register allocator the truth about out? registers.
FIXME: unfortunately, since the list of allocatable registers is immutable,
we can't simply 'delete r127' from the allocation order, say, if 'out0' is
used. The only correct thing we can do is have a linear order of regs:
out7, out6 ... out2, out1, out0, r32, r33, r34 ... r126, r127
and slide a 'window' of 96 registers along this line, depending on how many
of the out? regs a function actually uses. The only downside of this is
that the out? registers will be allocated _first_, which makes the
resulting assembly ugly. :( Note this in the README. Hope this gets fixed
soon. :) (note the 3rd person speech there)
llvm-svn: 21252
2005-04-12 18:42:59 +00:00
740f93ca10
Get rid of idefs for arguments (oops)
...
llvm-svn: 21251
2005-04-12 17:47:57 +00:00
10c6eb4be2
Get rid of idefs for arguments
...
llvm-svn: 21250
2005-04-12 17:35:16 +00:00
14f72885dd
Put out* into the allocation order, allowing the register allocator to
...
coallesce moves into outgoing args.
llvm-svn: 21249
2005-04-12 15:12:51 +00:00
6b91767b77
Make sure to realize that calls use their argument regs
...
llvm-svn: 21248
2005-04-12 15:12:19 +00:00
b6dfb227b7
stop emitting IDEFs for args - change to using liveIn/liveOut
...
llvm-svn: 21247
2005-04-12 14:54:44 +00:00
f67f3bf627
Initial support for allocation condition registers
...
llvm-svn: 21246
2005-04-12 07:04:16 +00:00
79a3bea4ca
Implement bitfield clears
...
Implement divide by negative power of two
llvm-svn: 21240
2005-04-12 00:10:02 +00:00
08698cf644
Update PPC readme. Remove things that are done or aren't ppc specific
...
llvm-svn: 21232
2005-04-11 20:48:57 +00:00
607bd26b38
IA64 supports this operation.
...
llvm-svn: 21228
2005-04-11 18:55:36 +00:00
67291ea580
ORo sets CR0
...
llvm-svn: 21227
2005-04-11 15:03:48 +00:00
f29cc88210
Revert the previous patch, which I didn't mean to check in.
...
llvm-svn: 21226
2005-04-11 15:03:41 +00:00
d3dc31009f
Fix a minor bug (ORo didn't mark that it set CR0).
...
Refactor how . instructions are handled. In particular, instead of passing
the RC flag all the way up the inheritance hierarchy, just make a new tblgen
class 'DOT' which can be added to an instruction definition.
For example, instead of this:
-def AND : XForm_6<31, 28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
-let Defs = [CR0] in
-def ANDo : XForm_6<31, 28, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "and. $rA, $rS, $rB">;
We now have this:
+def AND : XForm_6<31, 28, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"and $rA, $rS, $rB">;
llvm-svn: 21225
2005-04-11 15:01:39 +00:00
8de7ac092d
hmm, should probably change addImm() to take 64-bit arguments one day anyway.
...
llvm-svn: 21224
2005-04-11 07:16:39 +00:00
bebefac791
Add recording variants of ISD::AND and ISD::OR. This kills almost 1000
...
(1.5%) instructions in 186.crafty
llvm-svn: 21222
2005-04-11 06:34:10 +00:00
fb43ef78c5
assorted fixes:
...
* clean up immediates (we use 14, 22 and 64 bit immediates now. sane.)
* fold r0/f0/f1 registers into comparisons against 0/0.0/1.0
* fix nasty thinko - didn't use two-address form of conditional add
for extending bools to integers, so occasionally there would be
garbage in the result. it's amazing how often zeros are just
sitting around in registers ;) - this should fix a bunch of tests.
llvm-svn: 21221
2005-04-11 05:55:56 +00:00
492370311d
Fix another fixme: factor out the constant fp generation code.
...
llvm-svn: 21207
2005-04-10 06:06:10 +00:00
941a01802f
Fix 64 bit argument loading that straddles the args in regs / args on stack
...
boundary.
llvm-svn: 21206
2005-04-10 05:53:14 +00:00
b076731713
Remove unnecessary Implicit Defs. Since r0 is not in allocation, we do not
...
have to inform the register allocator it might be stepped on.
llvm-svn: 21202
2005-04-10 03:59:42 +00:00
6566e8ac06
Make sure that BRCOND branches can be converted into long branches too.
...
llvm-svn: 21198
2005-04-10 01:48:29 +00:00
3345eadc37
Don't hand ISD::CALL nodes off to SelectExprFP. This fixes siod.
...
llvm-svn: 21197
2005-04-10 01:14:13 +00:00
9ff4b4190f
rename getPPCOpcodeForSetCCNumber -> getPPCOpcodeForSetCCOpode to be more
...
correct. Remove the EmitComparison retvalue, as it is always the first arg.
Fix a place where we incorrectly passed in the setcc opcode instead of the
setcc number, causing us to miscompile crafty. Crafty now works!
llvm-svn: 21195
2005-04-10 01:03:31 +00:00
2121a54868
fix ISD::BRCONDTWOWAY codegen to not deference the end() iterator
...
llvm-svn: 21193
2005-04-09 23:35:05 +00:00
228fed92e6
Fix CodeGen/Generic/2005-05-09-GlobalInPHI.ll, which was reduced from 254.gap.
...
This caused the "use before a def" assertion on some programs.
With this patch, 254.gap now passes with the PPC backend.
llvm-svn: 21191
2005-04-09 22:05:17 +00:00
e8e070dbfb
do not set the root to null if an argument is dead
...
llvm-svn: 21188
2005-04-09 21:23:24 +00:00
8309a333dd
Add rlwnm instruction for variable rotate
...
Generate rotate left/right immediate
Generate code for brcondtwoway
Use new livein/liveout functionality
llvm-svn: 21187
2005-04-09 20:09:12 +00:00
3a7f5768c5
Fix a crash on 173.applu by asking for a constant bigger than 32-bits.
...
llvm-svn: 21185
2005-04-09 19:47:21 +00:00
a55a5f2580
Switch this instruction selector over to using liveins and liveouts, eliminating
...
implicit defs on entry to the function. yaay :)
llvm-svn: 21184
2005-04-09 16:32:30 +00:00
b59006c4a1
Use live out sets for return values instead of imp_defs, which is cleaner and faster.
...
llvm-svn: 21181
2005-04-09 15:23:56 +00:00
46aa06cfed
ok, the "ia64 has a boatload of registers" joke stopped being funny today ;)
...
* fix overallocation of integer (stacked) registers: we can't allocate
registers for local use if they are required as output registers
this fixes 'toast' in the test suite, and all sorts of larger programs
like bzip2 etc.
llvm-svn: 21178
2005-04-09 11:53:00 +00:00
2f64122319
Optimize FSEL a bit for fneg arguments. This fixes the recently added test
...
case so that we emit
_test_fneg_sel:
.LBB_test_fneg_sel_0: ;
fsel f1, f1, f3, f2
blr
instead of:
_test_fneg_sel:
.LBB_test_fneg_sel_0: ;
fneg f0, f1
fneg f0, f0
fsel f1, f0, f3, f2
blr
llvm-svn: 21177
2005-04-09 09:33:07 +00:00
888c5fdcc2
Fix CodeGen/SparcV9/2005-05-09-GEP-Crash.ll a crash on some specfp program
...
lets hope this doesn't break other programs with induced entropy
llvm-svn: 21174
2005-04-09 06:27:14 +00:00
a3a135a9f7
This target does not support/want ISD::BRCONDTWOWAY
...
llvm-svn: 21164
2005-04-09 03:22:37 +00:00
4f77badaa3
This target does not yet support ISD::BRCONDTWOWAY
...
llvm-svn: 21163
2005-04-09 03:22:30 +00:00
e8ce0cda40
64b: Expand S/UREM
...
32b: No longer pattern match fneg(fsub(fmul)) as fnmsub
Pattern match fsub a, mul(b, c) as fnmsub
Pattern match fadd a, mul(b, c) as fmadd
Those changes speed up hydro2d by 2.5%, distray by 6%, and scimark by 8%
llvm-svn: 21161
2005-04-09 03:05:51 +00:00
f50b597f67
Fix 64b shifts
...
llvm-svn: 21159
2005-04-08 23:45:01 +00:00
705d3c18e8
Match Mac OS X 64 bit calling conventions
...
llvm-svn: 21157
2005-04-08 21:26:05 +00:00
de5aed3f12
collect a few statistics, factor constants (constant loading and mult), fix logic operation pattern matchs, supress FP div when int dividing by a constant
...
llvm-svn: 21156
2005-04-08 17:28:49 +00:00
41ff502549
fix bogus division-by-power-of-2 (was wrong for negative input, adds extr insn)
...
fix hack in division (clean up frcpa instruction)
llvm-svn: 21153
2005-04-08 10:01:48 +00:00
b1f66d1af2
Optimized code sequences for setcc reg, 0
...
Optimized code sequence for (a < 0) ? b : 0
llvm-svn: 21150
2005-04-07 20:30:01 +00:00
534eebb317
Alpha zero extends setcc results
...
llvm-svn: 21149
2005-04-07 20:11:32 +00:00
532ac79122
PowerPC zero extends setcc results
...
llvm-svn: 21147
2005-04-07 19:41:49 +00:00
38fd97084b
X86 zero extends setcc results
...
llvm-svn: 21146
2005-04-07 19:41:46 +00:00
9807ac5d3c
fix a small optimization opertunity and make gcc happy
...
llvm-svn: 21143
2005-04-07 18:15:28 +00:00
6b492bec30
fixup magic constant making code. tested by thousands of random divisions.... by 10000. ok, so random divisors would be good too, but this at least fixes some things
...
llvm-svn: 21140
2005-04-07 17:19:16 +00:00
d2da7177f2
lowercase instructions, makes diff happier
...
llvm-svn: 21139
2005-04-07 17:17:48 +00:00
05e51d92e0
It wasn't happy about this either
...
llvm-svn: 21133
2005-04-07 14:18:13 +00:00
85f34a5682
Yea, it wasn't happy
...
llvm-svn: 21132
2005-04-07 13:55:53 +00:00
a7abda3989
teach asmprinter to print s8/s14 operands
...
llvm-svn: 21131
2005-04-07 12:34:36 +00:00
8419da8acf
codegen immediate forms of add/sub/shift
...
llvm-svn: 21130
2005-04-07 12:33:38 +00:00
b484f7c55e
add immediate forms of add, sub, shift
...
llvm-svn: 21129
2005-04-07 12:32:24 +00:00
d20628ff7d
Pattern match bitfield insert, which helps shift long by immediate, among
...
other things.
llvm-svn: 21127
2005-04-06 23:51:40 +00:00
505f6b760d
Fix some shift bugs
...
llvm-svn: 21126
2005-04-06 22:42:08 +00:00
7ca0947274
Make these 64 bit constants so that this compiles on x86-32 as well.
...
llvm-svn: 21125
2005-04-06 22:09:40 +00:00
3ea17c6cfe
added sdiv by 2^k and works for neg divisors also
...
llvm-svn: 21124
2005-04-06 22:03:13 +00:00
df3256aa7f
fix copy/paste errors, and add imm support to SxADDQ and SxSUBQ
...
llvm-svn: 21121
2005-04-06 20:59:59 +00:00
bd32728a98
Fix SingleSource/Regression/C/2005-05-06-LongLongSignedShift.c, we were not
...
properly sign extending the top of the result of a 64-bit shift right by
a constant > 32.
llvm-svn: 21120
2005-04-06 20:59:35 +00:00
1d4747c302
Added Nate's div by constant stuff, also scaled operations!
...
llvm-svn: 21116
2005-04-06 20:25:34 +00:00
70b8b96d6c
Fix a namespace issue, reported by Vladimir Merzliakov!
...
llvm-svn: 21115
2005-04-06 19:45:39 +00:00
c36b6c3b1a
steal sampo's div-by-constant-power-of-2 stuff
...
thanks sampo!!
llvm-svn: 21113
2005-04-06 09:55:17 +00:00
03c530786c
add fms instruction
...
llvm-svn: 21112
2005-04-06 09:54:09 +00:00
39ef2f1d43
Fixed version of optimized integer divide is now fixed. Calculate the
...
quotient, not the remainder. Also, make sure to remove the old div operand
from the ExprMap and let SelectExpr insert the new one.
llvm-svn: 21111
2005-04-06 06:44:57 +00:00
c0e9adf3cc
lie a bit and say that r1/r12 (GP/SP) _aren't_ callee-save, as we take
...
care of this ourselves
llvm-svn: 21110
2005-04-06 06:18:36 +00:00
df0ecbd4cc
make sure 'special' registers don't get allocated
...
llvm-svn: 21109
2005-04-06 06:17:54 +00:00
4fbb4af5d1
Add (untested) support for MULHS and MULHU.
...
llvm-svn: 21107
2005-04-06 04:21:07 +00:00
c21db6b15c
add signed versions of the extra precision multiplies
...
llvm-svn: 21106
2005-04-06 04:19:22 +00:00
dd397119b0
Turn off the div -> mul optimization until it works correctly 100% of the
...
time.
llvm-svn: 21105
2005-04-06 03:36:33 +00:00
4164c4baac
Add support for MULHS and MULHU nodes
...
Have LegalizeDAG handle SREM and UREM for us
Codegen SDIV and UDIV by constant as a multiply by magic constant instead
of integer divide, which is very slow.
llvm-svn: 21104
2005-04-06 00:25:27 +00:00
43f78bc2da
added lowerargs support for varargs
...
llvm-svn: 21101
2005-04-05 20:51:46 +00:00
524417357c
Behold, rlwinm with certain immediate arguments is printed as the much more
...
readable slwi or srwi (shift left/right word immediate).
llvm-svn: 21099
2005-04-05 18:19:50 +00:00
a188b698a2
Fix cut & paste errors (32->64), and codegen float->int more optimally.
...
llvm-svn: 21098
2005-04-05 17:32:30 +00:00
8d64e9a90d
Updated to use dep analyzer.
...
llvm-svn: 21097
2005-04-05 16:36:44 +00:00
9203e169a7
Remove 64 bit simple ISel, it never worked correctly
...
Add initial (buggy) implementation of 64 bit pattern ISel
llvm-svn: 21096
2005-04-05 08:51:15 +00:00
4bde071216
Back out the previous change to SelectBranchCC, since there are cases it
...
could miscompile. A correct solution will be found in the near future.
llvm-svn: 21095
2005-04-05 04:32:16 +00:00
9049e4beec
Rename canUseAsImmediateForOpcode to getImmediateForOpcode to better
...
indicate that it is not a boolean function.
Properly emit the pseudo instruction for conditional branch, so that we
can fix up conditional branches whose displacements are too large.
Reserve the right amount of opcode space for said pseudo instructions.
llvm-svn: 21094
2005-04-05 04:22:58 +00:00
d6933f5078
Implement SDIV by power of 2 as srawi/addze rather than load imm, divw
...
llvm-svn: 21091
2005-04-05 00:15:08 +00:00
1d5d767a09
Pattern match fp mul-add, mul-sub, neg-mul-add, and neg-mul-sub
...
llvm-svn: 21090
2005-04-04 23:40:36 +00:00
d96350095c
Add support for multiply-add, multiply-sub, and their negated versions
...
llvm-svn: 21089
2005-04-04 23:01:51 +00:00
1194531057
Make sure that arg regs used by the call instruction are marked as such, so
...
that regalloc doesn't cleverly reuse early arg regs loading later arg regs.
This fixes almost all outstanding failures in the pattern isel.
llvm-svn: 21086
2005-04-04 22:17:48 +00:00
c7186025de
Remove unnecessary register copy now that regalloc is fixed
...
llvm-svn: 21085
2005-04-04 21:48:13 +00:00
d753765460
i1 loads should also be from the low byte of the argument word.
...
llvm-svn: 21077
2005-04-04 09:09:00 +00:00
1ce4839890
Fix i64 return, fix CopyFromReg
...
llvm-svn: 21076
2005-04-04 06:52:38 +00:00
9935f44fb8
fix SREM/UREM, which gave incorrect results for x%y if x was zero. This is
...
an ugly hack, but it seems to work. I should fix this properly and add a test
as well.
fixes multisource/obsequi (maybe others)
llvm-svn: 21075
2005-04-04 05:05:52 +00:00
dbc810022b
add implicit use op
...
llvm-svn: 21074
2005-04-04 04:50:57 +00:00
629cdaea39
Full varargs support. All of UnitTests now passes
...
llvm-svn: 21070
2005-04-03 23:11:17 +00:00
7a3e929efc
Pass the correct value for the chain to the store
...
llvm-svn: 21066
2005-04-03 22:22:56 +00:00
f6dc43bd46
Fix SHL_PARTS
...
Start implementation of integer varargs
llvm-svn: 21065
2005-04-03 22:13:27 +00:00
79e727e8a7
is this simpler? I think it is simpler.
...
llvm-svn: 21064
2005-04-03 20:35:21 +00:00
7ce5740de9
fix 101 regressions
...
llvm-svn: 21063
2005-04-03 18:24:50 +00:00
6c9afaead4
.bss is no problem here.
...
llvm-svn: 21061
2005-04-03 14:52:01 +00:00
34cc5b329f
Keeping up with the Joneses.
...
Implement not, nor, nand, and eqv
llvm-svn: 21060
2005-04-03 11:20:20 +00:00
46897ab49e
Select optimization
...
llvm-svn: 21051
2005-04-02 22:32:39 +00:00
f029d795f0
Try several things. 1) drop /i from FP ops 2) factor out FP to Int moves and provide 21264 support for those 3) match not 4) match ornot andnot xornot
...
llvm-svn: 21046
2005-04-02 21:06:51 +00:00
e7ae400bc8
FNEG/FABS/UNDEF
...
llvm-svn: 21029
2005-04-02 19:11:07 +00:00
7ad3697e1e
FNEG/FABS
...
llvm-svn: 21028
2005-04-02 19:04:58 +00:00
50b339b7fa
ia64 asmprinter fixes:
...
- turn off assembler's autoalignment
- set FunctionAddrPrefix/Suffix so that .data8 entries pointing to
functions have their value wrapped in @fptr(), so that a function
descriptor will be materialized for that function.
llvm-svn: 21025
2005-04-02 12:30:47 +00:00
c935c833d1
support IDEF, fnegabs (thanks sampo)
...
llvm-svn: 21023
2005-04-02 10:33:53 +00:00
0ccac38ed3
add fnegabs op
...
llvm-svn: 21022
2005-04-02 10:06:27 +00:00
165cf4844e
Set shift amount to Extend
...
Implement ISD::FABS and ISD::FNEG nodes
Implement SHL_PARTS, SRL_PARTS, and SRA_PARTS
Generate PowerPC 'fneg', 'fabs', and 'fnabs' instructions
llvm-svn: 21018
2005-04-02 05:59:34 +00:00
0e0b599d29
add support for FABS and FNEG
...
llvm-svn: 21015
2005-04-02 05:30:17 +00:00
0720dc14ed
add support FNEG and FABS
...
llvm-svn: 21012
2005-04-02 05:18:38 +00:00
0b7e4cd107
This target doesn't support fabs/fneg yet.
...
llvm-svn: 21010
2005-04-02 05:03:24 +00:00
2d451658a6
add an fabs instr
...
llvm-svn: 21006
2005-04-02 04:31:56 +00:00
a31d4c7548
Add support for 64-bit shifts.
...
llvm-svn: 21005
2005-04-02 04:01:14 +00:00
Chris Lattner