4c07caf9d4
Make sure that Cygwin assembly includes _ as part of function names.
...
llvm-svn: 22190
2005-06-02 21:33:19 +00:00
7c0e9285ce
try custom expanders, doesn't seem to expand yet, so disabled
...
llvm-svn: 22188
2005-05-31 19:49:34 +00:00
41e2981e0a
switch to the new live in thing. Really, this time it works
...
llvm-svn: 22187
2005-05-31 18:42:18 +00:00
676e4db6dc
switch to the new live in thing
...
llvm-svn: 22186
2005-05-31 18:37:16 +00:00
973d85e660
switch to the new live in thing
...
llvm-svn: 22185
2005-05-31 18:35:43 +00:00
86f856f19c
match gcc, makes diff easier
...
llvm-svn: 22179
2005-05-27 03:39:30 +00:00
39edea8306
Fix 2005-05-12-Int64ToFP
...
The issue is there is no unsigned -> double conversion, only signed. So I
need to test the sign and do a different thing depending on it. Ideally
this should be in a different BB, but in the mean time, I use a branch
free method.
llvm-svn: 22177
2005-05-26 18:18:34 +00:00
38724d33c1
C'mon everybody, let's modify X86JITInfo.cpp. This time, we add <iostream>
...
so that the shiny new use of std::cerr is defined.
llvm-svn: 22156
2005-05-20 21:29:24 +00:00
eba2471fa3
Since everyone else has "fixed" this file, might as well join in the fun.
...
* Change assert() to std::cerr printout, as it will not appear in opt builds
* Add comments to clarify what #ifdef/#else/#endif match what condition(s)
llvm-svn: 22154
2005-05-20 19:46:50 +00:00
8deafa3378
Fix this a 3rd time :)
...
llvm-svn: 22151
2005-05-20 17:00:21 +00:00
5d37a3abae
fix compilation error due to no abort being defined. There is probably a better way to do this
...
llvm-svn: 22150
2005-05-20 16:34:44 +00:00
3a5eb61899
re-enable direct calls, this should just be a performance boost
...
llvm-svn: 22148
2005-05-20 11:39:17 +00:00
6e7355e6c1
this seems dead (and broke the ia64 build, so..)
...
llvm-svn: 22147
2005-05-20 06:21:59 +00:00
e3948c433c
Fix tail call support in VC++ builds
...
llvm-svn: 22143
2005-05-20 01:35:39 +00:00
83a6f107fb
Fastcc passes arguments in EAX and EDX, make sure the JIT doesn't clobber them
...
llvm-svn: 22137
2005-05-19 06:49:17 +00:00
57279597ab
Tailcalls require stubs to be emitted. Otherwise, the compilation callback
...
doesn't know who 'called' it.
llvm-svn: 22136
2005-05-19 05:54:33 +00:00
d5f457c47b
Wrap long lines
...
llvm-svn: 22125
2005-05-18 20:37:33 +00:00
4e5a3a6df6
PPC "branch and link" instructions are branches in the PPC sense, but not
...
in the LLVM code generator sense (they are calls). Don't mark them as such,
which fixes the regressions on the ppc tester last night
llvm-svn: 22065
2005-05-15 20:11:44 +00:00
0ae9b08916
Fix andrews changes to fit in 80 columns
...
llvm-svn: 22064
2005-05-15 19:54:37 +00:00
9f406cb29b
make angry compilers happy again
...
llvm-svn: 22054
2005-05-15 14:44:13 +00:00
1a61fa460f
don't reserve space for tailcall arg areas. It explicitly managed.
...
llvm-svn: 22050
2005-05-15 06:07:10 +00:00
97e3b65652
Teach reginfo how to deal with ADJSTACKPTRri, allowing us to generate:
...
add %ESP, 20
jmp %EDX # TAIL CALL
instead of:
add %ESP, -8
add %ESP, 28
jmp %EDX # TAIL CALL
llvm-svn: 22047
2005-05-15 05:49:58 +00:00
dd66a41e0e
Implement proper tail calls in the X86 backend for all fastcc->fastcc
...
tail calls.
llvm-svn: 22046
2005-05-15 05:46:45 +00:00
3f5a98d1f4
Add markers in the asm file for tail calls, add a new ADJSTACKPTRri
...
sorta-pseudo-instruction
llvm-svn: 22042
2005-05-15 03:10:37 +00:00
6b5fa91a63
Yes, calltarget is the operand of the day.
...
llvm-svn: 22040
2005-05-15 01:10:30 +00:00
5366c859a7
When emitting the function epilog, check to see if there already a stack
...
adjustment. If so, we merge the adjustment into the existing one. This
allows us to generate:
caller2:
sub %ESP, 12
mov DWORD PTR [%ESP], 0
mov %EAX, 1234567890
mov %EDX, 0
call func2
add %ESP, 8
ret 4
intead of:
caller2:
sub %ESP, 12
mov DWORD PTR [%ESP], 0
mov %EAX, 1234567890
mov %EDX, 0
call func2
sub %ESP, 4
add %ESP, 12
ret 4
for X86/fast-cc-merge-stack-adj.ll
llvm-svn: 22038
2005-05-14 23:53:43 +00:00
f0649db870
Add some new instructions
...
llvm-svn: 22036
2005-05-14 23:35:21 +00:00
18b2c2f13c
Pass i64 values correctly split in reg/mem to fastcc calls.
...
This fixes fourinarow with -enable-x86-fastcc.
llvm-svn: 22022
2005-05-14 12:03:10 +00:00
1b3520c90b
Use target-specific nodes for calls. This allows the fastcc code to not have
...
to do ugly hackery to avoid emitting code like this:
call foo
mov vreg, EAX
adjcallstackup ...
If foo is a fastcc call and if vreg gets spilled, we might end up with this:
call foo
mov [ESP+offset], EAX ;; Offset doesn't consider the 12!
sub ESP, 12
Which is bad. The previous hacky code to deal with this was A) gross B) not
good enough. In particular, it could miss cases and emit the bad code above.
Now we always emit this:
call foo
adjcallstackup ...
mov vreg, EAX
directly.
This makes fastcc with callees poping the stack work much better. Next
stop (finally!) really is tail calls.
llvm-svn: 22021
2005-05-14 08:48:15 +00:00
a36117b360
use a target-specific node and custom expander to lower long->FP to FILD64m.
...
This should fix some missing symbols problems on BSD and improve performance
of programs that use that operation.
llvm-svn: 22012
2005-05-14 06:52:07 +00:00
9b29fe2008
Make sure the start of the arg area and the end (after the RA is pushed)
...
is always 8-byte aligned for fastcc
llvm-svn: 21995
2005-05-13 23:49:10 +00:00
5011ff0179
fix typo
...
llvm-svn: 21991
2005-05-13 22:46:57 +00:00
2267d67941
Fix the problems with callee popped argument lists
...
llvm-svn: 21988
2005-05-13 22:13:49 +00:00
79e9fa5de1
Don't emit SAR X, 0 in the case of sdiv Y, 2
...
llvm-svn: 21986
2005-05-13 21:50:27 +00:00
7d387d207d
Fix UnitTests/2005-05-13-SDivTwo.c
...
llvm-svn: 21985
2005-05-13 21:48:20 +00:00
c0e369ed66
switch to having the callee pop stack operands for fastcc. This is currently buggy
...
do not use
llvm-svn: 21984
2005-05-13 21:44:04 +00:00
1a12476531
allow RETI
...
llvm-svn: 21980
2005-05-13 20:46:35 +00:00
8abab9b0c7
treat TAILCALL nodes identically to CALL nodes
...
llvm-svn: 21977
2005-05-13 20:29:26 +00:00
f27e31d690
Build TAILCALL nodes in LowerCallTo, treat them like normal calls everywhere.
...
llvm-svn: 21976
2005-05-13 20:29:13 +00:00
6fec835461
capitalize
...
llvm-svn: 21962
2005-05-13 19:48:34 +00:00
f4cfcc48f6
clarify that these are v9 options
...
llvm-svn: 21960
2005-05-13 19:45:45 +00:00
f9a4d96038
hide this option
...
llvm-svn: 21959
2005-05-13 19:44:21 +00:00
2e77db6af6
Add an isTailCall flag to LowerCallTo
...
llvm-svn: 21958
2005-05-13 18:50:42 +00:00
6e4c2302e6
add 'ret imm' instruction
...
llvm-svn: 21945
2005-05-13 17:56:48 +00:00
6756f2f795
Realize that we don't support fmod directly, fixing CodeGen/Generic/print-arith-fp.ll
...
llvm-svn: 21939
2005-05-13 16:20:22 +00:00
0b17b45a96
Do not CopyFromReg physregs for live-in values. Instead, create a vreg for
...
each live in, and copy the regs from the vregs. As the very first thing we
do in the function, insert copies from the pregs to the vregs. This fixes
problems where the token chain of CopyFromReg was not enough to allow reordering
of the copyfromreg nodes and other unchained nodes (e.g. div, which clobbers
eax on intel).
llvm-svn: 21932
2005-05-13 07:38:09 +00:00
2dce703710
rename the ADJCALLSTACKDOWN/ADJCALLSTACKUP nodes to be CALLSEQ_START/BEGIN.
...
llvm-svn: 21915
2005-05-12 23:24:06 +00:00
7ce7a8fc81
Add a new -enable-x86-fastcc option that enables passing the first
...
two integer values in registers for the fastcc calling conv.
llvm-svn: 21912
2005-05-12 23:06:28 +00:00
36674a123e
Pass in Calling Convention to use into LowerCallTo
...
llvm-svn: 21899
2005-05-12 19:56:45 +00:00
b5ff4e5e10
Enable pattern isel by default
...
llvm-svn: 21898
2005-05-12 19:56:09 +00:00
f80969f29b
These targets don't like setcc
...
llvm-svn: 21884
2005-05-12 02:06:00 +00:00
99fa5bc1fa
Necessary changes to codegen cttz efficiently on PowerPC
...
1. Teach LegalizeDAG how to better legalize CTTZ if the target doesn't have
CTPOP, but does have CTLZ
2. Teach PPC32 how to do sub x, const -> add x, -const for valid consts
3. Teach PPC32 how to do and (xor a, -1) b -> andc b, a
4. Teach PPC32 that ISD::CTLZ -> PPC::CNTLZW
llvm-svn: 21880
2005-05-11 23:43:56 +00:00
96726a46c7
Fixed issue that broke ssa.
...
llvm-svn: 21878
2005-05-11 21:45:03 +00:00
9c64b0cc18
fix some GCC 4 warnings
...
llvm-svn: 21877
2005-05-11 21:40:40 +00:00
72002e87cc
Added support for decomposing constant expressions containing shr and shl
...
instructions.
Review of this commit would be greatly appreciated.
llvm-svn: 21876
2005-05-11 21:16:42 +00:00
25163d8d60
add the popcount instruction and support this in the isel
...
the primary user of this will probably end up being find-first-set-bit/find-
last-set-bit, which i'll get around to...
llvm-svn: 21860
2005-05-11 05:16:09 +00:00
669c3b17eb
No really IA*64* :)
...
llvm-svn: 21858
2005-05-11 05:03:56 +00:00
05ad4b8369
X86 has more than just 32-bit registers
...
llvm-svn: 21857
2005-05-11 05:00:34 +00:00
d8145bcd5b
Convert feature of the simple isel over for the pattern isel to use.
...
llvm-svn: 21840
2005-05-10 03:53:18 +00:00
915594d884
Silence some VC++ warnings
...
llvm-svn: 21838
2005-05-10 02:22:38 +00:00
70ea07cfd2
Implement READPORT/WRITEPORT, implementing the last X86 regression tests
...
that were failing with the pattern selector. Note that the support that
existed in the simple selector was clearly broken in several ways though
(which has also been fixed).
llvm-svn: 21831
2005-05-09 21:17:38 +00:00
e53158e21d
do not emit illegal instructions
...
llvm-svn: 21830
2005-05-09 21:06:04 +00:00
46b5ca4310
Fix the syntax of the i/o instructions, these are obviously unused.
...
llvm-svn: 21829
2005-05-09 20:49:20 +00:00
6c6a39a7b8
legalize readio/writeio into load/stores, fixing CodeGen/X86/io.llx with
...
the pattern isel.
llvm-svn: 21828
2005-05-09 20:37:29 +00:00
4ccd1f603c
restore some non-dead code I removed last night breaking double casts to
...
uint
llvm-svn: 21821
2005-05-09 18:37:02 +00:00
129c5fea44
fold and (shl X, C1), C2 -> rlwinm when possible. Many other cases are possible,
...
include and (srl) and the inverses (shl and) etc.
llvm-svn: 21820
2005-05-09 17:39:48 +00:00
74a01fa211
fix and cleanup constmul code a bit, this fixes mediabench/toast and
...
probably a couple of other tests.
llvm-svn: 21814
2005-05-09 13:18:34 +00:00
daa064d8fd
Wrap long lines, remove dead code that is now handled by legalize
...
llvm-svn: 21811
2005-05-09 05:40:26 +00:00
e62661185c
Fix FP -> bool casts
...
llvm-svn: 21810
2005-05-09 05:33:18 +00:00
6972c31ab5
Fix X86/2005-05-08-FPStackifierPHI.ll: ugly gross hack.
...
llvm-svn: 21801
2005-05-09 03:36:39 +00:00
18335f8925
clean up the CBE output a bit
...
llvm-svn: 21740
2005-05-06 06:58:42 +00:00
561b7eb9e1
add tail marker as a comment
...
llvm-svn: 21739
2005-05-06 06:53:07 +00:00
b8e94c3499
fix typo
...
llvm-svn: 21693
2005-05-04 19:25:37 +00:00
aed06a0e92
Well, add support for ct* for 21264 only.
...
21164 is broken until expand works.
llvm-svn: 21692
2005-05-04 19:12:09 +00:00
5e177826fd
Implement count leading zeros (ctlz), count trailing zeros (cttz), and count
...
population (ctpop). Generic lowering is implemented, however only promotion
is implemented for SelectionDAG at the moment.
More coming soon.
llvm-svn: 21676
2005-05-03 17:19:30 +00:00
7acd5d5f06
support multiplication by constant negative integers
...
this constmul code is still buggy though, so beware. mul by 7427 is currently
broken, for example. will fix it when I get a moment :)
llvm-svn: 21652
2005-05-02 07:27:14 +00:00
0e73188c10
add support for bools to SELECT, this fixes Prolangs-C/bison from the
...
testsuite, however 09-vor is still dead (hopefully for other reasons!)
llvm-svn: 21651
2005-05-02 06:41:13 +00:00
9d43c75a55
SMS for superblocks.
...
llvm-svn: 21643
2005-05-01 01:27:47 +00:00
bdfb9e61a0
Added extra constructor for superblocks.
...
llvm-svn: 21642
2005-05-01 01:25:53 +00:00
4d0ee754e3
Fixed bug in searchPath function for finding nodes between two recurrences.
...
Changed dependence analyzer to only use dep distances of 2 or less.
This is experimental.
Changed MSchedGraph to be able to represent more then one BB (first steps).
llvm-svn: 21641
2005-04-30 23:07:59 +00:00
537332eba8
I was sure I had thought about this and there was a reason it should work.
...
But it is entirely possible I am just crazy.
llvm-svn: 21640
2005-04-30 14:19:13 +00:00
c8a6633dea
Eliminate some random whitespace
...
llvm-svn: 21637
2005-04-30 04:44:07 +00:00
9993823876
Doesn't support these nodes
...
llvm-svn: 21634
2005-04-30 04:26:56 +00:00
9c6bbafc15
This target doesn't support the FSIN/FCOS/FSQRT nodes yet
...
llvm-svn: 21633
2005-04-30 04:26:06 +00:00
db68d39a01
Add support for FSIN/FCOS when unsafe math ops are enabled. Patch contributed by
...
Morten Ofstad!
llvm-svn: 21632
2005-04-30 04:25:35 +00:00
3b20386551
Add support for llvm.sqrt and sin/cos if unsafe math optimizations are enabled.
...
llvm-svn: 21631
2005-04-30 04:12:40 +00:00
4a2cc6603d
Expose an option allowing unsafe math optimizations. Patch contributed by
...
Morten Ofstad!
llvm-svn: 21630
2005-04-30 04:09:52 +00:00
014d2c42e7
Add support for FSQRT node, patch contributed by Morten Ofstad
...
llvm-svn: 21610
2005-04-28 22:07:18 +00:00
61827484c7
Add some new X86 instrs, patch contributed by Morten Ofstad
...
llvm-svn: 21608
2005-04-28 21:50:05 +00:00
effaec5436
Codegen fabs/fabsf as FABS. Patch contributed by Morten Ofstad
...
llvm-svn: 21607
2005-04-28 21:48:42 +00:00
4a73c2cfdc
Implement Value* tracking for loads and stores in the selection DAG. This enables one to use alias analysis in the backends.
...
(TRUNK)Stores and (EXT|ZEXT|SEXT)Loads have an extra SDOperand which is a SrcValueSDNode which contains the Value*. Note that if the operation is introduced by the backend, it will still have the operand, but the value* will be null.
llvm-svn: 21599
2005-04-27 20:10:01 +00:00
b071bef66a
clean up some warnings
...
llvm-svn: 21590
2005-04-27 11:57:39 +00:00
e06ef80244
constmul bugfix: multiply by 27611 was broken
...
llvm-svn: 21564
2005-04-26 09:42:50 +00:00
bbd0cd71a8
clean up the code! (oops) lots more cleaning left, however.
...
llvm-svn: 21563
2005-04-26 08:43:47 +00:00
81ebb57771
* Add code to reduce multiplies by constant integers to shifts, adds and
...
subtracts. This is a very rough and nasty implementation of Lefevre's
"pattern finding" algorithm. With a few small changes though, it should
end up beating most other methods in common use, regardless of the size
of the constant (currently, it's often one or two shifts worse)
TODO: rewrite it so it's not hideously ugly (this is a translation from
perl, which doesn't help ;)
bypass most of it for multiplies by 2^n+1
(eventually) teach it that some combinations of shift+add are
cheaper than others (e.g. shladd on ia64, scaled adds on alpha)
get it to try multiple booth encodings in search of the cheapest
routine
make it work for negative constants
This is hacked up as a DAG->DAG transform, so once I clean it up I hope
it'll be pulled out of here and put somewhere else. The only thing backends
should really have to worry about for now is where to draw the line
between using this code vs. going ahead and doing an integer multiply
anyway.
llvm-svn: 21560
2005-04-26 07:23:02 +00:00
ff7b16c1d6
Shut GCC 4.0 up about classes that have virtual functions but a non-virtual
...
destructor. Just add the do-nothing virtual destructor.
llvm-svn: 21524
2005-04-25 02:55:55 +00:00
fd8c2265fa
Convert tabs to spaces
...
llvm-svn: 21457
2005-04-22 18:06:01 +00:00
e73e76dc42
Convert tabs to spaces
...
llvm-svn: 21452
2005-04-22 17:54:37 +00:00
e4481c7c82
Implement the --enable-targets= feature of the configure script. The make
...
variable TARGETS_TO_BUILD is used to determine which targets in lib/Target
are built and which libraries are linked into llc. This effectively
implements the feature. One item remains: disabling targets in the dejagnu
test suite.
llvm-svn: 21450
2005-04-22 17:20:11 +00:00
8f4081a8c9
keep track of max depth stats
...
llvm-svn: 21446
2005-04-22 13:35:18 +00:00
42ed14860b
Updated dependence analyzer. Fixed numerous bugs. Same stage scheduling, etc.
...
llvm-svn: 21444
2005-04-22 06:32:48 +00:00
c88330ad13
* Remove trailing whitespace
...
* Convert tabs to spaces
llvm-svn: 21426
2005-04-21 23:38:14 +00:00
b440243e94
Remove trailing whitespace
...
llvm-svn: 21425
2005-04-21 23:30:14 +00:00
89b8c8d215
Remove trailing whitespace
...
llvm-svn: 21424
2005-04-21 23:13:11 +00:00
10468d8a3c
Remove trailing whitespace
...
llvm-svn: 21422
2005-04-21 22:55:34 +00:00
3590ef1164
Match another form of eqv
...
llvm-svn: 21413
2005-04-21 21:09:11 +00:00
486a1ec909
Handle stores of global address as stores of immediates. Instead of:
...
test1:
movl $N, %eax
movl %eax, G
ret
emit:
test1:
movl $N, G
ret
llvm-svn: 21407
2005-04-21 19:11:03 +00:00
adcfc1748b
Handle (store &GV -> mem) as a store immediate. This often occurs for
...
printf format strings and other stuff. Instead of generating this:
movl $l1__2E_str_1, %eax
movl %eax, (%esp)
we now emit:
movl $l1__2E_str_1, (%esp)
llvm-svn: 21406
2005-04-21 19:03:24 +00:00
ea548c0cb1
Remove trailing whitespace, patch by Markus Oberhumer.
...
llvm-svn: 21379
2005-04-20 16:05:03 +00:00
53c40624f9
Add completely untested support for mtcrf/mfcrf encoding
...
llvm-svn: 21353
2005-04-19 05:41:52 +00:00
baa9be572b
switch over the rest of the formats that use RC to use isDOT
...
llvm-svn: 21352
2005-04-19 05:21:30 +00:00
f9172e14c9
Convert the XForm instrs and XSForm instruction over to use isDOT
...
llvm-svn: 21351
2005-04-19 05:15:18 +00:00
5b78da4571
Now that the ppc64 and vmx operands of I are always 0, forward substitute
...
them away.
llvm-svn: 21350
2005-04-19 05:05:22 +00:00
116a9e5a34
convert over bform and iform instructions
...
llvm-svn: 21349
2005-04-19 05:00:59 +00:00
b2367e398e
Convert over DForm and DSForm instructions
...
llvm-svn: 21348
2005-04-19 04:59:28 +00:00
15709c2c33
Convert XLForm and XForm instructions over to use PPC64 when appropriate.
...
llvm-svn: 21347
2005-04-19 04:51:30 +00:00
d790d22f22
Convert XO XS and XFX forms to use isPPC64
...
llvm-svn: 21346
2005-04-19 04:40:07 +00:00
c7cb8c77fb
Turn PPC64 and VMX into classes that can be added to instructions instead of
...
bits that must be passed up the inheritance hierarchy. Convert MForm and AForm
instructions over
llvm-svn: 21345
2005-04-19 04:32:54 +00:00
2331c061ee
Next round of PPC CR optimizations. For the following code:
...
int %bar(float %a, float %b, float %c, float %d) {
entry:
%tmp.1 = setlt float %a, %d
%tmp.2 = setlt float %b, %d
%or = or bool %tmp.1, %tmp.2
%tmp.3 = setgt float %c, %d
%tmp.4 = or bool %or, %tmp.3
%tmp.5 = and bool %tmp.4, true
%retval = cast bool %tmp.5 to int
ret int %retval
}
We now emit:
_bar:
.LBB_bar_0: ; entry
fcmpu cr0, f1, f4
fcmpu cr1, f2, f4
cror 0, 0, 4
fcmpu cr1, f3, f4
cror 28, 0, 5
mfcr r2
rlwinm r3, r2, 29, 31, 31
blr
Instead of:
_bar:
.LBB_bar_0: ; entry
fcmpu cr7, f1, f4
mfcr r2
rlwinm r2, r2, 29, 31, 31
fcmpu cr7, f2, f4
mfcr r3
rlwinm r3, r3, 29, 31, 31
or r2, r2, r3
fcmpu cr7, f3, f4
mfcr r3
rlwinm r3, r3, 30, 31, 31
or r3, r2, r3
blr
llvm-svn: 21321
2005-04-18 07:48:09 +00:00
602a45f415
Change codegen for setcc to read the bit directly out of the condition
...
register. Added support in the .td file for the g5-specific variant
of cr -> gpr moves that executes faster, but we currently don't
generate it.
llvm-svn: 21314
2005-04-18 02:43:24 +00:00
f281f791b5
Handle ExternalSymbol operands in the PPC JIT
...
llvm-svn: 21312
2005-04-18 00:46:10 +00:00
779c5cbb44
Make pattern isel default for ppc
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Add new ppc beta option related to using condition registers
Make pattern isel control flag (-enable-pattern-isel) global and tristate
0 == off
1 == on
2 == target default
llvm-svn: 21309
2005-04-15 22:12:16 +00:00
00ce283b3f
fix calls
...
llvm-svn: 21303
2005-04-14 17:34:20 +00:00
7ae3aba5aa
a 21264 fix, and fix the operator precidence on an and -> zap check (should fix hundreds of test cases
...
llvm-svn: 21302
2005-04-14 16:24:00 +00:00
0a7c2b9078
print negative 64 bit immediates as negative numbers, makes things a little
...
easier on the eyes, not that numbers like 18446744073709541376 are bad or
anything
llvm-svn: 21300
2005-04-14 10:08:01 +00:00
dfbbcc098b
oops, this stopped us turning movl r4=0xFFFFFFFF;; and rX, r4 into zxt4
...
llvm-svn: 21299
2005-04-14 10:06:35 +00:00
53d3eccbe2
Implement multi-way branches through logical ops on condition registers.
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This can generate considerably shorter code, reducing the size of crafty
by almost 1%. Also fix the printing of mcrf. The code is currently
disabled until it gets a bit more testing, but should work as-is.
llvm-svn: 21298
2005-04-14 09:45:08 +00:00
f6b666fb06
we have zextloads, not sextloads!
...
llvm-svn: 21296
2005-04-14 08:37:32 +00:00
65a82c562e
Add the necessary support to codegen condition register logical ops with
...
register allocated condition registers. Make sure that the printed
output is gas compatible.
llvm-svn: 21295
2005-04-14 03:20:38 +00:00
be21011911
Start allocating condition registers. Almost all explicit uses of CR0 are
...
now gone. Next step is to get rid of the remaining ones and then start
allocating bools to CRs where appropriate.
llvm-svn: 21294
2005-04-13 23:15:44 +00:00
dd1bb81d04
Implement the fold shift X, zext(Y) -> shift X, Y at the target level,
...
where it is safe to do so.
llvm-svn: 21293
2005-04-13 22:14:14 +00:00
4ddd81657b
Disbale the broken fold of shift + sz[ext] for now
...
Move the transform for select (a < 0) ? b : 0 into the dag from ppc isel
Enable the dag to fold and (setcc, 1) -> setcc for targets where setcc
always produces zero or one.
llvm-svn: 21291
2005-04-13 21:23:31 +00:00
93341a0f82
WOW, function calls still seem to work after this.
...
llvm-svn: 21286
2005-04-13 17:17:28 +00:00
c3621316ee
prepare for func call optimization
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llvm-svn: 21285
2005-04-13 16:19:50 +00:00
2f2312575b
* add the shladd instruction
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* fold left shifts of 1, 2, 3 or 4 bits into adds
This doesn't save much now, but should get a serious workout once
multiplies by constants get converted to shift/add/sub sequences.
Hold on! :)
llvm-svn: 21282
2005-04-13 06:12:04 +00:00
c7287c8eda
add matches for SxADDL and company, as well as simplify the SxADDQ code
...
llvm-svn: 21281
2005-04-13 05:19:55 +00:00
e7ef27bcfe
* if ANDing with a constant of the form:
...
0x00000..00FFF..FF
^ ^
^ ^
any number of
0's followed by
some number of
1's
then we use dep.z to just paste zeros over the input. For the special
cases where this is zxt1/zxt2/zxt4, we use those instructions instead,
because we're all about readability!!!
that's what it's about!! readability!
*twitch* ;D
llvm-svn: 21279
2005-04-13 04:50:54 +00:00
8eb82fb524
added all flavors of zap for anding
...
llvm-svn: 21276
2005-04-13 03:47:03 +00:00
60c23bd169
Fix some mysteriously missing {}'s which cause the miscompilation of
...
Olden/mst, Ptrdist/bc, Obsequi, etc.
llvm-svn: 21274
2005-04-13 03:29:53 +00:00
e0efd1fa72
remove one more occurance of this that snuck in
...
llvm-svn: 21271
2005-04-13 02:46:17 +00:00
857624f47a
Remove support for ZERO_EXTEND_INREG. This pessimizes code, genering stuff
...
like this:
ldah $1,1($31)
lda $1,-1($1)
and $0,$1,$24
instead of this:
zap $0,252,$24
To get this back, the selector should recognize the ISD::AND case where this
happens and emit the appropriate ZAP instruction.
llvm-svn: 21270
2005-04-13 02:43:40 +00:00
7f4c4179a6
Remove special handling of ZERO_EXTEND_INREG. This pessimizes code, causing
...
things like this:
mov r9 = 65535;;
and r8 = r8, r9;;
To be emitted instead of:
zxt2 r8 = r8;;
To get this back, the selector for ISD::AND should recognize this case.
llvm-svn: 21269
2005-04-13 02:41:52 +00:00
83075510ee
Elimate handling of ZERO_EXTEND_INREG. This causes the PPC backend to emit
...
andi instructions instead of rlwinm instructions for zero extend, but they
seem like they would take the same time.
llvm-svn: 21268
2005-04-13 02:40:26 +00:00
248fe6bda2
Z_E_I is gone
...
llvm-svn: 21267
2005-04-13 02:39:05 +00:00
af1c0f7a00
Fold shift by size larger than type size to undef
...
Make llvm undef values generate ISD::UNDEF nodes
llvm-svn: 21261
2005-04-12 23:12:17 +00:00
818eb6ddd2
Implement setcc op, -1 sequences
...
Remove dead setcc op, 0 sequences
Coming later: generalization of op, imm
llvm-svn: 21260
2005-04-12 21:22:28 +00:00
fd469bddac
* OK, after changing to use liveIn/liveOut instead of IDEFs,
...
to avoid redundant mov out3=r44 type instructions, we need to
tell the register allocator the truth about out? registers.
FIXME: unfortunately, since the list of allocatable registers is immutable,
we can't simply 'delete r127' from the allocation order, say, if 'out0' is
used. The only correct thing we can do is have a linear order of regs:
out7, out6 ... out2, out1, out0, r32, r33, r34 ... r126, r127
and slide a 'window' of 96 registers along this line, depending on how many
of the out? regs a function actually uses. The only downside of this is
that the out? registers will be allocated _first_, which makes the
resulting assembly ugly. :( Note this in the README. Hope this gets fixed
soon. :) (note the 3rd person speech there)
llvm-svn: 21252
2005-04-12 18:42:59 +00:00
740f93ca10
Get rid of idefs for arguments (oops)
...
llvm-svn: 21251
2005-04-12 17:47:57 +00:00
10c6eb4be2
Get rid of idefs for arguments
...
llvm-svn: 21250
2005-04-12 17:35:16 +00:00
14f72885dd
Put out* into the allocation order, allowing the register allocator to
...
coallesce moves into outgoing args.
llvm-svn: 21249
2005-04-12 15:12:51 +00:00
Reid Spencer