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Author SHA1 Message Date
Matt Arsenault 81a709503d AMDGPU: Fix high bits after division optimization 
This is essentially doing a 24-bit signed division with FP.
We need to truncate to the N bit result.

llvm-svn: 270305
 2016-05-21 01:53:33 +00:00
Tom Stellard 45bb48ea19 R600 -> AMDGPU rename 
llvm-svn: 239657
 2015-06-13 03:28:10 +00:00