Commit Graph

1014 Commits

Author SHA1 Message Date
Krzysztof Parzyszek 21dc8bdd9e [Hexagon] Add PIC support
llvm-svn: 256025
2015-12-18 20:19:30 +00:00
Krzysztof Parzyszek 4f9164d9b3 [Hexagon] Misc fixes to r255807
llvm-svn: 255811
2015-12-16 20:07:04 +00:00
Krzysztof Parzyszek 56bbf54b43 [Hexagon] Update the Hexagon packetizer
llvm-svn: 255807
2015-12-16 19:36:12 +00:00
Tobias Edler von Koch b51460cf86 [Hexagon] Make memcpy lowering thread-safe
This removes an unpleasant hack involving a global variable for special
lowering of certain memcpy calls. These are now lowered as intended in
EmitTargetCodeForMemcpy in the same way that other targets do it.

llvm-svn: 255785
2015-12-16 17:29:37 +00:00
Krzysztof Parzyszek 372bd80834 [Hexagon] Preprocess mapped instructions before lowering to MC
llvm-svn: 255653
2015-12-15 17:05:45 +00:00
Krzysztof Parzyszek 5e6f2bd0cb [Hexagon] Add "const" to function parameters in HexagonInstrInfo
llvm-svn: 255544
2015-12-14 21:32:25 +00:00
Krzysztof Parzyszek dac7102874 [Packetizer] Add AliasAnalysis as a parameter to the packetizer
This will make the depedence graph more accurate if an alias analysis
is provided. If nullptr is specified in its place, the behavior will
remain as it is currently.

llvm-svn: 255540
2015-12-14 20:35:13 +00:00
Krzysztof Parzyszek d44a1fd506 Add "const" to function arguments in DFAPacketizer
llvm-svn: 255526
2015-12-14 18:54:44 +00:00
Krzysztof Parzyszek 759a7d0ed7 [Hexagon] Subtarget features/default CPU corrections
llvm-svn: 255501
2015-12-14 15:03:54 +00:00
Cong Hou c106989fd5 Normalize MBB's successors' probabilities in several locations.
This patch adds some missing calls to MBB::normalizeSuccProbs() in several
locations where it should be called. Those places are found by checking if the
sum of successors' probabilities is approximate one in MachineBlockPlacement
pass with some instrumented code (not in this patch).


Differential revision: http://reviews.llvm.org/D15259

llvm-svn: 255455
2015-12-13 09:26:17 +00:00
Ron Lieberman e6540e244a [Hexagon] Add NewValueJump support for C4_cmpneq, C4_cmplte, C4_cmplteu
llvm-svn: 255027
2015-12-08 16:28:32 +00:00
Sanjay Patel e4b9f507cf fix 'the the '; NFC
llvm-svn: 254928
2015-12-07 19:21:39 +00:00
Craig Topper 15576e1c8f Use make_range to reduce mentions of iterator type. NFC
llvm-svn: 254872
2015-12-06 05:08:07 +00:00
Craig Topper 5c32279bee [Hexagon] Don't call getNumImplicitDefs and then iterate over the count. getNumImplicitDefs contains a loop so its better to just loop over the null terminated implicit def list. NFC
llvm-svn: 254852
2015-12-05 17:34:07 +00:00
Craig Topper e5e035a3a8 Replace uint16_t with the MCPhysReg typedef in many places. A lot of physical register arrays already use this typedef.
llvm-svn: 254843
2015-12-05 07:13:35 +00:00
Krzysztof Parzyszek f1b3e5e52e [Hexagon] Simplify LowerCONCAT_VECTORS, handle different types better
llvm-svn: 254724
2015-12-04 16:18:15 +00:00
Colin LeMahieu 4c606e66a7 [Hexagon] Using multiply instead of shift on signed number which can be UB
llvm-svn: 254719
2015-12-04 15:48:45 +00:00
Colin LeMahieu 15ca65c253 [Hexagon] Adding shuffling resources for HVX instructions and tests for instruction encodings.
llvm-svn: 254652
2015-12-03 21:44:28 +00:00
Krzysztof Parzyszek 7709aa0e07 [Hexagon] Remove variable unused in NDEBUG build
llvm-svn: 254623
2015-12-03 17:53:34 +00:00
Krzysztof Parzyszek c168c0165c [Hexagon] Implement CONCAT_VECTORS for HVX using V6_vcombine
llvm-svn: 254617
2015-12-03 16:47:20 +00:00
Colin LeMahieu 7c572b2125 [Hexagon] NFC Using canonicalizePacket to compound/duplex/pad packets rather than doing it separately. This also ensures the integrated assembler path matches the assembly parser path.
llvm-svn: 254616
2015-12-03 16:37:21 +00:00
Krzysztof Parzyszek 25ddd2c9e8 [Hexagon] Fix instruction descriptor flags for memory access size
llvm-svn: 254613
2015-12-03 15:41:33 +00:00
Krzysztof Parzyszek 8d8b229de9 [Hexagon] Improve lowering of instructions to the MC layer
- Add extenders when necessary.
- Handle some basic relocations.

This should fix the failure in tools/clang/test/CodeGenCXX/crash.cpp

llvm-svn: 254564
2015-12-02 23:08:29 +00:00
Alexey Samsonov 44ff204fad Fixup for r254547: use format_hex() to simplify code.
llvm-svn: 254560
2015-12-02 22:59:22 +00:00
Alexey Samsonov bcfabaa05b [Hexagon] Remove std::hex in favor of format().
std::hex is not used anywhere in LLVM code base except for this place,
and it has a known undefined behavior (at least in libstdc++ 4.9.3):
https://llvm.org/bugs/show_bug.cgi?id=18156, which fires in UBSan
bootstrap of LLVM.

llvm-svn: 254547
2015-12-02 21:13:43 +00:00
Krzysztof Parzyszek de25ecfa62 [Hexagon] Remove TFRI_V4 instruction, use existing A2_tfrsi instead
llvm-svn: 254539
2015-12-02 19:44:35 +00:00
Tim Northover f520eff782 AArch64: use ldxp/stxp pair to implement 128-bit atomic loads.
The ARM ARM is clear that 128-bit loads are only guaranteed to have been atomic
if there has been a corresponding successful stxp. It's less clear for AArch32, so
I'm leaving that alone for now.

llvm-svn: 254524
2015-12-02 18:12:57 +00:00
Craig Topper ddc76f2bed [Hexagon] Use std::begin() and std::end() instead of doing the same manually. NFC
llvm-svn: 254385
2015-12-01 06:13:10 +00:00
Craig Topper d824f5f0d9 [Hexagon] Use array_lengthof and const correct and type correct the array and array size. NFC
llvm-svn: 254384
2015-12-01 06:13:08 +00:00
Craig Topper 6261e1b94d Use array_lengthof instead of manually calculating it. NFC
llvm-svn: 254383
2015-12-01 06:13:06 +00:00
Craig Topper 3da000c07f [Hexagon] Use ArrayRef to avoid needing to calculate an array size. Interestingly the original code may have had a bug because it was passing the byte size of a uint16_t array instead of the number of entries.
llvm-svn: 254382
2015-12-01 06:13:04 +00:00
Cong Hou d97c100dc4 Replace all weight-based interfaces in MBB with probability-based interfaces, and update all uses of old interfaces.
(This is the second attempt to submit this patch. The first caused two assertion
 failures and was reverted. See https://llvm.org/bugs/show_bug.cgi?id=25687)

The patch in http://reviews.llvm.org/D13745 is broken into four parts:

1. New interfaces without functional changes (http://reviews.llvm.org/D13908).
2. Use new interfaces in SelectionDAG, while in other passes treat probabilities
as weights (http://reviews.llvm.org/D14361).
3. Use new interfaces in all other passes.
4. Remove old interfaces.

This patch is 3+4 above. In this patch, MBB won't provide weight-based
interfaces any more, which are totally replaced by probability-based ones.
The interface addSuccessor() is redesigned so that the default probability is
unknown. We allow unknown probabilities but don't allow using it together
with known probabilities in successor list. That is to say, we either have a
list of successors with all known probabilities, or all unknown
probabilities. In the latter case, we assume each successor has 1/N
probability where N is the number of successors. An assertion checks if the
user is attempting to add a successor with the disallowed mixed use as stated
above. This can help us catch many misuses.

All uses of weight-based interfaces are now updated to use probability-based
ones.


Differential revision: http://reviews.llvm.org/D14973

llvm-svn: 254377
2015-12-01 05:29:22 +00:00
Hans Wennborg 1dbaf67537 Revert r254348: "Replace all weight-based interfaces in MBB with probability-based interfaces, and update all uses of old interfaces."
and the follow-up r254356: "Fix a bug in MachineBlockPlacement that may cause assertion failure during BranchProbability construction."

Asserts were firing in Chromium builds. See PR25687.

llvm-svn: 254366
2015-12-01 03:49:42 +00:00
Cong Hou fa1917c673 Replace all weight-based interfaces in MBB with probability-based interfaces, and update all uses of old interfaces.
The patch in http://reviews.llvm.org/D13745 is broken into four parts:

1. New interfaces without functional changes (http://reviews.llvm.org/D13908).
2. Use new interfaces in SelectionDAG, while in other passes treat probabilities
as weights (http://reviews.llvm.org/D14361).
3. Use new interfaces in all other passes.
4. Remove old interfaces.

This patch is 3+4 above. In this patch, MBB won't provide weight-based
interfaces any more, which are totally replaced by probability-based ones.
The interface addSuccessor() is redesigned so that the default probability is
unknown. We allow unknown probabilities but don't allow using it together
with known probabilities in successor list. That is to say, we either have a
list of successors with all known probabilities, or all unknown
probabilities. In the latter case, we assume each successor has 1/N
probability where N is the number of successors. An assertion checks if the
user is attempting to add a successor with the disallowed mixed use as stated
above. This can help us catch many misuses.

All uses of weight-based interfaces are now updated to use probability-based
ones.


Differential revision: http://reviews.llvm.org/D14973

llvm-svn: 254348
2015-12-01 00:02:51 +00:00
Colin LeMahieu e6241798c9 [Hexagon] NFC Reordering headers.
llvm-svn: 254307
2015-11-30 17:32:34 +00:00
Krzysztof Parzyszek 08ff8883fd [Hexagon] Lowering of V60/HVX vector types
llvm-svn: 254168
2015-11-26 18:38:27 +00:00
Krzysztof Parzyszek 4eb6d4d1f2 [Hexagon] Hexagon V60 HVX intrinsic defintions
Author: Ron Lieberman <ronl@codeaurora.org>
llvm-svn: 254165
2015-11-26 16:54:33 +00:00
Krzysztof Parzyszek 195dc8d0db [Hexagon] HVX vector register classes and more isel patterns
llvm-svn: 254132
2015-11-26 04:33:11 +00:00
Krzysztof Parzyszek 70a134d29f [Hexagon] Treat transfers of FP immediates are pseudo instructions
This is a temporary fix to address ICE on 2005-10-21-longlonggtu.ll.
The proper fix will be to use A2_tfrsi, but it will need more work to
teach all users of A2_tfrsi to also expect a floating-point operand.

llvm-svn: 254099
2015-11-25 21:40:03 +00:00
Krzysztof Parzyszek 207c13f254 Add hexagonv55 and hexagonv60 as recognized CPUs, make v60 the default
llvm-svn: 254089
2015-11-25 20:30:59 +00:00
Krzysztof Parzyszek aa93575b7e [Hexagon] Add missing include of <cctype>
Lack thereof breaks Windows builds due to the use of std::isspace
in HexagonInstrInfo.cpp.

llvm-svn: 253987
2015-11-24 15:11:13 +00:00
Krzysztof Parzyszek b9a1c3a32c [Hexagon] Bring HexagonInstrInfo up to date
llvm-svn: 253986
2015-11-24 14:55:26 +00:00
Krzysztof Parzyszek 29d23f9f4c [Hexagon] Update instruction formats
llvm-svn: 253867
2015-11-23 14:09:26 +00:00
Krzysztof Parzyszek b46557292c Hexagon V60/HVX DFA scheduler support
Extended DFA tablegen to:
  - added "-debug-only dfa-emitter" support to llvm-tblgen

  - defined CVI_PIPE* resources for the V60 vector coprocessor

  - allow specification of multiple required resources
    - supports ANDs of ORs
    - e.g. [SLOT2, SLOT3], [CVI_MPY0, CVI_MPY1] means:
           (SLOT2 OR SLOT3) AND (CVI_MPY0 OR CVI_MPY1)

  - added support for combo resources
    - allows specifying ORs of ANDs
    - e.g. [CVI_XLSHF, CVI_MPY01] means:
           (CVI_XLANE AND CVI_SHIFT) OR (CVI_MPY0 AND CVI_MPY1)

  - increased DFA input size from 32-bit to 64-bit
    - allows for a maximum of 4 AND'ed terms of 16 resources

  - supported expressions now include:

    expression     => term [AND term] [AND term] [AND term]
    term           => resource [OR resource]*
    resource       => one_resource | combo_resource
    combo_resource => (one_resource [AND one_resource]*)

Author: Dan Palermo <dpalermo@codeaurora.org>

kparzysz: Verified AMDGPU codegen to be unchanged on all llc
tests, except those dealing with instruction encodings.

Reapply the previous patch, this time without circular dependencies.

llvm-svn: 253793
2015-11-21 20:00:45 +00:00
Krzysztof Parzyszek 4ca21fc1aa Revert r253790: it breaks all builds for some reason.
llvm-svn: 253791
2015-11-21 17:38:33 +00:00
Krzysztof Parzyszek 220a9bc018 Hexagon V60/HVX DFA scheduler support
Extended DFA tablegen to:
  - added "-debug-only dfa-emitter" support to llvm-tblgen

  - defined CVI_PIPE* resources for the V60 vector coprocessor

  - allow specification of multiple required resources
    - supports ANDs of ORs
    - e.g. [SLOT2, SLOT3], [CVI_MPY0, CVI_MPY1] means:
           (SLOT2 OR SLOT3) AND (CVI_MPY0 OR CVI_MPY1)

  - added support for combo resources
    - allows specifying ORs of ANDs
    - e.g. [CVI_XLSHF, CVI_MPY01] means:
           (CVI_XLANE AND CVI_SHIFT) OR (CVI_MPY0 AND CVI_MPY1)

  - increased DFA input size from 32-bit to 64-bit
    - allows for a maximum of 4 AND'ed terms of 16 resources

  - supported expressions now include:

    expression     => term [AND term] [AND term] [AND term]
    term           => resource [OR resource]*
    resource       => one_resource | combo_resource
    combo_resource => (one_resource [AND one_resource]*)

Author: Dan Palermo <dpalermo@codeaurora.org>

kparzysz: Verified AMDGPU codegen to be unchanged on all llc
tests, except those dealing with instruction encodings.

llvm-svn: 253790
2015-11-21 17:23:52 +00:00
Krzysztof Parzyszek 6c5ca95814 [Hexagon] Fix the return value from HexagonGenInsert::runOnMachineFunction
llvm-svn: 253705
2015-11-20 20:46:23 +00:00
Tilmann Scheller 4cd1d51a4d [Hexagon] Remove redundant assignment.
Identified by the Clang static analyzer.

llvm-svn: 253664
2015-11-20 13:27:30 +00:00
Tilmann Scheller bfd7ce01ea [Hexagon] Remove redundant local variable.
Identified by the Clang static analyzer.

llvm-svn: 253660
2015-11-20 12:10:17 +00:00
Craig Topper 66059c9f4d Replace dyn_cast with isa in places that weren't using the returned value for more than a boolean check. NFC.
llvm-svn: 253441
2015-11-18 07:07:59 +00:00