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230 Commits

Author SHA1 Message Date
Jyotsna Verma ce1be1130f Hexagon: Set isPredicatedNew flag on predicate new instructions. 
llvm-svn: 179388
 2013-04-12 18:01:06 +00:00
Jyotsna Verma bea8327fcb Hexagon: Set isPredicatedFlase flag for all the instructions with negated predication. 
llvm-svn: 179387
 2013-04-12 17:46:52 +00:00
Jyotsna Verma a929ab58c0 Hexagon: Expand br_cc. 
It fixes following tests for Hexagon:

CodeGen/Generic/2003-07-29-BadConstSbyte.ll
CodeGen/Generic/2005-10-21-longlonggtu.ll
CodeGen/Generic/2009-04-28-i128-cmp-crash.ll
CodeGen/Generic/MachineBranchProb.ll
CodeGen/Generic/builtin-expect.ll
CodeGen/Generic/pr12507.ll

llvm-svn: 178794
 2013-04-04 21:18:26 +00:00
Duncan Sands fee96f832d Remove unused typedef. 
llvm-svn: 178462
 2013-04-01 13:46:15 +00:00
Duncan Sands e1aa194aab There is no longer any need to silence this compiler warning as the warning has 
been turned off globally.

llvm-svn: 178451
 2013-03-31 17:44:09 +00:00
Jyotsna Verma add82b3c75 Hexagon: Add emitFrameIndexDebugValue function to emit debug information. 
llvm-svn: 178368
 2013-03-29 21:09:53 +00:00
Jyotsna Verma 26226cea4b Hexagon: Disable DwarfUsesInlineInfoSection flag. 
llvm-svn: 178345
 2013-03-29 15:46:12 +00:00
Jyotsna Verma a46059b74d Hexagon: Replace switch-case in isDotNewInst with TSFlags. 
llvm-svn: 178281
 2013-03-28 19:44:04 +00:00
Jyotsna Verma 27c06f3322 Hexagon: Enable SupportDebugInfomation and DwarfInSection flags. 
llvm-svn: 178279
 2013-03-28 19:34:49 +00:00
Jyotsna Verma 93e740485f Hexagon: Use multiclass for gp-relative instructions. 
Remove noV4T gp-relative instructions.

llvm-svn: 178246
 2013-03-28 16:25:57 +00:00
Tim Northover d3490dc06a Switch to LLVM support function abs64 to keep VS2008 happy. 
llvm-svn: 178141
 2013-03-27 13:15:08 +00:00
Jyotsna Verma 653d8839c8 Hexagon: Disable optimizations at O0. 
llvm-svn: 178132
 2013-03-27 11:14:24 +00:00
Jyotsna Verma 15957b129f Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth. 
llvm-svn: 178032
 2013-03-26 15:43:57 +00:00
Jyotsna Verma f299668aeb Hexagon: Remove HexagonMCInst.h file. It has been replaced with MCTargetDesc/HexagonMCInst.h. 
llvm-svn: 178030
 2013-03-26 15:34:22 +00:00
Jyotsna Verma fdc660bf2e Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and word. 
llvm-svn: 177747
 2013-03-22 18:41:34 +00:00
Jyotsna Verma ec613665c2 Hexagon: Removed asserts regarding alignment and offset. 
We are warning the user about the alignment, so we should not assert.

llvm-svn: 177103
 2013-03-14 19:08:03 +00:00
Jakub Staszak df17ddd56b Cleanup #includes. 
llvm-svn: 176787
 2013-03-10 13:11:23 +00:00
Tom Stellard b1588fc057 DAGCombiner: Use correct value type for checking legality of BR_CC v3 
LegalizeDAG.cpp uses the value of the comparison operands when checking
the legality of BR_CC, so DAGCombiner should do the same.

v2:
  - Expand more BR_CC value types for NVPTX

v3:
  - Expand correct BR_CC value types for Hexagon, Mips, and XCore.

llvm-svn: 176694
 2013-03-08 15:36:57 +00:00
Jyotsna Verma 7825e064b9 Hexagon: Add patterns for zero extended loads from i1->i64. 
llvm-svn: 176689
 2013-03-08 14:15:15 +00:00
Jyotsna Verma c7dcc2fbc5 Hexagon: Handle i8, i16 and i1 Var Args. 
llvm-svn: 176647
 2013-03-07 20:28:34 +00:00
Jyotsna Verma 2ba0c0b927 Hexagon: Add support to lower block address. 
llvm-svn: 176637
 2013-03-07 19:10:28 +00:00
Jyotsna Verma 457801f7ab reverting patch 176508. 
llvm-svn: 176513
 2013-03-05 20:29:23 +00:00
Jyotsna Verma 7179e712dd Hexagon: Add support for lowering block address. 
llvm-svn: 176508
 2013-03-05 19:37:46 +00:00
Jyotsna Verma 0eeea14e3e Hexagon: Expand addc, adde, subc and sube. 
llvm-svn: 176505
 2013-03-05 19:04:47 +00:00
Jyotsna Verma f1214a8ab7 Hexagon: Use MO operand flags to mark constant extended instructions. 
llvm-svn: 176500
 2013-03-05 18:51:42 +00:00
Jyotsna Verma f4e324f4fb Hexagon: Add encoding bits to the TFR64 instructions. 
Set imMoveImm, isAsCheapAsAMove flags for TFRI instructions.

llvm-svn: 176499
 2013-03-05 18:42:28 +00:00
Andrew Trick 63474629e8 Added FIXME for future Hexagon cleanup. 
llvm-svn: 176400
 2013-03-02 01:43:08 +00:00
Jyotsna Verma 8425643728 Hexagon: Add constant extender support framework. 
llvm-svn: 176358
 2013-03-01 17:37:13 +00:00
Andrew Trick 57ecf603c4 Remove code copied from GenRegisterInfo.inc. 
There's no apparent reason this code was copied from generated source
into a .cpp. It sets a bad example for those working on other targets
and trying to understand the register info API.

llvm-svn: 175849
 2013-02-22 01:15:08 +00:00
Eli Bendersky 8da87163ca Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo 
to TargetFrameLowering, where it belongs. Incidentally, this allows us
to delete some duplicated (and slightly different!) code in TRI.

There are potentially other layering problems that can be cleaned up
as a result, or in a similar manner.

The refactoring was OK'd by Anton Korobeynikov on llvmdev.

Note: this touches the target interfaces, so out-of-tree targets may
be affected.

llvm-svn: 175788
 2013-02-21 20:05:00 +00:00
Anshuman Dasgupta d062c70444 Hexagon: Expand cttz, ctlz, and ctpop for now. 
llvm-svn: 175783
 2013-02-21 19:39:40 +00:00
Jim Grosbach 341ad3e72a Update TargetLowering ivars for name policy. 
http://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly

ivars should be camel-case and start with an upper-case letter. A few in
TargetLowering were starting with a lower-case letter.

No functional change intended.

llvm-svn: 175667
 2013-02-20 21:13:59 +00:00
Jyotsna Verma 7503a62bce Hexagon: Move HexagonMCInst.h to MCTargetDesc/HexagonMCInst.h. 
Add HexagonMCInst class which adds various Hexagon VLIW annotations.
In addition, this class also includes some APIs related to the
constant extenders.

llvm-svn: 175634
 2013-02-20 16:13:27 +00:00
Jyotsna Verma e758da2080 Hexagon: Sync TSFlags in MCTargetDesc/HexagonBaseInfo.h with 
HexagonInstrFormats.td.

llvm-svn: 175537
 2013-02-19 18:18:36 +00:00
Jyotsna Verma a556848131 Hexagon: Set appropriate TSFlags to the loads/stores with global address to 
support constant extension.

This patch doesn't introduce any functionality changes.

llvm-svn: 175280
 2013-02-15 17:52:07 +00:00
Jyotsna Verma de722193e5 Hexagon: Change insn class to support instruction encoding. 
This patch doesn't introduce any functionality changes.
It adds some new fields to the Hexagon instruction classes and
changes their layout to support instruction encoding.

llvm-svn: 175205
 2013-02-14 19:57:17 +00:00
Jyotsna Verma 3545d2fc41 Hexagon: Use multiclass for absolute addressing mode loads. 
This patch doesn't introduce any functionality changes.

llvm-svn: 175187
 2013-02-14 18:15:29 +00:00
Anshuman Dasgupta e96f804eba Hexagon: add support for predicate-GPR copies. 
llvm-svn: 175102
 2013-02-13 22:56:34 +00:00
Jyotsna Verma d92252469e Hexagon: Use absolute addressing mode loads/stores for global+offset 
instead of redefining separate instructions for them.

llvm-svn: 175086
 2013-02-13 21:38:46 +00:00
Andrew Trick 553e0fe365 MIsched: HazardRecognizers are created for each DAG. Free them. 
llvm-svn: 175067
 2013-02-13 19:22:27 +00:00
Jyotsna Verma 39f7a2b7a0 Hexagon: Add support to generate predicated absolute addressing mode 
instructions.

llvm-svn: 174973
 2013-02-12 16:06:23 +00:00
Krzysztof Parzyszek 9a278f108a Extend Hexagon hardware loop generation to handle various additional cases: 
- variety of compare instructions,
- loops with no preheader,
- arbitrary lower and upper bounds.

llvm-svn: 174904
 2013-02-11 21:37:55 +00:00
Krzysztof Parzyszek cfe285e604 Implement HexagonInstrInfo::analyzeCompare. 
llvm-svn: 174901
 2013-02-11 20:04:29 +00:00
Jyotsna Verma 6031625b03 Hexagon: Use TFR_cond with cmpb.[eq,gt,gtu] to handle 
zext( set[ne,eq,gt,ugt] (...) ) type of dag patterns.

llvm-svn: 174429
 2013-02-05 19:20:45 +00:00
Jyotsna Verma 50ca6dd8a7 Hexagon: Use multiclass for absolute addressing mode stores. 
llvm-svn: 174412
 2013-02-05 18:15:34 +00:00
Jakob Stoklund Olesen 0af477c3b1 Move MRI liveouts to Hexagon return instructions. 
llvm-svn: 174407
 2013-02-05 18:08:43 +00:00
Jyotsna Verma 6f635b5488 Hexagon: Add V4 compare instructions. Enable relationship mapping 
for the existing instructions.

llvm-svn: 174389
 2013-02-05 16:42:24 +00:00
Jyotsna Verma 7ab68fbd1d Hexagon: Add V4 combine instructions and some more Def Pats for V2. 
llvm-svn: 174331
 2013-02-04 15:52:56 +00:00
Jyotsna Verma 2ceafa6684 Replace LDriu*[bhdw]_indexed_V4 instructions with "def Pats". 
llvm-svn: 174193
 2013-02-01 16:36:16 +00:00
Jyotsna Verma d6eda1c227 Add appropriate TSFlags to the instructions that must be always extended. 
llvm-svn: 174186
 2013-02-01 15:54:43 +00:00