Commit Graph

43 Commits

Author SHA1 Message Date
Sean Fertile e0e586b997 [PPC64] Helper for offset from a function's global entry to local entry. [NFC]
The PPC64 elf V2 abi defines 2 entry points for a function. There are a few
places we need to calculate the offset from the global entry to the local entry
and how this is done is not straight forward. This patch adds a helper function
mostly for documentation purposes, explaining how the 2 entry points differ and
why we choose one over the other, as well as documenting how the offsets are
encoded into a functions st_other field.

Differential Revision: https://reviews.llvm.org/D52231

llvm-svn: 342603
2018-09-20 00:26:47 +00:00
Sean Fertile 7f3f05e0b7 [PPC64] Optimize redundant instructions in global access sequences.
The access sequence for global variables in the medium and large code models use
2 instructions to add an offset to the toc-pointer. If the offset fits whithin
16-bits then the instruction that sets the high 16 bits is redundant.

This patch adds the --toc-optimize option, (on by default) and enables rewriting
of 2 instruction global variable accesses into 1 when the offset from the
TOC-pointer to the variable (or .got entry) fits in 16 signed bits. eg

addis %r3, %r2, 0           -->     nop
addi  %r3, %r3, -0x8000     -->     addi %r3, %r2, -0x8000

This rewriting can be disabled with the --no-toc-optimize flag

Differential Revision: https://reviews.llvm.org/D49237

llvm-svn: 342602
2018-09-20 00:26:44 +00:00
Sean Fertile 72435e5701 [PPC64] Support relaxing R_PPC64_TLSGD16 in TlsGdtoLe relaxation.
A General-dynamic tls access can be written using a R_PPC64_TLSGD16 relocation
if the target got entry is within 16 bits of the TOC-base. This patch adds
support for R_PPC64_TLSGD16 by relaxing it the same as a R_PPC64_GOT_TLSGD16_LO.

Differential Revision: https://reviews.llvm.org/D52055

llvm-svn: 342411
2018-09-17 20:27:02 +00:00
Sean Fertile eed3e43e54 [PPC64] Helpers for read/write an instr while relocating a half16 type. [NFC]
There are a growing number of places when we either want to read or write an
instruction when handling a half16 relocation type. On big-endian the buffer
pointer is pointing into the middle of the word we want and on little-endian it
is pointing to the start of the word. These 2 helpers are to simplify reading
and writing in these contexts.

Differential Revision: https://reviews.llvm.org/D52115

llvm-svn: 342410
2018-09-17 20:27:00 +00:00
Sean Fertile 4d354e1199 [PPC64] Fix DQ-form instruction handling and emit error for misalignment.
Relanding r340564, original commit message:

Fixes the handling of *_DS relocations used on DQ-form instructions where we
were overwriting some of the extended opcode bits. Also adds an alignment check
so that the user will receive a diagnostic error if the value we are writing
is not properly aligned.

Differential Revision: https://reviews.llvm.org/D51124

llvm-svn: 340832
2018-08-28 15:16:01 +00:00
Sean Fertile 1542b0aef5 Revert "[PPC64] Fix DQ-form instruction handling and emit error for misalign..."
This reverts commit 5125b44dbb5d06b715213e4bec75c7346bfcc7d3.
ppc64-dq.s and ppc64-error-missaligned-dq.s fail on several of the build-bots.
Reverting to investigate.

llvm-svn: 340568
2018-08-23 19:10:40 +00:00
Sean Fertile a6b2ab7a91 [PPC64] Fix DQ-form instruction handling and emit error for misalignment.
Fixes the handling of *_DS relocations used on DQ-form instructions where we
were overwriting some of the extended opcode bits. Also adds an alignment check
so that the user will receive a diagnostic error if the value we are writing
is not properly aligned.

Differential Revision: https://reviews.llvm.org/D51124

llvm-svn: 340564
2018-08-23 18:35:09 +00:00
Zaara Syeda 662d146c5b [PPC64] Add TLS initial exec to local exec relaxation
This patch adds the target call back relaxTlsIeToLe to support TLS relaxation
from initial exec to local exec model.

Differential Revision: https://reviews.llvm.org/D48091

llvm-svn: 340281
2018-08-21 15:13:53 +00:00
Zaara Syeda 75c348a097 [PPC64] Add TLS local dynamic to local exec relaxation
This patch adds the target call back relaxTlsLdToLe to support TLS relaxation
from local dynamic to local exec model.

Differential Revision: https://reviews.llvm.org/D48293

llvm-svn: 336559
2018-07-09 16:35:51 +00:00
Rui Ueyama a8db71f06f Remove redundnat call of makeArrayRef(). NFC.
llvm-svn: 336378
2018-07-05 17:14:33 +00:00
Rui Ueyama 5ba7266761 Simplify PPC64::calcEFlags().
In this file we only have to handle the v2 ABI, so what we need to do
is to just make sure that all object files have v2 or unspecified version
number.

Differential Revision: https://reviews.llvm.org/D48112

llvm-svn: 336372
2018-07-05 16:58:42 +00:00
Zaara Syeda de54f584cc [PPC64] Add support for R_PPC64_GOT_DTPREL16* relocations
The local dynamic TLS access on PPC64 ELF v2 ABI uses R_PPC64_GOT_DTPREL16*
relocations when a TLS variables falls outside 2 GB of the thread storage
block. This patch adds support for these relocations by adding a new RelExpr
called R_TLSLD_GOT_OFF which emits a got entry for the TLS variable relative
to the dynamic thread pointer using the relocation R_PPC64_DTPREL64. It then
evaluates the R_PPC64_GOT_DTPREL16* relocations as the got offset for the
R_PPC64_DTPREL64 got entries.

Differential Revision: https://reviews.llvm.org/D48484

llvm-svn: 335732
2018-06-27 13:55:41 +00:00
Zaara Syeda 1cdd816c12 [PPC64] Add TLS global dynamic to local exec relaxation
This patch adds the target call back relaxTlsGdToLe to support TLS relaxation
from global dynamic to local exec model.

The relaxation performs the following transformation:
addis r3, r2, x@got@tlsgd@ha --> nop
addi r3, r3, x@got@tlsgd@l   --> addis r3, r13, x@tprel@ha
bl __tls_get_addr(x@tlsgd)   --> nop
nop                          --> addi r3, r3, x@tprel@l

Differential Revision: https://reviews.llvm.org/D48082

llvm-svn: 335730
2018-06-27 13:27:29 +00:00
Sean Fertile f60cb34c91 [PPC64] Thread-local storage general-dynamic to initial-exec relaxation.
Patch adds support for relaxing the general-dynamic tls sequence to
initial-exec.

the relaxation performs the following transformation:
addis r3, r2, x@got@tlsgd@ha --> addis r3, r2, x@got@tprel@ha
addi r3, r3, x@got@tlsgd@l   --> ld r3, x@got@tprel@l(r3)
bl __tls_get_addr(x@tlsgd)   --> nop
nop                          --> add r3, r3, r13

and instead of emitting a DTPMOD64/DTPREL64 pair for x, we emit a single
R_PPC64_TPREL64.

Differential Revision: https://reviews.llvm.org/D48090

llvm-svn: 335651
2018-06-26 19:38:18 +00:00
Rui Ueyama 92b931d519 Use shorter names for #lo, #hi, #ha, etc. NFC.
Since these functions are file-local, the new names shouldn't be ambiguous.

Differential Revision: https://reviews.llvm.org/D48093

llvm-svn: 334564
2018-06-13 00:50:17 +00:00
Fangrui Song 3773c196fc [ELF][PPC64] Support R_PPC64_DTPREL64 which may be emitted in .rela.debug_addr
llvm-svn: 334533
2018-06-12 20:26:49 +00:00
Sean Fertile e6b2e06f28 [PPC64] Support R_PPC64_DTPREL relocations.
Patch adds support for most of the dynamic thread pointer based relocations
for local-dynamic tls. The HIGH and HIGHA versions are missing becuase they
are not supported by the llvm integrated assembler yet.

llvm-svn: 334465
2018-06-12 01:47:02 +00:00
Zaara Syeda 4455b37666 [PPC64] Add support for local-exec TLS model
This patch adds the relocations needed support the local-exec TLS model:

R_PPC64_TPREL16
R_PPC64_TPREL16_HA
R_PPC64_TPREL16_LO
R_PPC64_TPREL16_HI
R_PPC64_TPREL16_DS
R_PPC64_TPREL16_LO_DS
R_PPC64_TPREL16_HIGHER
R_PPC64_TPREL16_HIGHERA
R_PPC64_TPREL16_HIGHEST
R_PPC64_TPREL16_HIGHESTA

Differential Revision: https://reviews.llvm.org/D47598

llvm-svn: 334304
2018-06-08 17:04:09 +00:00
Zaara Syeda e4da09f920 [PPC64] Add support for initial-exec TLS model
This patch adds the relocations needed support the initial-exec TLS model:
R_PPC64_GOT_TPREL16_HA
R_PPC64_GOT_TPREL16_LO_DS
R_PPC64_GOT_TPREL16_DS
R_PPC64_GOT_TPREL16_HI
R_PPC64_TLS

Differential Revision: https://reviews.llvm.org/D47455

llvm-svn: 333769
2018-06-01 15:20:56 +00:00
Sean Fertile 1a8343fce3 [PPC64] Support R_PPC64_GOT_TLSLD16 relocations.
Add support for the R_PPC64_GOT_TLSLD16 relocations used to build the address of
the tls_index struct used in local-dynamic tls.

Differential Revision: https://reviews.llvm.org/D47538

llvm-svn: 333681
2018-05-31 18:44:12 +00:00
Sean Fertile ef0f7496d1 [PPC64] Support General-Dynamic tls.
Adds handling of all the relocation types for general-dynamic thread local
storage.

Differential Revision: https://reviews.llvm.org/D47325

llvm-svn: 333420
2018-05-29 14:34:38 +00:00
Sean Fertile fd69969e54 [PPC64] Set the IRelative relocation type.
Set the IRelative relocation type and extend the related test to verify.
Differential Revision: https://reviews.llvm.org/D46877

llvm-svn: 333203
2018-05-24 16:32:14 +00:00
Zaara Syeda 6b8b868db5 [ELF][PPC64] Fix getRelExpr for R_PPC64_REL64
The relocation R_PPC64_REL64 should return R_PC for getRelExpr since it
computes S + A - P.

Differential Revision: https://reviews.llvm.org/D46766

llvm-svn: 332259
2018-05-14 16:39:45 +00:00
Zaara Syeda c87e16718f [ELF][PPC64] Fix getRelExpr for R_PPC64_REL32
The relocation R_PPC64_REL32 should return R_PC for getRelExpr since it
computes S + A - P.

Differential Revision: https://reviews.llvm.org/D46586

llvm-svn: 332252
2018-05-14 15:26:44 +00:00
Sean Fertile 49914cc807 [PPC64] Add lazy symbol resolution stubs.
Adds support for .glink resolver stubs from the example implementation in the V2
ABI (Section 4.2.5.3. Procedure Linkage Table). The stubs are written to the
PltSection, and the sections are renamed to match the PPC64 ABI:
    .got.plt --> .plt    Type = SHT_NOBITS
    .plt     --> .glink

And adds the DT_PPC64_GLINK dynamic tag to the dynamic section when the plt is
not empty.

Differential Revision: https://reviews.llvm.org/D45642

llvm-svn: 331840
2018-05-09 02:07:53 +00:00
Sean Fertile d2e887d2f6 [PPC64] Emit plt call stubs to the text section rather then the plt section.
On PowerPC calls to functions through the plt must be done through a call stub
that is responsible for:
1) Saving the toc pointer to the stack.
2) Loading the target functions address from the plt into both r12 and the
   count register.
3) Indirectly branching to the target function.

Previously we have been emitting these call stubs to the .plt section, however
the .plt section should be reserved for the lazy symbol resolution stubs. This
patch moves the call stubs to the text section by moving the implementation from
writePlt to the thunk framework.

Differential Revision: https://reviews.llvm.org/D46204

llvm-svn: 331607
2018-05-06 19:13:29 +00:00
Zaara Syeda edc7a8c1e5 [PPC64] Remove support for ELF V1 ABI in LLD - buildbot fix
Fix buildbot error, failure to build with msvc due to error C2446
Use switch instead of ternary operator.

Differential Revision: https://reviews.llvm.org/D46316

llvm-svn: 331534
2018-05-04 16:04:04 +00:00
Zaara Syeda f61b0733a8 [PPC64] Remove support for ELF V1 ABI in LLD
The current support for V1 ABI in LLD is incomplete.
This patch removes V1 ABI support and changes the default behavior to V2 ABI,
issuing an error when using the V1 ABI. It also updates the testcases to V2
and removes any V1 specific tests.

Differential Revision: https://reviews.llvm.org/D46316

llvm-svn: 331529
2018-05-04 15:09:49 +00:00
Rafael Espindola a59aacf52b Fix trap instruction on pp64.
The test was passing on a big endian host, but just because od with x4
was compensating for it.

llvm-svn: 330386
2018-04-20 01:21:24 +00:00
Rafael Espindola 3e7d6fc2c6 Define TrapInst for ppc64.
This is nice for testing since it is the first TrapInst whose bytes
are not all the same.

llvm-svn: 329014
2018-04-02 21:11:13 +00:00
Sean Fertile 227d4399bf [PPC64] Minor changes for Plt relocations.
The Plt relative relocations are R_PPC64_JMP_SLOT in the V2 abi, and we only
reserve 2 double words instead of 3 at the start of the array of PLT entries for
lazy linking.

Differential Revision: https://reviews.llvm.org/D44951

llvm-svn: 329006
2018-04-02 19:47:21 +00:00
Sean Fertile af95629deb [PPC64] Write plt stubs for ElfV2 abi
Add the default version of a plt stub for the V2 Elf abi.

Differential Revision: https://reviews.llvm.org/D44850

llvm-svn: 329004
2018-04-02 19:17:12 +00:00
Rui Ueyama f001ead490 Do not use template for check{Int,UInt,IntUInt,Alignment}.
Template is just unnecessary.

Differential Revision: https://reviews.llvm.org/D45063

llvm-svn: 328843
2018-03-29 22:40:52 +00:00
Zaara Syeda 5dd6bd9631 [ELF][PPC64] Fix getRelExpr for R_PPC64_REL16_LO and R_PPC64_REL16_HA
The relocations R_PPC64_REL16_LO and R_PPC64_REL16_HA should return R_PC
for getRelExpr since they compute #lo(S + A – P) and #ha(S + A – P).

Differential Revision: https://reviews.llvm.org/D44648

llvm-svn: 328103
2018-03-21 15:04:04 +00:00
Zaara Syeda 52ed6eb8d9 [ELF] Add basic support for PPC LE
This patch adds changes to start supporting the Power 64-Bit ELF V2 ABI.
This includes:
- Changing the ElfSym::GlobalOffsetTable to be named .TOC.
- Creating a GotHeader so the first entry in the .got is .TOC.
- Setting the e_flags to be 1 for ELF V1 and 2 for ELF V2

Differential Revision: https://reviews.llvm.org/D44483

llvm-svn: 327871
2018-03-19 17:40:14 +00:00
Fangrui Song 0c483024e4 [ELF] Convert {read,write}*be to endianness-aware read/write.
Subscribers: emaste, nemanjai, arichardson, kbarton, llvm-commits

Differential Revision: https://reviews.llvm.org/D44227

llvm-svn: 327156
2018-03-09 18:03:22 +00:00
Rui Ueyama f52496e1e0 Rename SymbolBody -> Symbol
Now that we have only SymbolBody as the symbol class. So, "SymbolBody"
is a bit strange name now. This is a mechanical change generated by

  perl -i -pe s/SymbolBody/Symbol/g $(git grep -l SymbolBody lld/ELF lld/COFF)

nd clang-format-diff.

Differential Revision: https://reviews.llvm.org/D39459

llvm-svn: 317370
2017-11-03 21:21:47 +00:00
Bob Haarman b8a59c8aa5 [lld] unified COFF and ELF error handling on new Common/ErrorHandler
Summary:
The COFF linker and the ELF linker have long had similar but separate
Error.h and Error.cpp files to implement error handling. This change
introduces new error handling code in Common/ErrorHandler.h, changes the
COFF and ELF linkers to use it, and removes the old, separate
implementations.

Reviewers: ruiu

Reviewed By: ruiu

Subscribers: smeenai, jyknight, emaste, sdardis, nemanjai, nhaehnle, mgorny, javed.absar, kbarton, fedor.sergeev, llvm-commits

Differential Revision: https://reviews.llvm.org/D39259

llvm-svn: 316624
2017-10-25 22:28:38 +00:00
Rui Ueyama be85529d2b Remove one parameter from Target::getRelExpr.
A section was passed to getRelExpr just to create an error message.
But if there's an invalid relocation, we would eventually report it
in relocateOne. So we don't have to pass a section to getRelExpr.

llvm-svn: 315552
2017-10-12 03:14:06 +00:00
Rui Ueyama 67533a2cb3 Define RelType to represent relocation types.
We were using uint32_t as the type of relocation kind. It has a
readability issue because what Type really means in `uint32_t Type`
is not obvious. It could be a section type, a symbol type or a
relocation type.

Since we do not do any arithemetic operations on relocation types
(e.g. adding one to R_X86_64_PC32 doesn't make sense), it would be
more natural if they are represented as enums. Unfortunately, that
is not doable because relocation type definitions are spread into
multiple header files.

So I decided to use typedef. This still should be better than the
plain uint32_t because the intended type is now obvious.

llvm-svn: 315525
2017-10-11 22:49:24 +00:00
Rafael Espindola 3bab91332f Fix which file is in an error message.
When reporting an invalid relocation we were blaming the destination
file instead of the file with the relocation.

llvm-svn: 310084
2017-08-04 18:33:16 +00:00
Rui Ueyama e145bc22fd Do not use make<> to allocate TargetInfo. NFC.
llvm-svn: 305577
2017-06-16 20:15:03 +00:00
Rui Ueyama 21c0a9ceeb Split Target.cpp into small files.
Target.cpp contains code for all the targets that LLD supports. It was
simple and easy, but as the number of supported targets increased,
it got messy.

This patch splits the file into per-target files under ELF/arch directory.

Differential Revision: https://reviews.llvm.org/D34222

llvm-svn: 305565
2017-06-16 17:32:43 +00:00