maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
278,422 Commits 23 Branches 0 Tags 2.2 GiB
Commit Graph

6 Commits

Author SHA1 Message Date
Krzysztof Parzyszek 557729761c [Hexagon] Switch to parameterized register classes for HVX 
This removes the duplicate HVX instruction set for the 128-byte mode.
Single instruction set now works for both modes (64- and 128-byte).

llvm-svn: 313362
 2017-09-15 15:46:05 +00:00
Krzysztof Parzyszek a72fad980c [Hexagon] Replace instruction definitions with auto-generated ones 
llvm-svn: 294753
 2017-02-10 15:33:13 +00:00
Krzysztof Parzyszek a540997ce4 [Hexagon] Separate Hexagon subreg indices for different register classes 
For pairs of 32-bit registers: isub_lo, isub_hi.
For pairs of vector registers: vsub_lo, vsub_hi.

Add generic subreg indices: ps_sub_lo, ps_sub_hi, and a function
  HexagonRegisterInfo::getHexagonSubRegIndex(RegClass, GenericSubreg)
that returns the appropriate subreg index for RegClass.

llvm-svn: 286377
 2016-11-09 16:19:08 +00:00
Krzysztof Parzyszek eabc0d0fd5 [Hexagon] Clean up some miscellaneous V60 intrinsics a bit 
llvm-svn: 278823
 2016-08-16 17:14:44 +00:00
Krzysztof Parzyszek 040bb35d9d [Hexagon] Use common Pat classes for selecting code for intrinsics 
llvm-svn: 267178
 2016-04-22 18:05:55 +00:00
Krzysztof Parzyszek 4eb6d4d1f2 [Hexagon] Hexagon V60 HVX intrinsic defintions 
Author: Ron Lieberman <ronl@codeaurora.org>
llvm-svn: 254165
 2015-11-26 16:54:33 +00:00