705d841bb6
R600: Don't compare iterators of different maps.
...
Found be libstdc's debug mode.
llvm-svn: 183549
2013-06-07 19:59:34 +00:00
ebe0be9ca4
Vincent says the element is at most once in the vector, so we don't need a full std::remove.
...
llvm-svn: 183541
2013-06-07 18:18:12 +00:00
a857fe115b
R600: Fix a potential iterator invalidation issue.
...
As a bonus this reduces the loop from O(n^2) to O(n).
llvm-svn: 183532
2013-06-07 16:13:49 +00:00
931bb768fd
R600: Remove an extra break in R600OptimizeVectorRegisters.cpp
...
llvm-svn: 183528
2013-06-07 15:44:53 +00:00
0030362ed9
R600: Rewrite an awkward loop in R600MachineScheduler
...
llvm-svn: 183458
2013-06-06 23:08:32 +00:00
54476a1503
R600: Remove leftover code in R600MachineScheduler.cpp
...
Spotted by Benjamin Kramer.
llvm-svn: 183413
2013-06-06 14:18:29 +00:00
b91216817f
Cast to the correct type. Pointer, not reference.
...
llvm-svn: 183385
2013-06-06 05:39:29 +00:00
4a8f079371
R600OptimizeVectorRegisters.cpp: Tweak a warning. [-Wsometimes-uninitialized]
...
FIXME: Is it false alarm?
llvm-svn: 183371
2013-06-06 02:15:12 +00:00
e5555fc238
R600OptimizeVectorRegisters.cpp: Suppress a warning. [-Wunused-variable]
...
llvm-svn: 183370
2013-06-06 02:15:06 +00:00
372574d447
Trailing linefeed.
...
llvm-svn: 183369
2013-06-06 02:15:00 +00:00
e410576865
Cast to the proper type.
...
llvm-svn: 183365
2013-06-06 01:04:21 +00:00
acec99c948
R600: Replace predicate loop with predicate function
...
llvm-svn: 183351
2013-06-05 23:39:50 +00:00
dec1875207
R600: Add a pass that merge Vector Register
...
Previously commited @183279 but tests were failing, reverted @183286
It was broken because @183336 was missing, now it's there.
llvm-svn: 183343
2013-06-05 21:38:04 +00:00
4b5b849753
R600: Schedule copy from phys register at beginning of block
...
It allows regalloc pass to remove them by trivially assigning associated reg
llvm-svn: 183336
2013-06-05 20:27:35 +00:00
aad5376fb6
R600: Make sure to schedule AR register uses and defs in the same clause
...
Reviewed-by: vljn at ovi.com
llvm-svn: 183294
2013-06-05 03:43:06 +00:00
beef23fe21
Revert "R600: Add a pass that merge Vector Register"
...
This reverts commit r183279. CodeGen/R600/texture-input-merge.ll was failing.
llvm-svn: 183286
2013-06-05 01:48:30 +00:00
a45aafabfe
R600: Add a pass that merge Vector Register
...
llvm-svn: 183279
2013-06-04 23:17:26 +00:00
c689679173
R600: Const/Neg/Abs can be folded to dot4
...
llvm-svn: 183278
2013-06-04 23:17:15 +00:00
276ceb8d5f
R600: Swizzle texture/export instructions
...
llvm-svn: 183229
2013-06-04 15:04:53 +00:00
19978553d4
Silencing an MSVC warning about mixing bool and unsigned int.
...
llvm-svn: 183176
2013-06-04 01:03:03 +00:00
94593ee8c3
R600/SI: Add support for work item and work group intrinsics
...
llvm-svn: 183138
2013-06-03 17:40:18 +00:00
ed882c2f1b
R600/SI: Add a calling convention for compute shaders
...
llvm-svn: 183137
2013-06-03 17:40:11 +00:00
046039e81b
R600/SI: Custom lower i64 sign_extend
...
llvm-svn: 183136
2013-06-03 17:40:03 +00:00
0518ff89ba
R600/SI: Adjust some instructions' out register class after ISel
...
This is necessary to avoid generating VGPR to SGPR copies in some
cases.
llvm-svn: 183135
2013-06-03 17:39:58 +00:00
bad1f59212
R600/SI: Handle REG_SEQUENCE in fitsRegClass()
...
llvm-svn: 183134
2013-06-03 17:39:54 +00:00
b5a97004fb
R600/SI: Handle nodes with glue results correctly SITargetLowering::foldOperands()
...
llvm-svn: 183133
2013-06-03 17:39:50 +00:00
2183b70523
R600/SI: Fixup CopyToReg register class in PostprocessISelDAG()
...
The CopyToReg nodes will sometimes try to copy a value from a VGPR to an
SGPR. This kind of copy is not possible, so we need to detect
VGPR->SGPR copies and do something else. The current strategy is to
replace these copies with VGPR->VGPR copies and hope that all the users
of CopyToReg can accept VGPRs as arguments.
llvm-svn: 183132
2013-06-03 17:39:46 +00:00
07a10a3d3f
R600/SI: Add support for global loads
...
llvm-svn: 183131
2013-06-03 17:39:43 +00:00
556d9aa841
R600/SI: Rework MUBUF store instructions
...
The lowering of stores is now mostly handled in the tablegen files. No
more BUFFER_STORE nodes I generated during legalization.
llvm-svn: 183130
2013-06-03 17:39:37 +00:00
91a942b93e
R600: 3 op instructions have no write bit but the result are store in PV
...
llvm-svn: 183111
2013-06-03 15:56:12 +00:00
eabf83e0a2
R600: CALL_FS consumes a stack size entry
...
llvm-svn: 183108
2013-06-03 15:44:42 +00:00
f83df1f1cb
R600: use capital letter for PV channel
...
llvm-svn: 183107
2013-06-03 15:44:35 +00:00
a09873dda7
R600: Constraints input regs of interp_xy,_zw
...
llvm-svn: 183106
2013-06-03 15:44:16 +00:00
b1a4d9da3b
Make SubRegIndex size mandatory, following r183020.
...
This also makes TableGen able to compute sizes/offsets of synthesized
indices representing tuples.
llvm-svn: 183061
2013-05-31 23:45:26 +00:00
ae8faf2e9a
Temporary fix to get rid of gcc warning.
...
llvm-svn: 182832
2013-05-29 07:32:08 +00:00
ef9de2a739
Track IR ordering of SelectionDAG nodes 2/4.
...
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.
llvm-svn: 182703
2013-05-25 02:42:55 +00:00
1b086cbcb8
R600: Fix R600ControlFlowFinalizer not considering VTX_READ 128 bit dst reg
...
Patch by: Vincent Lejeune
https://bugs.freedesktop.org/show_bug.cgi?id=64877
NOTE: This is a candidate for the 3.3 branch.
llvm-svn: 182600
2013-05-23 18:26:42 +00:00
d78bb468bd
Move passes from namespace llvm into anonymous namespaces. Sort includes while there.
...
llvm-svn: 182594
2013-05-23 17:10:37 +00:00
635e368e33
R600: Hide symbols of implementation details.
...
Also removes an unused function.
llvm-svn: 182587
2013-05-23 15:43:05 +00:00
15f193a1a3
Setting the default value (fixes CRT assertions about uninitialized variable use when doing debug MSVC builds), and fixing coding style.
...
llvm-svn: 182585
2013-05-23 14:55:00 +00:00
00345fa97b
Fix 32 bit build in c++11 mode.
...
The error was:
error: non-constant-expression cannot be narrowed from type 'long long' to 'long' in initializer list [-Wc++11-narrowing]
MI.getOperand(6).getImm() & 0x1F,
llvm-svn: 182584
2013-05-23 13:22:30 +00:00
39aca620db
Fix a leak on the r600 backend.
...
This should bring the valgrind bot back to life.
llvm-svn: 182561
2013-05-23 03:31:47 +00:00
bd6847fbea
clang-format this file.
...
llvm-svn: 182560
2013-05-23 03:28:39 +00:00
e3d83fb8c3
Fix use after free (pr16103).
...
llvm-svn: 182482
2013-05-22 15:31:11 +00:00
ebd8e38849
Check that a function starts with llvm. before using GET_FUNCTION_RECOGNIZER.
...
Fixes a use of uninitialized memory found by asan and valgind.
llvm-svn: 182480
2013-05-22 14:57:42 +00:00
4f328e1c2f
R600ISelLowering.cpp: Avoid "using namespace Intrinsic;" to appease MSC. Specify namespaces explicitly here.
...
MSC is confused about "memcpy" between <cstring> and llvm::Intrinsic::memcpy, when llvm::Intrinsic were exposed.
llvm-svn: 182452
2013-05-22 06:37:31 +00:00
18ca09c1cc
R600: Whitespace and untabify.
...
llvm-svn: 182451
2013-05-22 06:37:25 +00:00
616852848a
Create an FPOW SDNode opcode def in the target independent .td file rather than in a specific backend.
...
llvm-svn: 182450
2013-05-22 06:36:09 +00:00
21ea01d132
Attempt to fix the mingw32 bot.
...
This should hopefully fix
http://lab.llvm.org:8011/builders/clang-x86_64-darwin11-self-mingw32
llvm-svn: 182446
2013-05-22 02:30:47 +00:00
525cf28652
s/u_int32_t/uint32_t/
...
llvm-svn: 182444
2013-05-22 01:36:19 +00:00
f568827654
Fix warning in non-assert build.
...
llvm-svn: 182443
2013-05-22 01:29:38 +00:00
927ca942ce
R600: Fix bug detected by GCC warning.
...
R600TextureIntrinsicsReplacer.cpp:232: warning: the address of ‘ArgsType’ will always evaluate as ‘true’
This doesn't have any effect on the output as a vararg intrinsic behaves the
same way as a non-vararg one.
llvm-svn: 182293
2013-05-20 15:58:43 +00:00
f1ee716446
R600/SI: Use a multiclass for MUBUF_Load_Helper
...
This will simplify the instructions and also the pattern definitions.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182288
2013-05-20 15:02:31 +00:00
b8458f88d6
R600/SI: Add a pattern for S_LOAD_DWORDX2_* instructions
...
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182287
2013-05-20 15:02:28 +00:00
d2eebf001e
R600/SI: Add pattern for rotr
...
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182286
2013-05-20 15:02:24 +00:00
5643c4ac72
R600: Swap the legality of rotl and rotr
...
The hardware supports rotr and not rotl.
llvm-svn: 182285
2013-05-20 15:02:19 +00:00
1cfd7a50bb
R600/SI: Add patterns for 64-bit shift operations
...
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182284
2013-05-20 15:02:12 +00:00
459a79a81c
R600/SI: Use the same names for VOP3 operands and encoding fields
...
This makes it possible to reorder the operands without breaking the
encoding.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182283
2013-05-20 15:02:08 +00:00
b35efba4d9
R600/SI: Make fitsRegClass() operands const
...
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182282
2013-05-20 15:02:01 +00:00
75865923c9
Add LLVMContext argument to getSetCCResultType
...
llvm-svn: 182180
2013-05-18 00:21:46 +00:00
5986ce0e5d
Fix the build in c++11 mode.
...
The errors were:
non-constant-expression cannot be narrowed from type 'int64_t' (aka 'long') to 'uint32_t' (aka 'unsigned int') in initializer list
and
non-constant-expression cannot be narrowed from type 'long' to 'uint32_t' (aka 'unsigned int') in initializer list
llvm-svn: 182168
2013-05-17 22:45:52 +00:00
d3fcb5016c
R600: Lower int_load_input to copyFromReg instead of Register node
...
It solves a bug uncovered by dot4 patch where the register class of
int_load_input use was ignored.
llvm-svn: 182130
2013-05-17 16:51:06 +00:00
3d5118ca40
R600: Use bottom up scheduling algorithm
...
llvm-svn: 182129
2013-05-17 16:50:56 +00:00
4c81d4da6f
R600: Use depth first scheduling algorithm
...
It should increase PV substitution opportunities and lower gpr
usage (pending computations path are "flushed" sooner)
llvm-svn: 182128
2013-05-17 16:50:44 +00:00
e958c8e0d8
R600: Replace big texture opcode switch in scheduler by usesTC/usesVC
...
llvm-svn: 182127
2013-05-17 16:50:37 +00:00
519f21eed3
R600: Relax some vector constraints on Dot4.
...
Dot4 now uses 8 scalar operands instead of 2 vectors one which allows register
coalescer to remove some unneeded COPY.
This patch also defines some structures/functions that can be used to handle
every vector instructions (CUBE, Cayman special instructions...) in a similar
fashion.
llvm-svn: 182126
2013-05-17 16:50:32 +00:00
d3eed66e8c
R600: Improve texture handling
...
llvm-svn: 182125
2013-05-17 16:50:20 +00:00
4ebef18ab5
R600: Rename 128 bit registers.
...
Almost all instructions that takes a 128 bits reg as input (fetch, export...)
have the abilities to swizzle their argument and output. Instead of printing
default swizzle for each 128 bits reg, rename T*.XYZW to T* and let instructions
print potentially optimized swizzles themselves.
llvm-svn: 182124
2013-05-17 16:50:09 +00:00
0fca91d52e
R600: Some factorization
...
llvm-svn: 182123
2013-05-17 16:50:02 +00:00
f9f4e1e7db
R600: Factorize Fetch size limit inside AMDGPUSubTarget
...
llvm-svn: 182122
2013-05-17 16:49:55 +00:00
709e01688d
R600: prettier dump of clamp
...
llvm-svn: 182121
2013-05-17 16:49:49 +00:00
ecc2ad1cd4
R600: Fix encoding for R600 family GPUs
...
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
https://bugs.freedesktop.org/show_bug.cgi?id=64193
https://bugs.freedesktop.org/show_bug.cgi?id=64257
https://bugs.freedesktop.org/show_bug.cgi?id=64320
NOTE: This is a candidate for the 3.3 branch.
llvm-svn: 182113
2013-05-17 15:23:21 +00:00
edade94bbc
R600: Pass MCSubtargetInfo reference to R600CodeEmitter
...
llvm-svn: 182112
2013-05-17 15:23:12 +00:00
b7be72df5b
R600/SI: return undef instead of null for skipped arguments
...
This is a candidate for the stable branch.
Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=64694
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182084
2013-05-17 09:46:48 +00:00
1e21b53020
R600/SI: Add processor type for Hainan asic
...
Patch by: Alex Deucher
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
NOTE: This is a candidate for the 3.3 branch.
llvm-svn: 181792
2013-05-14 14:42:56 +00:00
b84cde5219
Remove unused fields and arguments.
...
llvm-svn: 181706
2013-05-13 14:34:48 +00:00
227144c23c
Remove the MachineMove class.
...
It was just a less powerful and more confusing version of
MCCFIInstruction. A side effect is that, since MCCFIInstruction uses
dwarf register numbers, calls to getDwarfRegNum are pushed out, which
should allow further simplifications.
I left the MachineModuleInfo::addFrameMove interface unchanged since
this patch was already fairly big.
llvm-svn: 181680
2013-05-13 01:16:13 +00:00
86067ad6a9
Fix the R600 build.
...
llvm-svn: 181621
2013-05-10 18:31:42 +00:00
2b971eb0d0
R600: Remove AMDILPeeopholeOptimizer and replace optimizations with tablegen patterns
...
The BFE optimization was the only one we were actually using, and it was
emitting an intrinsic that we don't support.
https://bugs.freedesktop.org/show_bug.cgi?id=64201
Reviewed-by: Christian König <christian.koenig@amd.com>
NOTE: This is a candidate for the 3.3 branch.
llvm-svn: 181580
2013-05-10 02:09:45 +00:00
3a7c34c778
R600: Expand SUB for v2i32/v4i32
...
Patch by: Aaron Watry
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>
NOTE: This is a candidate for the 3.3 branch.
llvm-svn: 181579
2013-05-10 02:09:39 +00:00
3deddc5079
R600: Expand MUL for v4i32/v2i32
...
Fixes piglit test for OpenCL builtin mul24, and allows mad24 to run.
Patch by: Aaron Watry
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>
NOTE: This is a candidate for the 3.3 branch.
llvm-svn: 181578
2013-05-10 02:09:34 +00:00
7fb3963498
R600: Expand SRA for v4i32/v2i32
...
v2: Add v4i32 test
Patch by: Aaron Watry
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>
NOTE: This is a candidate for the 3.3 branch.
llvm-svn: 181577
2013-05-10 02:09:29 +00:00
a99c6ae47a
R600: Expand vselect for v4i32 and v2i32
...
v2: Add vselect v4i32 test
Patch by: Aaron Watry
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>
NOTE: This is a candidate for the 3.3 branch.
llvm-svn: 181576
2013-05-10 02:09:24 +00:00
f787ef1d96
R600/SI: Add intrinsic for MIMG IMAGE_GET_RESINFO opcode
...
Patch by: Michel Dänzer
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 181269
2013-05-06 23:02:19 +00:00
e363dbf7eb
R600/SI: Handle arbitrary destination type in SITargetLowering::adjustWritemask
...
Patch by: Michel Dänzer
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 181268
2013-05-06 23:02:15 +00:00
353b336e8c
R600/SI: Add intrinsic for texture image loading
...
Patch by: Michel Dänzer
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 181267
2013-05-06 23:02:12 +00:00
c932d7329c
R600/SI: Add pattern for uint_to_fp
...
Patch by: Michel Dänzer
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 181266
2013-05-06 23:02:07 +00:00
cf6452c7d4
R600/SI: Add patterns for integer maxima / minima
...
Patch by: Michel Dänzer
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 181265
2013-05-06 23:02:04 +00:00
9b3d2535bf
R600/SI: Add pattern for AMDGPU.trunc intrinsic
...
Patch by: Michel Dänzer
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 181263
2013-05-06 23:02:00 +00:00
d93cede8e4
R600: Remove dead code from the CodeEmitter v2
...
v2:
- Replace switch statement with TSFlags query
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>
llvm-svn: 181229
2013-05-06 17:50:57 +00:00
043de4c5af
R600: Emit config values in register / value pairs
...
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>
llvm-svn: 181228
2013-05-06 17:50:51 +00:00
cfe2ef8fea
R600: Stop emitting the instruction type byte before each instruction
...
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>
llvm-svn: 181225
2013-05-06 17:50:44 +00:00
dbbcaf31b6
R600: Emit ISA for CALL_FS_* instructions
...
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>
llvm-svn: 181223
2013-05-06 17:50:26 +00:00
4489b85f2b
R600: Expand vector or, shl, srl, and xor nodes
...
llvm-svn: 181035
2013-05-03 17:21:31 +00:00
6a6ecedcb7
R600: BFI_INT is a vector-only instruction
...
llvm-svn: 181034
2013-05-03 17:21:24 +00:00
eac65dde30
R600: Add pattern for SHA-256 Ma function
...
This can be optimized using the BFI_INT instruction.
llvm-svn: 181033
2013-05-03 17:21:20 +00:00
c2516c6e40
R600: Clean up comments in Processors.td
...
llvm-svn: 181032
2013-05-03 17:21:14 +00:00
ddd43383ef
R600: Signed literals are 64bits wide
...
llvm-svn: 180960
2013-05-02 21:53:03 +00:00
2a44ae0053
R600: If previous bundle is dot4, PV valid chan is always X
...
llvm-svn: 180959
2013-05-02 21:52:55 +00:00
b0422e24a9
R600: Improve asmPrint of ALU clause
...
llvm-svn: 180957
2013-05-02 21:52:40 +00:00
Benjamin Kramer