b68eeb3852
Nuke no longer accurate comment.
...
llvm-svn: 144411
2011-11-11 22:30:06 +00:00
28c1d18434
Preserve MachineMemOperands in ARMLoadStoreOptimizer.
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Fixes PR8113.
llvm-svn: 144409
2011-11-11 22:18:09 +00:00
85a2343b01
ARM allow Q registers in vldm/vstm register lists.
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rdar://9672822
llvm-svn: 144407
2011-11-11 21:27:40 +00:00
089cc53232
allow non-device function calls in PTX when natively handling device-side printf
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llvm-svn: 144388
2011-11-11 14:45:12 +00:00
80cd65bfa9
add rules in tabgen for PTX COPY_ADDRESS of frameindex
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llvm-svn: 144387
2011-11-11 14:45:06 +00:00
48b5bbffed
Remove the unnecessary dependency on libARMCodeGen from libARMDisassembler.
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llvm-svn: 144384
2011-11-11 12:39:41 +00:00
1cc805c058
Remove the unnecessary dependency on libMBlazeCodeGen from libMBlazeDisassembler.
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llvm-svn: 144383
2011-11-11 12:39:35 +00:00
ea28a34c43
Add lowering for AVX2 shift instructions.
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llvm-svn: 144380
2011-11-11 07:39:23 +00:00
e19b0a9eb8
Rename variables to avoid confusion. No functionallity change intended.
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llvm-svn: 144377
2011-11-11 06:27:41 +00:00
7ddd63ce4e
Add support for using immediates with select instructions.
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rdar://10412592
llvm-svn: 144376
2011-11-11 06:20:39 +00:00
4a63d1c0f0
Do not try to detect DAG combine patterns for integer multiply-add/sub if value
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type is not i32. MIPS does not have 64-bit integer multiply-add/sub
instructions.
llvm-svn: 144373
2011-11-11 04:18:21 +00:00
21cbc25bbb
64-bit atomic instructions.
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llvm-svn: 144372
2011-11-11 04:14:30 +00:00
9189d7127f
Modify LowerFRAMEADDR. Use 64-bit register FP_64 when ABI is N64.
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llvm-svn: 144371
2011-11-11 04:11:56 +00:00
4bdfec57ba
Add 64-bit versions of LEA_ADDiu and DynAlloc. Modify LowerDYNAMIC_STACKALLOC.
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llvm-svn: 144370
2011-11-11 04:06:38 +00:00
0009dc2088
64-bit versions of jal, jalr and bal.
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llvm-svn: 144368
2011-11-11 04:03:54 +00:00
11521863da
Emit Mips64's sequence of instructions that set global register in prologue.
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llvm-svn: 144367
2011-11-11 04:00:29 +00:00
aa1f4c7986
Fix printing of MCSymbolRegExpr. Needs three closing parentheses for
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VK_Mips_GPOFF_HI/LO.
llvm-svn: 144366
2011-11-11 03:58:36 +00:00
c4a001478c
Make sure to expand SIGN_EXTEND_INREG for NEON vectors. PR11319, round 3.
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llvm-svn: 144361
2011-11-11 03:16:38 +00:00
023ede5649
When loading a value, treat an i1 as an i8.
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llvm-svn: 144356
2011-11-11 02:38:59 +00:00
8df8204554
If we have to reset the calculation of the compact encoding, then also reset the
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"saved register" index.
<rdar://problem/10430076>
llvm-svn: 144350
2011-11-11 00:59:14 +00:00
2a3503e061
Add support for using MVN to materialize negative constants.
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rdar://10412592
llvm-svn: 144348
2011-11-11 00:36:21 +00:00
6d617b48c7
LLVMBuild: Add explicit information on whether targets define an assembly printer, assembly parser, or disassembler.
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llvm-svn: 144344
2011-11-11 00:23:56 +00:00
d9a9be269c
Thumb2 ldm/stm updating w/ one register in the list are LDR/STR.
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rdar://10429490
llvm-svn: 144338
2011-11-10 23:58:34 +00:00
afad053141
ARM let processInstruction() tranforms chain.
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llvm-svn: 144337
2011-11-10 23:42:14 +00:00
9bded9dc24
Thumb2 parsing for push/pop w/ hi registers in the reglist.
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rdar://10130228.
llvm-svn: 144331
2011-11-10 23:17:11 +00:00
a113eb0205
Thumb1 diagnostics for reglist on PUSH/POP fix.
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Was not checking the first register in the register list.
llvm-svn: 144329
2011-11-10 23:01:27 +00:00
5a5ce63742
Thumb MUL assembly parsing for 3-operand form.
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Get the source register that isn't tied to the destination register correct,
even when the assembly source operand order is backwards.
rdar://10428630
llvm-svn: 144322
2011-11-10 22:10:12 +00:00
085f6f2af1
build/MBlazeDisassembler: Some compilers may generate an MBlaze disassembler
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that depends on MBlazeCodeGen. This is a layering violation that should really
be fixed.
llvm-svn: 144321
2011-11-10 22:00:37 +00:00
d1762e00e2
When in ARM mode, LDRH/STRH require special handling of negative offsets.
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For correctness, disable this for now.
rdar://10418009
llvm-svn: 144316
2011-11-10 21:09:49 +00:00
42ba6286b6
ARM .thumb_func directive for quoted symbol names.
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Use the getIdentifier() method of the token, not getString(), otherwise
we keep the quotes as part of the symbol name, which we don't want.
rdar://10428015
llvm-svn: 144315
2011-11-10 20:48:53 +00:00
c14871cc67
ARM assembly parsing for LSR/LSL/ROR(immediate).
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More of rdar://9704684
llvm-svn: 144301
2011-11-10 19:18:01 +00:00
61db5a59f7
ARM assembly parsing for ASR(immediate).
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Start of rdar://9704684
llvm-svn: 144293
2011-11-10 16:44:55 +00:00
b538095011
build: Rename CBackend and CppBackend libraries to have CodeGen suffix, for
...
consistency with other targets.
llvm-svn: 144292
2011-11-10 15:35:14 +00:00
0a2f797dec
AVX2: Add variable shift from memory.
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Note: These patterns only works in some cases because
many times the load sd node is bitcasted from a load
node of a different type.
llvm-svn: 144266
2011-11-10 06:54:20 +00:00
3fbd094ad9
For immediate encodings of icmp, zero or sign extend first. Then
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determine if the value is negative and flip the sign accordingly.
rdar://10422026
llvm-svn: 144258
2011-11-10 01:30:39 +00:00
807c6e4e5f
build/Make & CMake: Pass the appropriate --native-target and --enable-targets
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options to llvm-build, so the all-targets etc. components are defined properly.
llvm-svn: 144255
2011-11-10 01:16:48 +00:00
233c9304a8
llvm-build: Add --native-target and --enable-targets options, and add logic to
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handle defining the "magic" target related components (like native,
nativecodegen, and engine).
- We still require these components to be in the project (currently in
lib/Target) so that we have a place to document them and hopefully make it
more obvious that they are "magic".
llvm-svn: 144253
2011-11-10 00:50:07 +00:00
1c04e14447
llvm-build: Change CBackend and CppBackend to not use library_name. This will
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change the generated library .a file name once we fully switch over, but
simplifies how we treat these targets without requiring more special casing
(since their library group name and the codegen library name currently map to
the same "llvm-config" style component name).
llvm-svn: 144251
2011-11-10 00:49:55 +00:00
82219ad4dc
llvm-build: Add an explicit component type to represent targets.
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- Gives us a place to hang target specific metadata (like whether the target has a JIT).
llvm-svn: 144250
2011-11-10 00:49:51 +00:00
a48485a37f
Tidy up.
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llvm-svn: 144244
2011-11-10 00:02:33 +00:00
25bc090170
Thumb2 assembly parsing STMDB w/ optional .w suffix.
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rdar://10422955
llvm-svn: 144242
2011-11-09 23:44:23 +00:00
2d4055b683
Make sure we correctly unroll conversions between v2f64 and v2i32 on ARM.
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llvm-svn: 144241
2011-11-09 23:36:02 +00:00
2f27fab6ed
The ARM LDRH/STRH instructions use a +/-imm8 encoding, not an imm12.
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rdar://10418009
llvm-svn: 144213
2011-11-09 21:30:12 +00:00
1938482bfa
AVX2: Add patterns for variable shift operations
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llvm-svn: 144212
2011-11-09 21:22:13 +00:00
2f70bcdb94
Remove unnecessary include.
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llvm-svn: 144211
2011-11-09 21:11:02 +00:00
79135d844d
Add AVX2 support for vselect of v32i8
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llvm-svn: 144187
2011-11-09 13:21:28 +00:00
f87a2bef51
Enable execution dependency fix pass for YMM registers when AVX2 is enabled. Add AVX2 logical operations to list of replaceable instructions.
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llvm-svn: 144179
2011-11-09 09:37:21 +00:00
c9eb09d3b8
Add instruction selection for AVX2 integer comparisons.
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llvm-svn: 144176
2011-11-09 08:06:13 +00:00
8c8a431057
Add AVX2 instruction lowering for add, sub, and mul.
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llvm-svn: 144174
2011-11-09 07:28:55 +00:00
595d419427
Add support for encoding immediates in icmp and fcmp. Hopefully, this will
...
remove a fair number of unnecessary materialized constants.
rdar://10412592
llvm-svn: 144163
2011-11-09 03:22:02 +00:00
Jim Grosbach