10702d5f22
Hoist simpler checks above llvm::PointerMayBeCaptured. No functional change intended.
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llvm-svn: 156687
2012-05-12 00:43:40 +00:00
165473247f
Don't look for empty live ranges in the unions.
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Empty live ranges represent undef and still get allocated, but they
won't appear in LiveIntervalUnions.
Patch by Patrik Hägglund!
llvm-svn: 156685
2012-05-12 00:33:28 +00:00
d918f77ba3
Insert instructions to the entry basic block which initializes the global
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pointer register.
This is the first of the series of patches which clean up the way global pointer
register is used. The patches will make the following improvements:
- Make $gp an allocatable temporary register rather than reserving it.
- Use a virtual register as the global pointer register and let the register
allocator decide which register to assign to it or whether spill/reloads are
needed.
- Make sure $gp is valid at the entry of a called function, which is necessary
for functions using lazy binding.
- Remove the need for emitting .cprestore and .cpload directives.
llvm-svn: 156671
2012-05-12 00:17:17 +00:00
a39c9bceeb
Add doxygen comments.
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llvm-svn: 156665
2012-05-11 23:34:39 +00:00
0661b81bca
Do not replace operands of pseudo instructions with register $zero.
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llvm-svn: 156663
2012-05-11 23:22:18 +00:00
a33015d4e0
Revert 156658.
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llvm-svn: 156662
2012-05-11 23:21:01 +00:00
e40f5d3ee0
[fast-isel] Fast-isel doesn't use the expect intrinsic.
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llvm-svn: 156658
2012-05-11 23:10:58 +00:00
5d60c36f37
Use regular expression to match register names.
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llvm-svn: 156656
2012-05-11 23:00:40 +00:00
7d878db4e1
Make the URL a link instead.
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llvm-svn: 156655
2012-05-11 22:38:33 +00:00
93303819ac
[Support/StringRef] Add find_last_not_of and {r,l,}trim.
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llvm-svn: 156652
2012-05-11 22:08:50 +00:00
393f432ddf
Remove extraneous ; and the resulting warning.
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llvm-svn: 156649
2012-05-11 21:56:04 +00:00
9cc768581a
Add mention of Glasgow Haskell Compiler.
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llvm-svn: 156648
2012-05-11 21:42:37 +00:00
aa9cb9df59
[fast-isel] Add support for selecting @llvm.trap().
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llvm-svn: 156646
2012-05-11 21:33:49 +00:00
5edcf8822d
Updated instruction table due to addded intrinsics.
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llvm-svn: 156644
2012-05-11 21:10:16 +00:00
95d0117bb3
Remove warnings from HexagonVLIWPacketizer.
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llvm-svn: 156636
2012-05-11 20:00:34 +00:00
1367e49f6b
Some release notes for dragonegg.
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llvm-svn: 156635
2012-05-11 19:59:43 +00:00
31f8723ef3
Hexagon constant extender support.
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Patch by Jyotsna Verma.
llvm-svn: 156634
2012-05-11 19:56:59 +00:00
06e34d9220
Typo.
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llvm-svn: 156633
2012-05-11 19:43:29 +00:00
3268692aa8
[fast-isel] Remove -disable-arm-fast-isel option. -fast-isel=0 suffices. Minor cleanup.
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llvm-svn: 156632
2012-05-11 19:40:25 +00:00
83ccb6ce08
Hexagon V5 intrinsics support.
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llvm-svn: 156631
2012-05-11 19:39:13 +00:00
3f3eb18010
Defer computation of SuperRegs.
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Don't compute the SuperRegs list until the sub-register graph is
completely finished. This guarantees that the list of super-registers is
properly topologically ordered, and has no duplicates.
llvm-svn: 156629
2012-05-11 19:01:01 +00:00
90f9afe659
[fast-isel] Cleaner fix for when we're unable to handle a non-double multi-reg
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retval. Hoists check before emitting the call to avoid unnecessary work.
rdar://11430407
PR12796
llvm-svn: 156628
2012-05-11 18:51:55 +00:00
e2cfd3ce95
objectsize: add a few more tests and fix a bug
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llvm-svn: 156625
2012-05-11 18:25:29 +00:00
519b12f927
[fast-isel] Rather then assert (or segfault in a non-asserts build), fall back
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to selection DAG isel if we're unable to handle a non-double multi-reg retval.
rdar://11430407
PR12796
llvm-svn: 156622
2012-05-11 17:41:06 +00:00
466d3d8faa
The return type is an unsigned, not a bool.
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llvm-svn: 156621
2012-05-11 16:41:38 +00:00
0d5ec28ccc
Add space before an open parenthesis in control flow statements.
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llvm-svn: 156620
2012-05-11 15:36:46 +00:00
09de6ae399
Added X86 Atom latencies to X86InstrMMX.td.
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llvm-svn: 156615
2012-05-11 14:27:12 +00:00
05b46b3745
PR1255: ConstantRangesSet and CRSBuilder classes moved from include/llvm to include/llvm/Support.
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llvm-svn: 156613
2012-05-11 10:34:23 +00:00
addad7388d
Fix test/CodeGen/X86/tls-pie.ll.
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llvm-svn: 156612
2012-05-11 10:19:54 +00:00
f9d0e44b82
Implement initial-exec TLS model for 32-bit PIC x86
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This fixes a TODO from 2007 :) Previously, LLVM would emit the wrong
code here (see the update to test/CodeGen/X86/tls-pie.ll).
llvm-svn: 156611
2012-05-11 10:11:01 +00:00
ddc67a7655
Added the missing bit definition for the 4th bit of the STR (post reg) instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions.
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llvm-svn: 156609
2012-05-11 09:28:27 +00:00
5a719f9b9a
Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate offset addressing. The assembler and instruction printer were not properly handeling the #-0 immediate.
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llvm-svn: 156608
2012-05-11 09:10:54 +00:00
5f4b32f9d7
Fix a use after free when the streamer is destroyed. Fixes pr12622.
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llvm-svn: 156606
2012-05-11 03:42:13 +00:00
e37614438f
Fix a misleading comment.
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llvm-svn: 156603
2012-05-11 01:45:15 +00:00
dc1e36e9f5
Tidy up. Trailing whitespace.
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llvm-svn: 156602
2012-05-11 01:41:30 +00:00
3658412afc
Tidy up. Trailing whitespace.
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llvm-svn: 156601
2012-05-11 01:39:13 +00:00
e0a64d83fc
Fix a minor logic mistake transforming compares in instcombine. PR12514.
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llvm-svn: 156600
2012-05-11 01:32:59 +00:00
dc8ad0058f
ARM: peephole optimization to remove cmp instruction
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This patch will optimize the following cases:
sub r1, r3 | sub r1, imm
cmp r3, r1 or cmp r1, r3 | cmp r1, imm
bge L1
TO
subs r1, r3
bge L1 or ble L1
If the branch instruction can use flag from "sub", then we can replace
"sub" with "subs" and eliminate the "cmp" instruction.
rdar: 10734411
llvm-svn: 156599
2012-05-11 01:30:47 +00:00
dfab443ae8
Define a new intrinsic, @llvm.debugger. It will be similar to __builtin_trap(),
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but it generates int3 on x86 instead of ud2.
llvm-svn: 156593
2012-05-11 00:19:32 +00:00
b6148ed72c
Allow unique_file to take a mode for file permissions, but default
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to user only read/write.
Part of rdar://11325849
llvm-svn: 156591
2012-05-11 00:07:44 +00:00
8244b1dc7e
Fix intendation.
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llvm-svn: 156589
2012-05-10 23:38:07 +00:00
c08df9e5fd
Compute secondary sub-registers.
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The sub-registers explicitly listed in SubRegs in the .td files form a
tree. In a complicated register bank, it is possible to have
sub-register relationships across sub-trees. For example, the ARM NEON
double vector Q0_Q1 is a tree:
Q0_Q1 = [Q0, Q1], Q0 = [D0, D1], Q1 = [D2, D3]
But we also define the DPair register D1_D2 = [D1, D2] which is fully
contained in Q0_Q1.
This patch teaches TableGen to find such sub-register relationships, and
assign sub-register indices to them. In the example, TableGen will
create a dsub_1_dsub_2 sub-register index, and add D1_D2 as a
sub-register of Q0_Q1.
This will eventually enable the coalescer to handle copies of skewed
sub-registers.
llvm-svn: 156587
2012-05-10 23:27:10 +00:00
f573030391
objectsize: add support for GEPs with non-constant indexes
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add an additional parameter to InstCombiner::EmitGEPOffset() to force it to *not* emit operations with NUW flag
llvm-svn: 156585
2012-05-10 23:17:35 +00:00
4fe10a5d9a
Added X86 Atom latencies for instructions in X86InstrInfo.td.
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llvm-svn: 156579
2012-05-10 21:58:35 +00:00
ed51b9ec0b
Add support for the 'X' inline asm operand modifier.
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Patch by Jack Carter.
llvm-svn: 156577
2012-05-10 21:48:22 +00:00
c5d7008f27
misched: Print machineinstrs with -debug-only=misched
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llvm-svn: 156576
2012-05-10 21:06:21 +00:00
419eae2db7
misched: tracing register pressure heuristics.
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llvm-svn: 156575
2012-05-10 21:06:19 +00:00
7ee9de51f2
misched: Add register pressure backoff to ConvergingScheduler.
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Prioritize the instruction that comes closest to keeping pressure
under the target's limit. Then prioritize instructions that avoid
increasing the max pressure in the scheduled region. The max pressure
heuristic is a tad aggressive. Later I'll fix it to consider the
unscheduled pressure as well.
WIP: This is mostly functional but untested and not likely to do much good yet.
llvm-svn: 156574
2012-05-10 21:06:16 +00:00
795c1120a6
misched: Release only unscheduled nodes into ReadyQ.
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llvm-svn: 156573
2012-05-10 21:06:14 +00:00
95dafd8b31
misched: Added ReadyQ container wrapper for Top and Bottom Queues.
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llvm-svn: 156572
2012-05-10 21:06:12 +00:00
Chad Rosier