388769427d
Reinstate r146578; it doesn't appear to be the cause of some recent execution-
...
time regressions. In general, it is beneficial to compile-time.
Original commit message:
Fix for bug #11429 : Wrong behaviour for switches. Small improvement for code
size heuristics.
llvm-svn: 147175
2011-12-22 21:06:36 +00:00
12ccf45bbb
ARM assembler should accept shift-by-zero for any shifted-immediate operand.
...
Just treat it as-if the shift wasn't there at all. 'as' compatibility.
rdar://10604767
llvm-svn: 147153
2011-12-22 18:04:04 +00:00
f1fd6e394d
Give string constants generated by IRBuilder private linkage.
...
Fixes PR11640.
llvm-svn: 147144
2011-12-22 14:22:14 +00:00
b024aa021d
Make the unreachable probability much much heavier. The previous
...
probability wouldn't be considered "hot" in some weird loop structures
or other compounding probability patterns. This makes it much harder to
confuse, but isn't really a principled fix. I'd actually like it if we
could model a zero probability, as it would make this much easier to
reason about. Suggestions for how to do this better are welcome.
llvm-svn: 147142
2011-12-22 09:26:37 +00:00
1b7e2baf47
Speculatively revert r146578 to determine if it is the cause of a number of
...
performance regressions (both execution-time and compile-time) on our
nightly testers.
Original commit message:
Fix for bug #11429 : Wrong behaviour for switches. Small improvement for code
size heuristics.
llvm-svn: 147131
2011-12-22 02:40:57 +00:00
e2eed9649e
Local dynamic TLS model for direct object output. Create the correct TLS MIPS
...
ELF relocations.
Patch by Jack Carter.
llvm-svn: 147118
2011-12-22 01:05:17 +00:00
7869d8c01e
ARM VFP optional data type on VMOV GPR<-->SPR.
...
llvm-svn: 147104
2011-12-21 23:24:15 +00:00
8c59bbc1ed
Thumb2 assembly parsing of 'mov rd, rn, rrx'.
...
Maps to the RRX instruction. Missed this case earlier.
rdar://10615373
llvm-svn: 147096
2011-12-21 21:04:19 +00:00
b3ef713e44
Thumb2 assembly parsing of 'mov(register shifted register)' aliases.
...
These map to the ASR, LSR, LSL, ROR instruction definitions.
rdar://10615373
llvm-svn: 147094
2011-12-21 20:54:00 +00:00
c80a264386
ARM NEON assmebly parsing for VLD2 to all lanes instructions.
...
llvm-svn: 147069
2011-12-21 19:40:55 +00:00
7248bda595
Fix a couple of copy-n-paste bugs. Noticed by George Russell!
...
llvm-svn: 147064
2011-12-21 18:56:22 +00:00
b4039f633c
Make some intrinsics safe to speculatively execute.
...
llvm-svn: 147036
2011-12-21 05:52:02 +00:00
dc8a1aaea6
Fix a couple of copy-n-paste bugs. Noticed by George Russell.
...
llvm-svn: 147032
2011-12-21 03:04:10 +00:00
c5af54ec89
ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.
...
llvm-svn: 147025
2011-12-21 00:38:54 +00:00
964c891e61
Fix bug in zero-store peephole pattern reported in pr11615.
...
The patch and test case were originally written by Mans Rullgard.
llvm-svn: 147024
2011-12-21 00:31:10 +00:00
1d8efaba7e
Expand 64-bit CTLZ nodes if target architecture does not support it. Add test
...
case for DCLO and DCLZ.
llvm-svn: 147022
2011-12-21 00:20:27 +00:00
bd95275f7a
Test case for r147017.
...
llvm-svn: 147018
2011-12-20 23:58:36 +00:00
6ac54afeba
Enable and fix a test.
...
llvm-svn: 147011
2011-12-20 23:20:00 +00:00
cb2a85bc22
Add function MipsDAGToDAGISel::SelectMULT and factor out code that generates
...
nodes needed for multiplication. Add code for selecting 64-bit MULHS and MULHU
nodes.
llvm-svn: 147008
2011-12-20 23:10:57 +00:00
cf10f08825
64-bit data directive.
...
llvm-svn: 147005
2011-12-20 22:52:19 +00:00
494fdf1499
32-to-64-bit sext_inreg pattern.
...
llvm-svn: 147004
2011-12-20 22:40:40 +00:00
dac1d48d8d
Add code in MipsDAGToDAGISel for selecting constant +0.0.
...
MIPS64 can generate constant +0.0 with a single DMTC1 instruction.
llvm-svn: 146999
2011-12-20 22:25:50 +00:00
b95c102c2f
Heed spill slot alignment on ARM.
...
Use the spill slot alignment as well as the local variable alignment to
determine when the stack needs to be realigned. This works now that the
ARM target can always realign the stack by using a base pointer.
Still respect the ARMBaseRegisterInfo::canRealignStack() function
vetoing a realigned stack. Don't use aligned spill code in that case.
llvm-svn: 146997
2011-12-20 22:15:04 +00:00
2c59052984
ARM assembly parsing and encoding for VST2 single-element, double spaced.
...
llvm-svn: 146990
2011-12-20 20:46:29 +00:00
c8ebeff9a1
ARM enable a few more tests.
...
llvm-svn: 146985
2011-12-20 20:03:00 +00:00
75e2ab5db2
ARM assembly parsing and encoding for VLD2 single-element, double spaced.
...
llvm-svn: 146983
2011-12-20 19:21:26 +00:00
68132d8093
ARM target code clean up. Check for iOS, not Darwin where it makes sense.
...
llvm-svn: 146981
2011-12-20 18:26:50 +00:00
ec7e6e0946
This is the second fix related to VZEXT_MOVL node.
...
The failure that I see in the current version is:
LLVM ERROR: Cannot select: 0x18b8f70: v4i64 = X86ISD::VZEXT_MOVL 0x18beee0 [ID=14]
0x18beee0: v4i64 = insert_subvector 0x18b8c70, 0x18b9170, 0x18b9570 [ID=13]
0x18b8c70: v4i64 = insert_subvector 0x18b9870, 0x18bf4e0, 0x18b9970 [ID=12]
0x18b9870: v4i64 = undef [ID=4]
0x18bf4e0: v2i64 = bitcast 0x18bf3e0 [ID=10]
0x18bf3e0: v4i32 = BUILD_VECTOR 0x18b9770, 0x18b9770, 0x18b9770, 0x18b9770 [ID=8]
0x18b9770: i32 = TargetConstant<0> [ID=6]
0x18b9770: i32 = TargetConstant<0> [ID=6]
0x18b9770: i32 = TargetConstant<0> [ID=6]
0x18b9770: i32 = TargetConstant<0> [ID=6]
0x18b9970: i32 = Constant<0> [ID=3]
0x18b9170: v2i64 = undef [ORD=1] [ID=1]
0x18b9570: i32 = Constant<2> [ID=5]
llvm-svn: 146975
2011-12-20 13:34:28 +00:00
24680c24d8
Begin teaching the X86 target how to efficiently codegen patterns that
...
use the zero-undefined variants of CTTZ and CTLZ. These are just simple
patterns for now, there is more to be done to make real world code using
these constructs be optimized and codegen'ed properly on X86.
The existing tests are spiffed up to check that we no longer generate
unnecessary cmov instructions, and that we generate the very important
'xor' to transform bsr which counts the index of the most significant
one bit to the number of leading (most significant) zero bits. Also they
now check that when the variant with defined zero result is used, the
cmov is still produced.
llvm-svn: 146974
2011-12-20 11:19:37 +00:00
a34a8c45b4
Unit test for r146950: LSR postinc expansion, PR11571.
...
llvm-svn: 146951
2011-12-20 01:43:20 +00:00
75f12cc3fe
Mark ARM eh_sjlj_dispatchsetup as clobbering all registers. Radar 10567930.
...
We used to rely on the *eh_sjlj_setjmp instructions to mark that a function
with setjmp/longjmp exception handling clobbers all the registers. But with
the recent reorganization of ARM EH, those eh_sjlj_setjmp instructions are
expanded away earlier, before PEI can see them to determine what registers to
save and restore. Mark the dispatchsetup instruction in the same way, since
that instruction cannot be expanded early. This also more accurately reflects
when the registers are clobbered.
llvm-svn: 146949
2011-12-20 01:29:27 +00:00
e2ca9e5b5f
ARM assembly shifts by zero should be plain 'mov' instructions.
...
"mov r1, r2, lsl #0" should assemble as "mov r1, r2" even though it's
not strictly legal UAL syntax. It's a common extension and the friendly
thing to do.
rdar://10604663
llvm-svn: 146937
2011-12-20 00:59:38 +00:00
9eb3f00406
Now that PR11464 is fixed, reapply the patch to fix PR11464,
...
merging types by name when we can. We still don't guarantee type name linkage
but we do it when obviously the right thing to do. This makes LTO type names
easier to read, for example.
llvm-svn: 146932
2011-12-20 00:12:26 +00:00
5e3bd9727a
fix PR11464 by preventing the linker from mapping two different struct types from the source module onto the same opaque destination type. An opaque type can only be resolved to one thing or another after all.
...
llvm-svn: 146929
2011-12-20 00:03:52 +00:00
3bfaefe9e7
Move tests to FileCheck.
...
llvm-svn: 146923
2011-12-19 23:26:44 +00:00
8648c10184
ARM assembly parsing and encoding support for LDRD(label).
...
rdar://9932658
llvm-svn: 146921
2011-12-19 23:06:24 +00:00
37c45db189
Add a test case for r146900.
...
llvm-svn: 146901
2011-12-19 20:24:28 +00:00
db47e0c49d
Add patterns for matching immediates whose lower 16-bit is cleared. These
...
patterns emit a single LUi instruction instead of a pair of LUi and ORi.
llvm-svn: 146900
2011-12-19 20:21:18 +00:00
64f4de29e0
ARM NEON two-operand aliases for VPADD.
...
rdar://10602276
llvm-svn: 146895
2011-12-19 19:51:03 +00:00
2a232d81f6
Remove definitions of double word shift plus 32 instructions. Assembler or
...
direct-object emitter should emit the appropriate shift instruction depending
on the shift amount.
llvm-svn: 146893
2011-12-19 19:44:09 +00:00
3c9f336361
Remove the restriction on the first operand of the add node in SelectAddr.
...
This change reduces the number of instructions generated.
For example,
(load (add (sub $n0, $n1), (MipsLo got(s))))
results in the following sequence of instructions:
1. sub $n2, $n0, $n1
2. lw got(s)($n2)
Previously, three instructions were needed.
1. sub $n2, $n0, $n1
2. addiu $n3, $n2, got(s)
3. lw 0($n3)
llvm-svn: 146888
2011-12-19 19:28:37 +00:00
9ae4fc035b
ARM NEON implied destination aliases for VMAX/VMIN.
...
llvm-svn: 146885
2011-12-19 18:57:38 +00:00
cef98cddbe
ARM NEON relax parse time diagnostics for alignment specifiers.
...
There's more variation that we need to handle. Error checking will need
to be on operand predicates.
llvm-svn: 146884
2011-12-19 18:31:43 +00:00
d6cb7649d8
Allow inlining of functions with returns_twice calls, if they have the
...
attribute themselve.
llvm-svn: 146851
2011-12-18 20:35:43 +00:00
5e5bee4c52
Revert 146728 as it's causing failures on some of the external bots as well as
...
internal nightly testers. Original commit message:
By popular demand, link up types by name if they are isomorphic and one is an
autorenamed version of the other. This makes the IR easier to read, because
we don't end up with random renamed versions of the types after LTO'ing a large
app.
llvm-svn: 146838
2011-12-17 22:19:53 +00:00
8b3deabd2d
Revert r146822 at Pete Cooper's request as it broke clang self hosting.
...
Hope I did this correctly :)
llvm-svn: 146834
2011-12-17 19:48:52 +00:00
eadf124d2b
SimplifyCFG now predicts some conditional branches to true or false depending on previous branch on same comparison operands.
...
For example,
if (a == b) {
if (a > b) // this is false
Fixes some of the issues on <rdar://problem/10554090>
llvm-svn: 146822
2011-12-17 06:32:38 +00:00
3c2848ea31
Deleting the json-bench-test until I understand why it is flaky.
...
llvm-svn: 146821
2011-12-17 06:29:32 +00:00
903231bc58
Fix a CPSR liveness tracking bug introduced when I converted IT block to bundle.
...
llvm-svn: 146805
2011-12-17 01:25:34 +00:00
d3df3d3527
Add back the MC bits of 126425. Original patch by Nathan Jeffords. I added the
...
asm parsing and testcase.
llvm-svn: 146801
2011-12-17 01:14:52 +00:00
da07b3ad42
Make sure that the lower bits on the VSELECT condition are properly set.
...
llvm-svn: 146800
2011-12-17 01:08:46 +00:00
518cda42b9
The powers that be have decided that LLVM IR should now support 16-bit
...
"half precision" floating-point with a first-class type.
This patch adds basic IR support (but not codegen support).
llvm-svn: 146786
2011-12-17 00:04:22 +00:00
27886c6c1e
When recursing for the original size of a type, stop if we are at a
...
pointer or a reference type - we actually just want the size of the
pointer then for that.
Fixes rdar://10335756
llvm-svn: 146785
2011-12-16 23:42:45 +00:00
9790187b6c
Fix off-by-one error in bucket sort.
...
The bad sorting caused a misaligned basic block when building 176.vpr in
ARM mode.
<rdar://problem/10594653>
llvm-svn: 146767
2011-12-16 23:00:05 +00:00
9ca2e7293b
Hexagon: Fix a nasty order-of-initialization bug.
...
Reenable the tests.
llvm-svn: 146750
2011-12-16 19:08:59 +00:00
2c899a181c
Adds a JSON parser and a benchmark (json-bench) to catch performance regressions.
...
llvm-svn: 146735
2011-12-16 13:09:10 +00:00
3fdf98c60f
By popular demand, link up types by name if they are isomorphic and one is an
...
autorenamed version of the other. This makes the IR easier to read, because
we don't end up with random renamed versions of the types after LTO'ing a large app.
llvm-svn: 146728
2011-12-16 08:36:07 +00:00
a4d411cb1b
Don't try to match 'unpackl/h v, v' for 32xi8 and 16xi16 when only AVX1 is supported. Fix 'unpackh v, v' for 256-bit types to understand 128-bit lanes.
...
llvm-svn: 146726
2011-12-16 08:06:31 +00:00
561dade58d
[asan] add a test for instrumenting globals
...
llvm-svn: 146718
2011-12-16 01:28:19 +00:00
64944090ff
Make sure we correctly note the existence of an i8 immediate for vblendvps and friends, so we compute fixups correctly. PR11586.
...
llvm-svn: 146709
2011-12-15 23:46:18 +00:00
a47294e24d
ARM NEON VCLE is an alias for VCGE w/ the source operands reversed.
...
llvm-svn: 146699
2011-12-15 22:56:33 +00:00
4a5c887370
ARM NEON VTBL/VTBX assembly parsing and encoding.
...
llvm-svn: 146691
2011-12-15 22:27:11 +00:00
41dbf59e12
Add missing zmovl AVX patterns which were causing crashes.
...
Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!
llvm-svn: 146689
2011-12-15 22:11:31 +00:00
75ed9dcbc6
Fix assert in LowerBUILD_VECTOR for v16i16 type on AVX.
...
Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!
llvm-svn: 146684
2011-12-15 21:34:44 +00:00
918f976e66
Set specific target cpu for testcase.
...
llvm-svn: 146678
2011-12-15 20:22:34 +00:00
2d6d3a2f96
Added test case for r146671.
...
llvm-svn: 146675
2011-12-15 19:56:07 +00:00
750366f014
Add a test case to make sure that the nop really does follow the bl on ppc64 elf
...
llvm-svn: 146666
2011-12-15 17:59:23 +00:00
ef7b2f2532
Fix test.
...
llvm-svn: 146642
2011-12-15 04:52:47 +00:00
a45ab503f6
Make constant folding for GEPs a bit more aggressive.
...
llvm-svn: 146639
2011-12-15 04:33:48 +00:00
2ec824966d
Don't try to form FGETSIGN after legalization; it is possible in some cases, but the existing code can't do it correctly. PR11570.
...
llvm-svn: 146630
2011-12-15 02:07:20 +00:00
1940baa76b
Add support for lowering fneg when AVX is enabled.
...
rdar://10566486
llvm-svn: 146625
2011-12-15 01:02:25 +00:00
b33c297f14
Added InstCombine for "select cond, ~cond, x" type patterns
...
These can be reduced to "~cond & x" or "~cond | x"
llvm-svn: 146624
2011-12-15 00:56:45 +00:00
16ad2905a3
Make loop preheader insertion in LoopSimplify handle the case where the loop header is a landing pad correctly (by splitting the landingpad out of the loop header). Make some adjustments to the rest of LoopSimplify to make it clear that the rest of LoopSimplify isn't making bad assumptions about the presence of landing pads. PR11575.
...
llvm-svn: 146621
2011-12-15 00:50:34 +00:00
75d7d5e988
Move Instruction::isSafeToSpeculativelyExecute out of VMCore and
...
into Analysis as a standalone function, since there's no need for
it to be in VMCore. Also, update it to use isKnownNonZero and
other goodies available in Analysis, making it more precise,
enabling more aggressive optimization.
llvm-svn: 146610
2011-12-14 23:49:11 +00:00
a8aa30b620
ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding.
...
llvm-svn: 146605
2011-12-14 23:25:46 +00:00
c268688643
Do not sink instruction, if it is not profitable.
...
On ARM, peephole optimization for ABS creates a trivial cfg triangle which tempts machine sink to sink instructions in code which is really straight line code. Sometimes this sinking may alter register allocator input such that use and def of a reg is divided by a branch in between, which may result in extra spills. Now mahine sink avoids sinking if final sink destination is post dominator.
Radar 10266272.
llvm-svn: 146604
2011-12-14 23:20:38 +00:00
ad41ab5015
Improve the implementation of .incbin directive by replacing a loop by using
...
getStreamer().EmitBytes. Suggestion by Benjamin Kramer!
llvm-svn: 146599
2011-12-14 22:34:45 +00:00
e0ced62119
LSR: Fold redundant bitcasts on-the-fly.
...
llvm-svn: 146597
2011-12-14 22:07:19 +00:00
bb18fb4f52
ARM NEON fix alignment encoding for VST2 w/ writeback.
...
Add tests for w/ writeback instruction parsing and encoding.
llvm-svn: 146594
2011-12-14 21:49:24 +00:00
109f25c966
Add the .incbin directive which takes the binary data from a file and emits
...
it to the streamer. rdar://10383898
llvm-svn: 146592
2011-12-14 21:47:48 +00:00
8d24618975
ARM NEON VST2 assembly parsing and encoding.
...
Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.
llvm-svn: 146579
2011-12-14 19:35:22 +00:00
d7b2bb3bdd
Fix for bug #11429 : Wrong behaviour for switches. Small improvement for code size heuristics.
...
llvm-svn: 146578
2011-12-14 19:19:17 +00:00
bd944b4153
It turns out that clang does use pointer-to-function types to
...
point to ARC-managed pointers sometimes. This fixes rdar://10551239.
llvm-svn: 146577
2011-12-14 19:10:53 +00:00
bff84e1914
Add support for local dynamic TLS model in LowerGlobalTLSAddress. Direct object
...
emission is not supported yet, but a patch that adds the support should follow
soon.
llvm-svn: 146572
2011-12-14 18:26:41 +00:00
a342667fd0
ARM/Thumb2 'cmp rn, #imm' alias to cmn.
...
When 'cmp rn #imm' doesn't match due to the immediate not being representable,
but 'cmn rn, #-imm' does match, use the latter in place of the former, as
it's equivalent.
rdar://10552389
llvm-svn: 146567
2011-12-14 17:30:24 +00:00
ab5830e51b
ARM assembler support for the target-specific .req directive.
...
rdar://10549683
llvm-svn: 146543
2011-12-14 02:16:11 +00:00
7fae11b231
- Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function
...
to finalize MI bundles (i.e. add BUNDLE instruction and computing register def
and use lists of the BUNDLE instruction) and a pass to unpack bundles.
- Teach more of MachineBasic and MachineInstr methods to be bundle aware.
- Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to
prevent IT blocks from being broken apart.
llvm-svn: 146542
2011-12-14 02:11:42 +00:00
4020ae75ea
Add newline at EOF.
...
llvm-svn: 146538
2011-12-14 01:34:39 +00:00
485e5622f4
Thumb2 assembler aliases for "mov(shifted register)"
...
rdar://10549767
llvm-svn: 146520
2011-12-13 22:45:11 +00:00
18bf363078
ARM LDM/STM system instruction variants.
...
rdar://10550269
llvm-svn: 146519
2011-12-13 21:48:29 +00:00
dce106940e
Test for 146516
...
llvm-svn: 146517
2011-12-13 21:06:59 +00:00
1f1a3598c2
ARM thumb2 parsing of "rsb rd, rn, #0".
...
rdar://10549741
llvm-svn: 146515
2011-12-13 20:50:38 +00:00
4b0844e191
ARM NEON two-operand aliases for VQDMULH.
...
llvm-svn: 146514
2011-12-13 20:40:37 +00:00
561e4e18cf
ARM pre-UAL NEG mnemonic for convenience when porting old code.
...
llvm-svn: 146511
2011-12-13 20:23:22 +00:00
563de603f7
[fast-isel] Unaligned loads of floats are not supported. Therefore, convert to a regular
...
load and then move the result from a GPR to a FPR.
llvm-svn: 146502
2011-12-13 19:22:14 +00:00
7200123fa3
Add test/MC/Mips/dg.exp.
...
llvm-svn: 146472
2011-12-13 04:12:49 +00:00
341850fdc6
Move direct object emitter test to directory test/MC/Mips. Rename it to
...
elf-relsym.ll.
llvm-svn: 146470
2011-12-13 03:50:34 +00:00
e41963ce47
Relocation against a symbol, instead of against section. We had some extreme
...
test cases where there were a lot of relocations applied relative to a large
rodata section. Gas would create a symbol for each of these whereas we would
be relative to the beginning of the rodata section. This change mimics what
gas does.
Patch by Jack Carter.
llvm-svn: 146468
2011-12-13 02:27:40 +00:00
86ffb03c79
Don't rely on a particular version string for llvm.
...
llvm-svn: 146456
2011-12-13 00:34:14 +00:00
525ca5fc69
Temporarily disable Hexagon tests. They are failing on OS X
...
llvm-svn: 146455
2011-12-13 00:33:45 +00:00
Chad Rosier