Commit Graph

5807 Commits

Author SHA1 Message Date
Bob Wilson fadc2c83e5 Implement 'e' and 'f' modifiers for Neon inline asm. <rdar://problem/10551006>
These modifiers simply select either the low or high D subregister of a Neon
Q register.  I've also removed the unimplemented 'p' modifier, which turns out
to be a bit different than the comment here suggests and as far as I can tell
was only intended for internal use in Apple's version of gcc.

llvm-svn: 146417
2011-12-12 21:45:15 +00:00
Daniel Dunbar 27a7489a03 LLVMBuild: Remove trailing newline, which irked me.
llvm-svn: 146409
2011-12-12 19:48:00 +00:00
Jakob Stoklund Olesen 91a7bcbb9b Add a postOffset() alignment argument.
This computes the offset of the layout sucessor block, considering its
alignment as well.

llvm-svn: 146401
2011-12-12 19:25:54 +00:00
Jakob Stoklund Olesen 0863de458d Fix typo.
llvm-svn: 146400
2011-12-12 19:25:51 +00:00
Jakob Stoklund Olesen 17c27a8898 Also set the proper alignment on inner islands and the function itself.
Downgrade the alignment of the initial constant island when constant
pool entries are moved elsewhere.

This is all gated by -arm-align-constant-islands.

llvm-svn: 146391
2011-12-12 18:45:45 +00:00
Jakob Stoklund Olesen 2a75997858 Make MF a class member instead of passing it around everywhere.
Also add an MCP member pointing to the machine constant pool.

No functional change intended.

llvm-svn: 146382
2011-12-12 18:16:53 +00:00
Jakob Stoklund Olesen b5f52aad22 Add a -arm-align-constant-islands flag, default off.
Order constant pool entries by descending alignment in the initial
island to ensure packing and correct alignment.  When the command line
flag is set, also align the basic block containing the constant pool
entries.

This is only a partial implementation of constant island alignment. More
to come.

llvm-svn: 146375
2011-12-12 16:49:37 +00:00
Stepan Dyatkovskiy 4683740967 Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Third attempt: simplified checks in test for armv7-apple-darwin11.
llvm-svn: 146341
2011-12-11 14:35:48 +00:00
Chad Rosier 6641294e3b Revert r146322 to appease buildbots. Original commit message:
Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for
FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second
attempt.

llvm-svn: 146328
2011-12-10 19:55:03 +00:00
Stepan Dyatkovskiy df0b779e9f Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second attempt.
llvm-svn: 146322
2011-12-10 08:42:24 +00:00
Jakob Stoklund Olesen 146ac7b609 Try to align the point where a large basic block is split.
The split point is picked such that the newly created water has the same
alignment as the function. This makes the island suitable for constant
pool entries with potentially higher alignment.

This also fixes an issue where the basic block was split one instruction
too late, causing nonconvergence of the algorithm.

<rdar://problem/10550705>

There is still an issue with correctly packing differently aligned
entries in the island.

llvm-svn: 146314
2011-12-10 02:55:10 +00:00
Jakob Stoklund Olesen b3734522fa More debug output formatting.
llvm-svn: 146313
2011-12-10 02:55:06 +00:00
Jim Grosbach 54337b8617 ARM add some more pre-UAL VFP mnemonics for convenience when porting old code.
llvm-svn: 146300
2011-12-10 00:01:02 +00:00
Eli Friedman 4e36a934dc Splats can contain undef's; make sure to handle them correctly. PR11526.
llvm-svn: 146299
2011-12-09 23:54:42 +00:00
Jim Grosbach 8be2f6577e ARM add some pre-UAL VFP mnemonics for convenience when porting old code.
llvm-svn: 146296
2011-12-09 23:34:09 +00:00
Jim Grosbach ef70e9b704 ARM allows '' syntax, not just '#imm' for assembly.
Backwards compatibility with 'gas'. #imm is the preferered and documented
syntax, but lots of existing code uses the '$' prefix, so we should
support it if we can.

llvm-svn: 146285
2011-12-09 22:25:03 +00:00
Jim Grosbach 6192b6570d ARM assembly aliases for BIC<-->AND (immediate).
When the immediate operand of an AND or BIC instruction isn't representable
in the immediate field of the instruction, but the bitwise negation of the
immediate is, assemble the instruction as the inverse operation instead
with the inverted immediate as the operand.

rdar://10550057

llvm-svn: 146283
2011-12-09 22:02:17 +00:00
Jim Grosbach ea1b353e67 ARM NEON data type aliases for VBIC(register).
llvm-svn: 146281
2011-12-09 21:46:04 +00:00
Jim Grosbach d146a02c79 ARM assembly parsing and encoding for VLD2 with writeback.
Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.

Add tests for the instruction variants now supported.

llvm-svn: 146278
2011-12-09 21:28:25 +00:00
Jakob Stoklund Olesen f85723626c User a helper overload for a common pattern.
llvm-svn: 146270
2011-12-09 19:44:39 +00:00
Jim Grosbach 8a4009dab2 Tidy up. Better base class factoring.
llvm-svn: 146267
2011-12-09 19:07:20 +00:00
Jim Grosbach b076e6f3d5 Tidy up. Better base class factoring.
llvm-svn: 146266
2011-12-09 18:54:11 +00:00
Jakob Stoklund Olesen 5f5fa12413 Tweak debugging output.
llvm-svn: 146264
2011-12-09 18:20:35 +00:00
Jim Grosbach 8cc83fa1b7 ARM convenience aliases for VSQRT.
llvm-svn: 146201
2011-12-08 22:51:25 +00:00
Jim Grosbach db731be7b8 ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough.
llvm-svn: 146194
2011-12-08 22:19:04 +00:00
Jim Grosbach ba7d6ed05d ARM VSHR implied destination operand form aliases.
llvm-svn: 146192
2011-12-08 22:06:06 +00:00
Jim Grosbach 98bc797b4d ARM asm parser, just issue a warning for a duplicate reg in a list.
For better 'gas' compatibility.

llvm-svn: 146185
2011-12-08 21:34:20 +00:00
Jim Grosbach ab9c8bb45b ARM VSUB implied destination operand form aliases.
llvm-svn: 146182
2011-12-08 20:56:26 +00:00
Jim Grosbach 66c9ad7642 ARM VQADD implied destination operand form aliases.
llvm-svn: 146179
2011-12-08 20:49:43 +00:00
Jim Grosbach e9ee1092e1 ARM a few more VMUL implied destination operand form aliases.
llvm-svn: 146177
2011-12-08 20:42:35 +00:00
Jim Grosbach 4edc7360c7 ARM assembler support for register name aliases.
rdar://10550084

llvm-svn: 146170
2011-12-08 19:27:38 +00:00
Daniel Dunbar c09e4593b2 Revert r146143, "Fix bug 9905: Failure in code selection for llvm intrinsics
sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP,
FEXP2).", it is failing tests.

llvm-svn: 146157
2011-12-08 17:32:18 +00:00
Stepan Dyatkovskiy a4bcf27dae Fix bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2).
llvm-svn: 146143
2011-12-08 07:55:03 +00:00
Jim Grosbach 00326406d4 ARM NEON two-operand aliases for VSHL(immediate).
llvm-svn: 146125
2011-12-08 01:30:04 +00:00
Jakob Stoklund Olesen 14e024dff7 Drop the HasInlineAsm flag.
It is not used any more. We are tracking inline assembly misalignments
directly through the BBInfo.Unalign and KnownBits fields.

A simple conservative size estimate is not good enough since it can
cause alignment padding to be underestimated.

llvm-svn: 146124
2011-12-08 01:22:39 +00:00
Jim Grosbach f10a635eb4 ARM NEON two-operand aliases for VSHL(register).
llvm-svn: 146123
2011-12-08 01:12:35 +00:00
Jakob Stoklund Olesen bd97f5d753 Simplify offset verification.
llvm-svn: 146121
2011-12-08 01:10:05 +00:00
Jim Grosbach 0dd1bc9c79 Fix copy/past-o.
llvm-svn: 146120
2011-12-08 01:02:26 +00:00
Jim Grosbach 31a462c02c ARM NEON two-operand aliases for VMUL.
llvm-svn: 146119
2011-12-08 00:59:47 +00:00
Jakob Stoklund Olesen 2a82333f54 Don't include alignment padding in BBInfo.Size.
Compute alignment padding before and after basic blocks dynamically.

Heed basic block alignment.

This simplifies bookkeeping because we don't have to constantly add and
remove padding from BBInfo.Size.  It also makes it possible to track the
extra known alignment bits we get after a tBR_JTr terminator and when
entering an aligned basic block.

This makes the ARMConstantIslandPass aware of aligned basic blocks.

It is tricky to model block alignment correctly when dealing with inline
assembly and tBR_JTr instructions that have variable size.  If inline
assembly turns out to be smaller than expected, that may cause following
alignment padding to be larger than expected.  This could cause constant
pool entries to move out of range.

To avoid that problem, we use the worst case alignment padding following
inline assembly. This may cause slightly suboptimal constant island
placement in aligned basic blocks following inline assembly.  Normal
functions should be unaffected.

llvm-svn: 146118
2011-12-08 00:55:02 +00:00
Jim Grosbach 9a6ba3c94e ARM VFP support 'fmrs/fmsr' aliases for 'vldr'
llvm-svn: 146116
2011-12-08 00:52:55 +00:00
Jim Grosbach 086d013e56 ARM VFP support 'flds/fldd' aliases for 'vldr'
llvm-svn: 146115
2011-12-08 00:49:29 +00:00
Jim Grosbach 6600f520b0 ARM optional destination operand variants for VEXT instructions.
llvm-svn: 146114
2011-12-08 00:43:47 +00:00
Jim Grosbach 3050625a50 ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm".
llvm-svn: 146111
2011-12-08 00:31:07 +00:00
Jim Grosbach 3b559ff3c5 ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands.
For 'gas' compatibility.

llvm-svn: 146106
2011-12-07 23:40:58 +00:00
Jim Grosbach 90d961250b ARM two-operand aliases for VAND/VEOR/VORR instructions.
llvm-svn: 146095
2011-12-07 23:08:12 +00:00
Jim Grosbach 3744a7febb ARM two-operand aliases for VADDW instructions.
llvm-svn: 146093
2011-12-07 23:01:10 +00:00
Jim Grosbach 552691556c ARM two-operand aliases for VADD instructions.
llvm-svn: 146091
2011-12-07 22:52:54 +00:00
Jim Grosbach d633c2f120 Nuke inadvertant debugging commit.
llvm-svn: 146057
2011-12-07 19:56:16 +00:00
Jim Grosbach d6ae4ba002 Darwin assembler improved relocs when w/o subsections_via_symbols.
When the file isn't being built with subsections-via-symbols, symbol
differences involving non-local symbols can be resolved more aggressively.
Needed for gas compatibility.

llvm-svn: 146054
2011-12-07 19:46:59 +00:00
Jim Grosbach 18b0e5dca0 Thumb2 alias for long-form pop and friends.
rdar://10542474

llvm-svn: 146046
2011-12-07 18:32:28 +00:00
Jim Grosbach 7f882399b8 ARM support the .arm and .thumb directives for assembly mode switching.
llvm-svn: 146042
2011-12-07 18:04:19 +00:00
Jim Grosbach 721042fa3a ARM NEON VCLT(register) is a pseudo aliasing VCGT(register).
llvm-svn: 146039
2011-12-07 17:51:15 +00:00
Evan Cheng 7f8e563a69 Add bundle aware API for querying instruction properties and switch the code
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.

llvm-svn: 146026
2011-12-07 07:15:52 +00:00
Jakob Stoklund Olesen 2f0400b780 Eliminate delta argument from AdjustBBOffsetsAfter.
The block offset can be computed from the previous block. That is more
robust than keeping track of a delta.

Eliminate one redundant AdjustBBOffsetsAfter call.

llvm-svn: 146018
2011-12-07 05:17:30 +00:00
Jakob Stoklund Olesen 97c857199e Compute some alignment information for each basic block.
These fields are not used for anything yet.

llvm-svn: 146017
2011-12-07 04:17:35 +00:00
Jim Grosbach 2cf294a213 ARM tidy up and remove no longer needed InstAlias definitions.
The TokenAlias handling of data type suffices renders these unnecessary.

llvm-svn: 146010
2011-12-07 01:50:36 +00:00
Jakob Stoklund Olesen af748e1180 Move common expression into a method.
llvm-svn: 146008
2011-12-07 01:22:52 +00:00
Jim Grosbach 585ce30b8b ARM Implement ARM ARM Table A7-3 via TokenAlias.
Data type suffix aliasing. Previously handled via lots of instruction
aliases. Cleanup of those forthcoming.

rdar://10435076

llvm-svn: 146007
2011-12-07 01:17:58 +00:00
Jakob Stoklund Olesen e2b3ff2a07 Group BBSizes and BBOffsets into a single vector<BasicBlockInfo>.
No functional change is intended.

llvm-svn: 146005
2011-12-07 01:08:25 +00:00
Jim Grosbach d4b8249434 ARM: NEON SHLL instruction immediate operand range checking.
llvm-svn: 146003
2011-12-07 01:07:24 +00:00
Jim Grosbach 47c24c2084 ARM: Parameterize the immediate operand type for NEON VSHLL.
No functional change yet. Will be implementing range-checked immediates
for better diagnostics and disambiguation of instructions.

llvm-svn: 145994
2011-12-07 00:02:17 +00:00
Jakob Stoklund Olesen cc6bfa8e79 Revert r145971: "Use conservative size estimate for tBR_JTr."
This caused more offset errors.

llvm-svn: 145980
2011-12-06 22:41:31 +00:00
Evan Cheng 2a81dd4a3c First chunk of MachineInstr bundle support.
1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs

llvm-svn: 145975
2011-12-06 22:12:01 +00:00
Jakob Stoklund Olesen 33fe130e12 Use conservative size estimate for tBR_JTr.
This pseudo-instruction contains a .align directive in its expansion, so
the total size may vary by 2 bytes.

It is too difficult to accurately keep track of this alignment
directive, just use the worst-case size instead.

llvm-svn: 145971
2011-12-06 21:55:39 +00:00
Jakob Stoklund Olesen 2fa7448f31 Remove alignment from deserted constant islands.
ARMConstantIslandPass may sometimes leave empty constant islands behind
(it really shouldn't). Remove the alignment from the empty islands so
the size calculations are still correct.

This should fix the many Thumb1 assembler errors in the nightly test
suite.

The reduced test case for this problem is way too big. That is to be
expected for ARMConstantIslandPass bugs.

<rdar://problem/10534709>

llvm-svn: 145970
2011-12-06 21:55:35 +00:00
Jim Grosbach e303e24d77 ARM mode 'mul' operand ordering tweak.
Same as r145922, just for ARM mode.

llvm-svn: 145923
2011-12-06 05:28:00 +00:00
Jim Grosbach 5f143be8c5 Thumb2: MUL two-operand form encoding operand order fix.
Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we
match gas.

rdar://10532439

llvm-svn: 145922
2011-12-06 05:03:45 +00:00
Jim Grosbach 175c7d0da5 Thumb2 encoding choice correction for PLD.
Using encoding T1 for offset of #0 and encoding T2 for #-0.

rdar://10532413

llvm-svn: 145919
2011-12-06 04:49:29 +00:00
Jim Grosbach 425e180ce8 Tidy up value checking.
llvm-svn: 145895
2011-12-06 01:53:17 +00:00
Chad Rosier c77830d21e [arm-fast-isel] Doublewords only require word-alignment.
rdar://10528060

llvm-svn: 145891
2011-12-06 01:44:17 +00:00
Jakob Stoklund Olesen 2e05db2fa0 Align ARM constant pool islands via their basic block.
Previously, all ARM::CONSTPOOL_ENTRY instructions had a hardwired
alignment of 4 bytes emitted by ARMAsmPrinter.  Now the same alignment
is set on the basic block.

This is in preparation of supporting ARM constant pool islands with
different alignments.

llvm-svn: 145890
2011-12-06 01:43:02 +00:00
Jim Grosbach 9105085b4a Fix ARM handling of tBcc branch relaxation.
rdar://10069056

llvm-svn: 145885
2011-12-06 01:08:19 +00:00
Jakob Stoklund Olesen 2608157f79 Use an existing function.
llvm-svn: 145883
2011-12-06 00:51:12 +00:00
Jim Grosbach 25b63fa117 Move target-specific logic out of generic MCAssembler.
Whether a fixup needs relaxation for the associated instruction is a
target-specific function, as the FIXME indicated. Create a hook for that
and use it.

llvm-svn: 145881
2011-12-06 00:47:03 +00:00
Jim Grosbach 34a7c6dfd7 Simple branch relaxation for Thumb2 Bcc instructions.
Not right yet, as the rules for when to relax in the MCAssembler aren't
(yet) correct for ARM. This is a step in the proper direction, though.

llvm-svn: 145871
2011-12-05 23:45:46 +00:00
Jim Grosbach b8c719ccc6 Tweak ADDrr fix. Bad check for explicit .w
llvm-svn: 145863
2011-12-05 22:27:04 +00:00
Jim Grosbach e489babf9b Thumb2 prefer ADD register encoding T2 to T3 when possible.
rdar://10529664

llvm-svn: 145860
2011-12-05 22:16:39 +00:00
Jim Grosbach ec9ba98299 Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions.
rdar://10529348

llvm-svn: 145851
2011-12-05 21:06:26 +00:00
Jim Grosbach fdf9e1587a ARM assembly parsing for the rest of the VMUL data type aliases.
Finish up rdar://10522016.

llvm-svn: 145846
2011-12-05 20:29:59 +00:00
Jim Grosbach 9e90c5cde3 Fix previous commit. Oops.
llvm-svn: 145844
2011-12-05 20:12:26 +00:00
Jim Grosbach 2b37e4fc80 Tidy up. No functional change.
llvm-svn: 145843
2011-12-05 20:09:44 +00:00
Jim Grosbach 0a978ef715 ARM assmebler parsing for two-operand VMUL instructions.
Combined destination and first source operand for f32 variant of the VMUL
(by scalar) instruction.

rdar://10522016

llvm-svn: 145842
2011-12-05 19:55:46 +00:00
Bob Wilson 80381f6cbf Fix 80-column issues.
llvm-svn: 145783
2011-12-04 00:52:23 +00:00
Anton Korobeynikov 965e0c6de2 Emit the ctors in the proper order on ARM/EABI.
Maybe some targets should use this as well.

Patch by Evgeniy Stepanov!

llvm-svn: 145781
2011-12-03 23:49:37 +00:00
Chad Rosier ec3b77e00d [arm-fast-isel] Unaligned stores of floats require special care.
rdar://10510150

llvm-svn: 145742
2011-12-03 02:21:57 +00:00
Jim Grosbach 9dff9f4c41 ARM NEON VEXT aliases for data type suffices.
llvm-svn: 145726
2011-12-02 23:34:39 +00:00
Jim Grosbach 2635f54cb6 ARM VEXT tighten up operand classes a bit.
llvm-svn: 145722
2011-12-02 22:57:57 +00:00
Jim Grosbach eb53822f5a ARM VST1 single lane assembly parsing.
llvm-svn: 145718
2011-12-02 22:34:51 +00:00
Nick Lewycky 50f02cb21b Move global variables in TargetMachine into new TargetOptions class. As an API
change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.

One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.

llvm-svn: 145714
2011-12-02 22:16:29 +00:00
Jim Grosbach dda976b804 ARM VLD1 single lane assembly parsing.
llvm-svn: 145712
2011-12-02 22:01:52 +00:00
Jim Grosbach 81c9003695 ARM encoder method needs the physical register number, not the enum.
llvm-svn: 145711
2011-12-02 22:01:25 +00:00
Chad Rosier 9fd0e55e91 [arm-fast-isel] After promoting a function parameter be sure to update the
argument value type.  Otherwise, the sign/zero-extend has no effect on arguments
passed via the stack (i.e., undefined high-order bits).
rdar://10515467

llvm-svn: 145701
2011-12-02 20:25:18 +00:00
Jim Grosbach e7dcbc8691 Clean up aliases for ARM VLD1 single-lane assembly parsing a bit.
Add the 16-bit lane variants while I'm at it.

llvm-svn: 145693
2011-12-02 18:52:30 +00:00
Jim Grosbach 04945c42c6 ARM start parsing VLD1 single lane instructions.
The alias pseudos need cleaned up for size suffix handling, but this gets
the basics working. Will be cleaning up and adding more.

llvm-svn: 145655
2011-12-02 00:35:16 +00:00
Matt Beaumont-Gay 23c30b90e3 Remove unused variable
llvm-svn: 145517
2011-11-30 19:53:11 +00:00
Jim Grosbach a68c9a847e ARM parsing for VLD1 all lanes, with writeback.
llvm-svn: 145510
2011-11-30 19:35:44 +00:00
Jim Grosbach 3ecf976ca9 ARM parsing for VLD1 two register all lanes, no writeback.
llvm-svn: 145504
2011-11-30 18:21:25 +00:00
Jim Grosbach cd6f5e757c ARM parsing aliases for VLD1 single register all lanes.
llvm-svn: 145464
2011-11-30 01:09:44 +00:00
Jim Grosbach 182b6a077e Tidy up a bit.
llvm-svn: 145458
2011-11-29 23:51:09 +00:00
Jim Grosbach ae672f8118 Add comment.
llvm-svn: 145456
2011-11-29 23:33:40 +00:00
Jim Grosbach e1154eef0b ARM parsing aliases for data-size suffices on VST1.
llvm-svn: 145454
2011-11-29 23:21:31 +00:00
Jim Grosbach 5ee209ce3a ARM assembly parsing and encoding for four-register VST1.
llvm-svn: 145450
2011-11-29 22:58:48 +00:00
Jim Grosbach 98d032fd67 ARM assembly parsing and encoding for three-register VST1.
llvm-svn: 145442
2011-11-29 22:38:04 +00:00
Andrew Trick 312b97c267 comment.
llvm-svn: 145422
2011-11-29 19:33:49 +00:00
Daniel Dunbar 539d0a8a09 build/CMake: Finish removal of add_llvm_library_dependencies.
llvm-svn: 145420
2011-11-29 19:25:30 +00:00
Jim Grosbach ae9132207f Better fix for ARM MOVT relocation encoding of thumb bit.
Replaces r145318 with a more targetted fix for the relocation handling.

llvm-svn: 145346
2011-11-29 01:15:25 +00:00
Duncan Sands 12330650f8 Silence wrong warnings from GCC about variables possibly being used
uninitialized: GCC doesn't understand that the variables are only used
if !UseImm, in which case they have been initialized.

llvm-svn: 145239
2011-11-28 10:31:27 +00:00
Benjamin Kramer 7ba71be392 Move code into anonymous namespaces.
llvm-svn: 145154
2011-11-26 23:01:57 +00:00
NAKAMURA Takumi 989eaf6e3f ARMLoadStoreOptimizer.cpp: Fix MSVC(Debug) build.
llvm-svn: 145129
2011-11-25 09:19:57 +00:00
Chad Rosier ee93ff736a Guard call to getRegForValue with isTypeLegal check to avoid unnecessary work/dead code.
llvm-svn: 144959
2011-11-18 01:17:34 +00:00
Chad Rosier 0eff3e5c21 Add TODO comment.
llvm-svn: 144920
2011-11-17 21:46:13 +00:00
Chad Rosier 15b2498e88 Dead code.
llvm-svn: 144888
2011-11-17 07:24:49 +00:00
Chad Rosier ce619ddfc5 Don't unconditionally set the kill flag.
rdar://10456186

llvm-svn: 144872
2011-11-17 01:16:53 +00:00
Jim Grosbach d3f02cbce9 Generalize the fixup info for ARM mode.
We don't (yet) have the granularity in the fixups to be specific about which
bitranges are affected. That's a future cleanup, but we're not there yet.

llvm-svn: 144852
2011-11-16 22:48:37 +00:00
Jim Grosbach 7ccdb7c0ae Fix encoding of NOP used for padding in ARM mode .align.
llvm-svn: 144842
2011-11-16 22:40:25 +00:00
Jim Grosbach bfe5c5c968 ARM assembly parsing for shifted register operands for MOV instruction.
llvm-svn: 144837
2011-11-16 21:50:05 +00:00
Jim Grosbach 01e0439240 Clean up debug printing of ARM shifted operands.
llvm-svn: 144836
2011-11-16 21:46:50 +00:00
Jim Grosbach 3127ab6d8f ARM assmebly two operand forms for LSR, ASR, LSL, ROR register.
llvm-svn: 144814
2011-11-16 19:12:24 +00:00
Jim Grosbach 1a2f9ee3c8 ARM assembly parsing for RRX mnemonic.
rdar://9704684

llvm-svn: 144812
2011-11-16 19:05:59 +00:00
Chad Rosier 80979b6ea6 Check to make sure we can select the instruction before trying to put the
operands into a register.  Otherwise, we may materialize dead code.

llvm-svn: 144805
2011-11-16 18:39:44 +00:00
Jim Grosbach abcac56869 ARM mode aliases for bitwise instructions w/ register operands.
rdar://9704684

llvm-svn: 144803
2011-11-16 18:31:45 +00:00
Bob Wilson 0ca7ce389c Fix tablegen warning: hasSideEffects is inferred for eh_sjlj_dispatchsetup.
llvm-svn: 144798
2011-11-16 17:09:59 +00:00
NAKAMURA Takumi b345060a85 lib/Target/ARM/CMakeLists.txt: Disable optimization in ARMISelLowering.cpp also on MSC15(aka VS9). Seems miscompiled.
llvm-svn: 144794
2011-11-16 09:18:28 +00:00
Evan Cheng ecb2908bf9 Sink codegen optimization level into MCCodeGenInfo along side relocation model
and code model. This eliminates the need to pass OptLevel flag all over the
place and makes it possible for any codegen pass to use this information.

llvm-svn: 144788
2011-11-16 08:38:26 +00:00
Bob Wilson f6d1728d8f Fix ARM SjLj-EH dispatch setup code. <rdar://problem/10444602>
The EmitBasePointerRecalculation function has 2 problems, one minor and one
fatal.  The minor problem is that it inserts the code at the setjmp
instead of in the dispatch block.  The fatal problem is that at the point
where this code runs, we don't know whether there will be a base pointer,
so the entire function is a no-op.  The base pointer recalculation needs to
be handled as it was before, by inserting a pseudo instruction that gets
expanded late.

Most of the support for the old approach is still here, but it no longer
has any connection to the eh_sjlj_dispatchsetup intrinsic.  Clean up the
parts related to the intrinsic and just generate the pseudo instruction
directly.

llvm-svn: 144781
2011-11-16 07:11:57 +00:00
Chad Rosier af13d767a2 Add FIXME comment.
llvm-svn: 144743
2011-11-16 00:32:20 +00:00
Jakob Stoklund Olesen 653183fd5c Enable -widen-vmovs by default.
This will widen 32-bit register vmov instructions to 64-bit when
possible.  The 64-bit vmovd instructions can then be translated to NEON
vorr instructions by the execution dependency fix pass.

The copies are only widened if they are marked as clobbering the whole
D-register.

llvm-svn: 144734
2011-11-15 23:53:18 +00:00
Jim Grosbach e891fe8d6c ARM assembly parsing for register range syntax for VLD/VST register lists.
For example,
vld1.f64 {d2-d5}, [r2,:128]!

Should be equivalent to:
vld1.f64 {d2,d3,d4,d5}, [r2,:128]!

It's not documented syntax in the ARM ARM, but it is consistent with what's
accepted for VLDM/VSTM and is unambiguous in meaning, so it's a good thing to
support.

rdar://10451128

llvm-svn: 144727
2011-11-15 23:19:15 +00:00
Jim Grosbach 003cea6011 ARM assembly parsing for data type suffices on NEON VMOV aliases.
llvm-svn: 144722
2011-11-15 22:54:42 +00:00
Jim Grosbach 75fb4abcdc ARM assembly parsing two operand forms for shift instructions.
llvm-svn: 144713
2011-11-15 22:27:54 +00:00
Jim Grosbach a01033709f ARM VFP assembly parsing for VADD and VSUB two-operand forms.
llvm-svn: 144710
2011-11-15 22:15:10 +00:00
Jim Grosbach 8279c1828f ARM accept an immediate offset in memory operands w/o the '#'.
llvm-svn: 144709
2011-11-15 22:14:41 +00:00
Jim Grosbach 8d579230c6 ARM enclosing curly braces optional on one-register VLD/VST instruction lists.
'vld1.f32 d4, [r7]' should be parsed as equivalent to 'vld1.f32 {d4}, [r7]'

rdar://10450488.

llvm-svn: 144701
2011-11-15 21:45:55 +00:00
Jim Grosbach 84f0ba5747 ARM size suffix on VFP single-precision 'vmov' is optional.
rdar://10435114

llvm-svn: 144698
2011-11-15 21:18:35 +00:00
Jim Grosbach a92a5d8548 Fix typo.
llvm-svn: 144695
2011-11-15 21:01:30 +00:00
Jim Grosbach 131b45e632 ARM alternate size suffices for VTRN instructions.
rdar://10435076

llvm-svn: 144694
2011-11-15 20:49:46 +00:00
Owen Anderson 05060f0748 Fix a misplaced paren bug.
llvm-svn: 144692
2011-11-15 20:30:41 +00:00
Jim Grosbach 5803f6d5a2 ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns.
Yet more of rdar://10435076.

llvm-svn: 144691
2011-11-15 20:29:42 +00:00
Jim Grosbach c5b1bc561e ARM assembly parsing for two-operand form of 'mul' instruction.
rdar://10449856.

llvm-svn: 144689
2011-11-15 20:14:51 +00:00
Jim Grosbach 72dfd20aba ARM assembly parsing for two-operand form of 'mul' instruction.
Ongoing rdar://10435114.

llvm-svn: 144688
2011-11-15 20:02:06 +00:00
Jim Grosbach efa7e95d06 Thumb2 two-operand 'mul' instruction wide encoding parsing.
rdar://10449724

llvm-svn: 144684
2011-11-15 19:55:16 +00:00
Owen Anderson 0ac9058f89 Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32.
llvm-svn: 144683
2011-11-15 19:55:00 +00:00
Jim Grosbach 6efa7b9852 Thumb2 assembly parsing for mul.w in IT block fix.
When the 3rd operand is not a low-register, and the first two operands are
the same low register, the parser was incorrectly trying to use the 16-bit
instruction encoding.

rdar://10449281

llvm-svn: 144679
2011-11-15 19:29:45 +00:00
Jim Grosbach 2aabaa704a ARM parsing datatype suffix variants for register-writeback VLD1/VST1 instructions.
rdar://10435076

llvm-svn: 144650
2011-11-15 17:49:59 +00:00
Jay Foad e5cbd3c3fb Fix typo in comment.
llvm-svn: 144633
2011-11-15 07:50:05 +00:00
Jay Foad 465101bb0e Make use of MachinePointerInfo::getFixedStack. This removes all mention
of PseudoSourceValue from lib/Target/.

llvm-svn: 144632
2011-11-15 07:34:52 +00:00
Jay Foad 0745e645e0 Remove some unnecessary includes of PseudoSourceValue.h.
llvm-svn: 144631
2011-11-15 07:24:32 +00:00
Evan Cheng 7ca4b6eb5c Add vmov.f32 to materialize f32 immediate splats which cannot be handled by
integer variants. rdar://10437054

llvm-svn: 144608
2011-11-15 02:12:34 +00:00
Jim Grosbach 29cdcda80d ARM parsing datatype suffix variants for fixed-writeback VLD1/VST1 instructions.
rdar://10435076

llvm-svn: 144606
2011-11-15 01:46:57 +00:00