Commit Graph

96154 Commits

Author SHA1 Message Date
Akira Hatanaka af4211ad94 [mips] Make sure loads from lazy-binding entries do not get CSE'd or hoisted out
of loops.

Previously, two consecutive calls to function "func" would result in the
following sequence of instructions:

1. load $16, %got(func)($gp) // load address of lazy-binding stub.
2. move $25, $16
3. jalr $25                  // jump to lazy-binding stub.
4. nop
5. move $25, $16
6. jalr $25                  // jump to lazy-binding stub again.

With this patch, the second call directly jumps to func's address, bypassing
the lazy-binding resolution routine:

1. load $25, %got(func)($gp) // load address of lazy-binding stub.
2. jalr $25                  // jump to lazy-binding stub.
3. nop
4. load $25, %got(func)($gp) // load resolved address of func.
5. jalr $25                  // directly jump to func.

llvm-svn: 191591
2013-09-28 00:12:32 +00:00
Manman Ren f3a8c27e8d TBAA: try to fix the dragonegg bots.
llvm-svn: 191585
2013-09-27 22:59:21 +00:00
Eric Christopher a51d3fc721 Unify conditionals and reformat.
llvm-svn: 191582
2013-09-27 22:50:48 +00:00
Matt Arsenault 4c265906cc Minor code simplification
llvm-svn: 191579
2013-09-27 22:38:23 +00:00
Akira Hatanaka e0657b2419 [mips] Define a derived class of PseudoSourceValue that represents a GOT entry
resolved by lazy-binding.

llvm-svn: 191578
2013-09-27 22:30:36 +00:00
Matt Arsenault 31cfc78f81 Use right pointer type in DebugIR
llvm-svn: 191576
2013-09-27 22:26:25 +00:00
Matt Arsenault fa25272db9 Use type helper functions
llvm-svn: 191574
2013-09-27 22:18:51 +00:00
Eric Christopher 7857d489a9 Rework conditional for printing out pub sections.
llvm-svn: 191571
2013-09-27 22:10:10 +00:00
Josh Magee 8ecfb52388 [stackprotector] Refactor the StackProtector pass from a single .cpp file into StackProtector.h and StackProtector.cpp.
No functionality change.  Future patches will add analysis which will be used
in other passes (PEI, StackSlot).  The end goal is to support ssp-strong stack
layout rules.

WIP.

Differential Revision: http://llvm-reviews.chandlerc.com/D1521

llvm-svn: 191570
2013-09-27 21:58:43 +00:00
Rui Ueyama bc654b18bc Object/COFF: Rename getXXX{Begin,End} -> xxx_{begin,end}.
It is mentioned in the LLVM coding standard that _begin() and _end() suffixes
should be used.

llvm-svn: 191569
2013-09-27 21:47:05 +00:00
Rui Ueyama 4ebe2ba32c Resurrect lit.local.cfg to un-break hexagon buildbot.
llvm-svn: 191565
2013-09-27 21:26:38 +00:00
Matt Arsenault 29f31735a2 Fix SLPVectorizer using wrong address space for load/store
llvm-svn: 191564
2013-09-27 21:24:57 +00:00
Dmitri Gribenko 78fe2ba3ba SourceMgr diagnotics printing: fix a bug where printing a fixit for a source
range that includes a tab character will cause out-of-bounds access to the
fixit string.

llvm-svn: 191563
2013-09-27 21:24:36 +00:00
Renato Golin 9e3c678040 Clarifying doc about cross-compiling
llvm-svn: 191561
2013-09-27 21:14:54 +00:00
Dmitri Gribenko 8f944628ac Make SourceMgr::PrintMessage() testable and add unit tests
llvm-svn: 191558
2013-09-27 21:09:25 +00:00
Rui Ueyama c2bed42904 Re-submit r191472 with a fix for big endian.
llvm-objdump: Dump COFF import table if -private-headers option is given.
llvm-svn: 191557
2013-09-27 21:04:00 +00:00
Bill Wendling c78b4255df Update.
llvm-svn: 191553
2013-09-27 20:40:40 +00:00
Justin Bogner 4a9ac8cd75 InstCombine: Only foldSelectICmpAndOr for integer types
Currently foldSelectICmpAndOr asserts if the "or" involves a vector
containing several of the same power of two. We can easily avoid this by
only performing the fold on integer types, like foldSelectICmpAnd does.

Fixes <rdar://problem/15012516>

llvm-svn: 191552
2013-09-27 20:35:39 +00:00
Akira Hatanaka d8f10ceb51 [mips] Rewrite MipsTargetLowering::getAddr functions as template functions.
No intended functionality change.

llvm-svn: 191546
2013-09-27 19:51:35 +00:00
Yunzhong Gao b8bbcbfcc8 Adding intrinsics to the llvm backend for TBM instruction set.
Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750

llvm-svn: 191539
2013-09-27 18:38:42 +00:00
Manman Ren 0ed04fc9ab TBAA: handle scalar TBAA format and struct-path aware TBAA format.
Remove the command line argument "struct-path-tbaa" since we should not depend
on command line argument to decide which format the IR file is using. Instead,
we check the first operand of the tbaa tag node, if it is a MDNode, we treat
it as struct-path aware TBAA format, otherwise, we treat it as scalar TBAA
format.

When clang starts to use struct-path aware TBAA format no matter whether
struct-path-tbaa is no, and we can auto-upgrade existing bc files, the support
for scalar TBAA format can be dropped.

Existing testing cases are updated to use the struct-path aware TBAA format.

llvm-svn: 191538
2013-09-27 18:34:27 +00:00
Justin Bogner ca9bd8fac1 Transforms: Use getFirstNonPHI to set the insertion point for PHIs
We were previously using getFirstInsertionPt to insert PHI
instructions when vectorizing, but getFirstInsertionPt also skips past
landingpads, causing this to generate invalid IR.

We can avoid this issue by using getFirstNonPHI instead.

llvm-svn: 191526
2013-09-27 15:30:25 +00:00
Richard Sandiford 067817ee05 [SystemZ] Rein back the use of block operations
The backend tries to use block operations like MVC, NC, OC and XC for
simple scalar operations.  For correctness reasons, it rejects any case
in which the regions might partially overlap.  However, for performance
reasons, it should also reject cases where the regions might be equal,
since the instruction might then not use the fast path.

This fixes a performance regression seen in bzip2.  We may want to limit
the optimisation even more in future, or even remove it entirely, but I'll
try with this for now.

llvm-svn: 191525
2013-09-27 15:29:20 +00:00
Richard Sandiford 54b369166f [SystemZ] Improve handling of PC-relative addresses
The backend previously folded offsets into PC-relative addresses
whereever possible.  That's the right thing to do when the address
can be used directly in a PC-relative memory reference (using things
like LRL).  But if we have a register-based memory reference and need
to load the PC-relative address separately, it's better to use an anchor
point that could be shared with other accesses to the same area of the
variable.

Fixes a FIXME.

llvm-svn: 191524
2013-09-27 15:14:04 +00:00
Daniel Sanders 6098b33515 [mips][msa] Implemented insert.d intrinsic.
This intrinsic is lowered into an equivalent INSERT_VECTOR_ELT which is
further lowered into a sequence of insert.w's on MIPS32.

llvm-svn: 191521
2013-09-27 13:36:54 +00:00
Tilmann Scheller 1aebfa0a9b ARM: Teach assembler to enforce constraints for ARM LDRD destination register operands.
As specified in A8.8.72/A8.8.73/A8.8.74 in the ARM ARM, all variants of the ARM LDRD instruction have the following two constraints:

LDRD<c> <Rt>, <Rt2>, ...

(a) Rt must be even-numbered and not r14
(b) Rt2 must be R(t+1)

If those two constraints are not met the result of executing the instruction will be unpredictable.

Constraint (b) was already enforced, this commit adds support for constraint (a).

Fixes rdar://14479793.

llvm-svn: 191520
2013-09-27 13:28:17 +00:00
Daniel Sanders c72593e69a [mips][msa] Implemented fill.d intrinsic.
This intrinsic is lowered into an equivalent BUILD_VECTOR which is further
lowered into a sequence of insert.w's on MIPS32.

llvm-svn: 191519
2013-09-27 13:20:41 +00:00
Daniel Sanders 7f3d946fb7 [mips][msa] Implemented copy_[us].d intrinsic.
This intrinsic is lowered into equivalent copy_s.w instructions during
legalization.

llvm-svn: 191518
2013-09-27 13:04:21 +00:00
Daniel Sanders 51287b9355 [mips][msa] Rename arguments to MSA_INSERT_DESC_BASE to better match their expected values.
No functional change.

llvm-svn: 191517
2013-09-27 12:45:08 +00:00
Daniel Sanders a515070eb3 [mips][msa] Implemented insert_vector_elt for v4f32 and v2f64.
For v4f32 and v2f64, INSERT_VECTOR_ELT is matched by a pseudo-insn which is
later expanded to appropriate insve.[wd] insns.

llvm-svn: 191515
2013-09-27 12:31:32 +00:00
Daniel Sanders 39bb8ba023 [mips][msa] Implemented extract_vector_elt for v4f32 or v2f64
For v4f32 and v2f64, EXTRACT_VECTOR_ELT is matched by a pseudo-insn which may
be expanded to subregister copies and/or instructions as appropriate.

llvm-svn: 191514
2013-09-27 12:17:32 +00:00
Andrea Di Biagio 63192f635e Remove superfluous comment accidentally checked-in.
llvm-svn: 191513
2013-09-27 12:13:58 +00:00
Daniel Sanders 9ea9ff2da7 [mips][msa] Added support for MSA registers to copyPhysReg
llvm-svn: 191512
2013-09-27 12:03:51 +00:00
Daniel Sanders 7e51fe19d5 [mips][msa] Added support for matching splati from normal IR (i.e. not intrinsics)
Updated some of the vshf since they (correctly) emit splati's now

llvm-svn: 191511
2013-09-27 11:48:57 +00:00
Andrea Di Biagio 56ce9c4e78 Re-apply the change from r191393 with fix for pr17380.
This change fixes the problem reported in pr17380 and re-add the dagcombine 
transformation ensuring that the value types are always legal if the 
transformation is triggered after Legalization took place.

Added the test case from pr17380.

llvm-svn: 191509
2013-09-27 11:37:05 +00:00
Daniel Sanders 928920ab29 [mips][msa] Added MSA.txt to describe instruction selection quirks.
This file contains notes about the instruction selection for MSA. For example,
it notes that ilvl.d is cannot be selected because ilvev.d covers the same
cases and is selected instead of ilvl.d.

llvm-svn: 191507
2013-09-27 10:42:22 +00:00
Tilmann Scheller 041f717680 Fix comment.
llvm-svn: 191505
2013-09-27 10:38:11 +00:00
Tilmann Scheller 88c8f16558 ARM: Teach assembler to enforce constraint for Thumb2 LDRD (literal/immediate) destination register operands.
LDRD<c> <Rt>, <Rt2>, <label>
LDRD<c> <Rt>, <Rt2>, [<Rn>{, #+/-<imm>}]
LDRD<c> <Rt>, <Rt2>, [<Rn>], #+/-<imm>
LDRD<c> <Rt>, <Rt2>, [<Rn>, #+/-<imm>]!

As specified in A8.8.72/A8.8.73 in the ARM ARM, the T1 encoding has a constraint which enforces that Rt != Rt2.

If this constraint is not met the result of executing the instruction will be unpredictable.

Fixes rdar://14479780.

llvm-svn: 191504
2013-09-27 10:30:18 +00:00
Daniel Sanders 84e7caf741 [mips][msa] Tidy up
lowerMSABinaryIntr, lowerMSABinaryImmIntr, lowerMSABranchIntr,
and lowerMSAUnaryIntr were trivially small functions. Inlined them into
their callers.

lowerMSASplat now takes its callers SDLoc instead of making a new one.

No functional change.

llvm-svn: 191503
2013-09-27 10:25:41 +00:00
Daniel Sanders 1b1e25b7c5 [mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
llvm-svn: 191498
2013-09-27 10:08:31 +00:00
Daniel Sanders 36c671e2c7 [mips][msa] Expand all truncstores and loadexts for MSA as well as DSP
llvm-svn: 191496
2013-09-27 09:44:59 +00:00
Daniel Sanders f4f1a872ca [mips][msa] Added missing check in performSRACombine
Reviewers: jacksprat, dsanders

Reviewed By: dsanders

Differential Revision: http://llvm-reviews.chandlerc.com/D1755

llvm-svn: 191495
2013-09-27 09:25:29 +00:00
Puyan Lotfi 74e38de492 First check in. Modified a comment.
llvm-svn: 191491
2013-09-27 07:36:10 +00:00
Craig Topper dbe8b7d236 Put HasAVX512 predicate on some patterns to properly disable them when AVX512 isn't enabled. Currently it works simply because the SSE and AVX version of the same patterns are checked first in the DAG isel table.
llvm-svn: 191490
2013-09-27 07:20:47 +00:00
Craig Topper 8f14de8f32 Switch HasAVX to UseAVX in one spot to ensure that AVX512 form of VINSERTPS is used in AVX512 mode.
llvm-svn: 191489
2013-09-27 07:16:24 +00:00
Craig Topper c6a1aac735 Removal some duplicate patterns.
llvm-svn: 191488
2013-09-27 07:11:17 +00:00
Yunzhong Gao 4467f33e3c Fixing Intel format of the vshufpd instruction.
Phabricator code review is located at: http://llvm-reviews.chandlerc.com/D1759

llvm-svn: 191481
2013-09-27 01:44:23 +00:00
Rui Ueyama 333d28a0bb Revert "llvm-objdump: Dump COFF import table if -private-headers option is given."
This reverts commit r191472 because it's failing on BE machine.

llvm-svn: 191480
2013-09-27 01:29:36 +00:00
Rui Ueyama 6b27fe648a Fix another -Wnon-pod-varargs error in r191472.
llvm-svn: 191474
2013-09-27 00:53:07 +00:00
Rui Ueyama 9a80df5537 Fix -Wnon-pod-varargs error in r191472.
llvm-svn: 191473
2013-09-27 00:20:53 +00:00
Rui Ueyama 5b1adbaad9 llvm-objdump: Dump COFF import table if -private-headers option is given.
This is a patch to add capability to llvm-objdump to dump COFF Import Table
entries, so that we can write tests for LLD checking Import Table contents.

llvm-objdump did not print anything but just file name if the format is COFF
and -private-headers option is given. This is a patch adds capability for
dumping DLL Import Table, which is specific to the COFF format.

In this patch I defined a new iterator to iterate over import table entries.
Also added a few functions to COFFObjectFile.cpp to access fields of the entry.

Differential Revision: http://llvm-reviews.chandlerc.com/D1719

llvm-svn: 191472
2013-09-27 00:07:01 +00:00
Adrian Prantl 6ac40036f1 MCParser/Debug info: Accept line number 0 as a legitimate value, since
CFE produces it to indicate artificial locations.
c.f.: DWARF standard, Table 6.2:
line -- An unsigned integer indicating a source line number. Lines are numbered beginning at 1. The compiler may emit the value 0 in cases where an instruction cannot be attributed to any source line.

llvm-svn: 191471
2013-09-26 23:37:11 +00:00
Jack Carter cb8b40b08d [mips][msa] Direct Object Emission for 3RF instructions.
Patch by Matheus Almeida

llvm-svn: 191461
2013-09-26 21:31:43 +00:00
Jack Carter 142ec8283d [mips][msa] Updates encoding of 3RF instructions to match the latest revision of the MSA spec (1.06).
This does not affect any of the existing output.

Patch by Matheus Almeida

llvm-svn: 191460
2013-09-26 21:18:57 +00:00
Weiming Zhao 286304a317 Fix PR 17372: Emitting PLD for stack address for ARM Thumb2
t2PLDi12, t2PLDi8, t2PLDs was omitted in Thumb2InstrInfo.
This patch fixes it.

llvm-svn: 191441
2013-09-26 17:25:10 +00:00
Bill Schmidt cea1596205 [PowerPC] Fix PR17354: Generate nop after local calls for PIC code.
When generating code for shared libraries, even local calls may be
intercepted, so we need a nop after the call for the linker to fix up the
TOC.  Test case adapted from the one provided in PR17354.

llvm-svn: 191440
2013-09-26 17:09:28 +00:00
Andrea Di Biagio 549d6605a0 Revert r191393 since it caused pr17380.
llvm-svn: 191438
2013-09-26 16:54:01 +00:00
Venkatraman Govindaraju 4c0cdd734c [Sparc] Implements exception handling in SPARC with DwarfCFI.
llvm-svn: 191432
2013-09-26 15:11:00 +00:00
Venkatraman Govindaraju 3816d43a9a Implements parsing and emitting of .cfi_window_save in MC.
llvm-svn: 191431
2013-09-26 14:49:40 +00:00
Amara Emerson b4ad2f396a [ARM] Use the load-acquire/store-release instructions optimally in AArch32.
Patch by Artyom Skrobov.

llvm-svn: 191428
2013-09-26 12:22:36 +00:00
David Majnemer 7137420d94 PPC: Allow partial fills in writeNopData()
When asked to pad an irregular number of bytes, we should fill with
zeros.  This is consistent with the behavior specified in the AIX
Assembler Language Reference as well as other LLVM and binutils
assemblers.

N.B. There is a small deviation from binutils' PPC assembler:
when handling pads which are greater than 4 bytes but not mod 4,
binutils will not emit any NOP sequences at all and only use zeros.
This may or may not be a bug but there is no excellent rationale as to
why that behavior is important to emulate.  If that behavior is needed,
we can change writeNopData() to behave in the same way.

This fixes PR17352.

llvm-svn: 191426
2013-09-26 09:18:48 +00:00
Renato Golin 22a2d963b9 Add links to cross-compilation docs from getting started
llvm-svn: 191425
2013-09-26 08:57:07 +00:00
Andrew Trick 71e8bb6d1d Added temp flag -misched-bench for staging in default changes.
llvm-svn: 191423
2013-09-26 05:53:35 +00:00
Andrew Trick 6f5aad7a24 whitespace
llvm-svn: 191422
2013-09-26 05:53:31 +00:00
David Majnemer 08249a31b2 PPC: Do not introduce ISD nodes for fctid and fctiw
llvm-svn: 191421
2013-09-26 05:22:11 +00:00
David Majnemer 6ad26d3364 PPC: Add support for fctid and fctiw
Encodings were checked against the Power ISA documents and double
checked against binutils.

This fixes PR17350.

llvm-svn: 191419
2013-09-26 04:11:24 +00:00
Jack Carter 3eb663b037 [mips][msa] Direct Object Emission for 3R instructions.
This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class.
 
Patch by Matheus Almeida

llvm-svn: 191415
2013-09-26 00:09:46 +00:00
Jack Carter 77551abef4 [mips][msa] Updates encoding of 3R instructions to match the latest revision of the MSA spec (1.06).
Internal changes only.
 
Patch by Matheus Almeida

llvm-svn: 191414
2013-09-26 00:02:44 +00:00
Jack Carter 3381298227 [mips][msa] Direct Object Emission for 2RF instructions.
Patch by Matheus Almeida

llvm-svn: 191413
2013-09-25 23:56:25 +00:00
Jack Carter 5dc8ac92b9 [mips][msa] Direct Object Emission support for the MSA instruction set.
In more detail, this patch adds the ability to parse, encode and decode MSA registers ($w0-$w31). The format of 2RF instructions (MipsMSAInstrFormat.td) was updated so that we could attach a test case to this patch i.e., the test case parses, encodes and decodes 2 MSA instructions. Following patches will add the remainder of the instructions.

Note that DecodeMSA128BRegisterClass is missing from MipsDisassembler.td because it's not yet required at this stage and having it would cause a compiler warning (unused function).

Patch by Matheus Almeida

llvm-svn: 191412
2013-09-25 23:50:44 +00:00
Jack Carter 56c681eb7f [mips][msa] Updates encoding of 2RF instructions to match the latest revision of the MSA spec (1.06).
This only changes internal encodings and doesn't affect output.


Patch by Matheus Almeida

llvm-svn: 191411
2013-09-25 23:42:03 +00:00
Weiming Zhao 2052f4843b Fix PR 17368: disable vector mul distribution for square of add/sub for ARM
Generally, it is desirable to distribute (a + b) * c to a*c + b*c for
ARM with VMLx forwarding, where a, b and c are vectors.
However, for (a + b)*(a + b), distribution will result in one extra
instruction.
With distribution:
  x = a + b (add)
  y = a * x (mul)
  z = y + b * y (mla)

Without distribution:
  x = a + b (add)
  z = x * x (mul)

This patch checks if a mul is a square of add/sub. If yes, skip
distribution.

llvm-svn: 191410
2013-09-25 23:12:06 +00:00
Eric Christopher a9e303e746 Add gnu pubsections as options to llvm-dwarfdump.
Argument spelling feedback welcome.

llvm-svn: 191409
2013-09-25 23:02:44 +00:00
Eric Christopher 4c7e6ba7d3 Dump the normal dwarf pubtypes section as well.
llvm-svn: 191408
2013-09-25 23:02:41 +00:00
Eric Christopher 0de5359e20 Unify pubsection/gnu pubsection printing.
llvm-svn: 191407
2013-09-25 23:02:36 +00:00
Josh Magee 06ffaee67e Test commit. Removed trailing whitespace.
llvm-svn: 191402
2013-09-25 22:07:48 +00:00
Eric Christopher a88fd7fdb6 Slight formatting change for pubnames/pubtypes output.
llvm-svn: 191401
2013-09-25 21:17:37 +00:00
Reed Kotler a6ce797f05 Fix a bad typo in the inline assembly code for mips16 pic fp stubs
and make one cosmetic cleanup to make it look the same as gcc
in this area; adjusting test cases.

llvm-svn: 191400
2013-09-25 20:58:50 +00:00
Andrea Di Biagio 9f3313109f Teach DAGCombiner how to canonicalize dags according to the rule
(shl (zext (shr A, X)), X) => (zext (shl (shr A, X), X)).

The rule only triggers when there are no other uses of the
zext to avoid materializing more instructions.

This helps the DAGCombiner understand that the shl/shr
sequence can then be converted into an and instruction.

llvm-svn: 191393
2013-09-25 19:01:01 +00:00
Andrew Trick b6854d80e3 Mark the x86 machine model as incomplete. PR17367.
Ideally, the machinel model is added at the time the instructions are
defined. But many instructions in X86InstrSSE.td still need a model.

Without this workaround the scheduler asserts because x86 already has
itinerary classes for these instructions, indicating they should be
modeled by the scheduler. Since we use the new machine model for other
instructions, it expects a new machine model for these too.

llvm-svn: 191391
2013-09-25 18:14:12 +00:00
Joerg Sonnenberger 7278edc5b4 Undefine NetBSD, it may have been defined by an earlier include of
sys/param.h.

llvm-svn: 191384
2013-09-25 17:49:57 +00:00
Rafael Espindola 4102eafdc8 Set the minimal stack size with msvc when using cmake >= 2.8.11.
This makes sure we get the same behavior with all supported cmake versions. Once
we support only versions >= 2.8.11 we can experiment with other values or just
setting it for some binaries.

Patch by Greg Bedwell.

llvm-svn: 191372
2013-09-25 14:06:55 +00:00
Arnold Schwaighofer 07520324f5 SLPVectorize: Put horizontal reductions feeding a store under separate flag
Put them under a separate flag for experimentation. They are more likely to
interfere with loop vectorization which happens later in the pass pipeline.

llvm-svn: 191371
2013-09-25 14:02:32 +00:00
Richard Sandiford 652784e29a [SystemZ] Define the GR64 low-word logic instructions as pseudo aliases.
Another patch to avoid duplication of encoding information.  Things like
NILF, NILL and NILH are used as both 32-bit and 64-bit instructions.
Here the 64-bit versions are defined as aliases of the 32-bit ones.

llvm-svn: 191369
2013-09-25 11:11:53 +00:00
David Majnemer 0c58bc64a4 MC: Add support for treating $ as a reference to the PC
The binutils assembler supports a mode called DOLLAR_DOT which treats
the dollar sign token as a reference to the current program counter if
the dollar sign doesn't precede a constant or identifier.

This commit adds a new MCAsmInfo flag stating whether or not a given
target supports this interpretation of the dollar sign token; by
default, this flag is not enabled.

Further, enable this flag for PPC. The system assembler for AIX and
binutils both support using the dollar sign in this manner.

This fixes PR17353.

llvm-svn: 191368
2013-09-25 10:47:21 +00:00
Richard Sandiford f348f831d5 [SystemZ] Define the call instructions as pseudo aliases.
Similar to r191364, but for calls.  This patch also removes the shortening
of BRASL to BRAS within a TU.  Doing that was a bit controversial internally,
since there's a strong expectation with the z assembler that WYWIWYG.

llvm-svn: 191366
2013-09-25 10:37:17 +00:00
Richard Sandiford 6cbd7f0c5d [SystemZ] Use subregs for 64-bit truncating stores
Another patch to reduce the duplication of encoding information.
Rather than define separate patterns for truncating 64-bit stores,
use the 32-bit stores with a subreg.  No behavioral changed intended.

llvm-svn: 191365
2013-09-25 10:29:47 +00:00
Richard Sandiford 9ab97cd147 [SystemZ] Define the return instruction as a pseudo alias of BR
This is the first of a few patches to reduce the dupliation of encoding
information.  The return instruction is a normal BR in which one of the
registers is fixed.

llvm-svn: 191364
2013-09-25 10:20:08 +00:00
Richard Sandiford 35ec4e356c [SystemZ] Add instruction-shortening pass
When loading immediates into a GR32, the port prefered LHI, followed by
LLILH or LLILL, followed by IILF.  LHI and IILF are natural 32-bit
operations, but LLILH and LLILL also clear the upper 32 bits of the register.
This was represented as taking a 32-bit subreg of a 64-bit assignment.

Using subregs for something as simple as a move immediate was probably
a bad idea.  Also, I have patches to add support for the high-word facility, 
and we don't want something like LLILH and LLILL to stop the high word of
the same GPR from being used.

This patch therefore uses LHI and IILF to begin with and adds a late
machine-specific pass to use LLILH and LLILL if the other half of the
register is not live.  The high-word patches extend this behavior to
IIHF, LLIHL and LLIHH.

No behavioral change intended.

llvm-svn: 191363
2013-09-25 10:11:07 +00:00
David Majnemer 1ccd2f2aee MC: Remove vestigial PCSymbol field from AsmInfo
llvm-svn: 191362
2013-09-25 09:36:11 +00:00
Evgeniy Stepanov 32be0340f5 [msan] Fix -Wreturn-type warnings in non-self-hosted build.
llvm-svn: 191361
2013-09-25 08:56:00 +00:00
Peter Collingbourne dda3591f48 Try again to fix the MSVC build.
llvm-svn: 191359
2013-09-25 07:52:21 +00:00
Peter Collingbourne 445eb3327b Wrap the #include of <stdbool.h> in an #ifndef __cplusplus.
This should fix the MSVC build.

llvm-svn: 191357
2013-09-25 07:11:58 +00:00
Craig Topper 0ac6f9fc6a Fix doxygen comments to use correct function name.
llvm-svn: 191356
2013-09-25 06:40:22 +00:00
Craig Topper 95198f4a94 Replace EVT with MVT in CodeGenDAGAPatterns.cpp.
llvm-svn: 191355
2013-09-25 06:37:18 +00:00
Akira Hatanaka 7d92b346a7 Revert r191350.
llvm-svn: 191353
2013-09-25 00:52:34 +00:00
Akira Hatanaka f215e077bb [mips] Move public functions to the beginning of the class definition.
No intended functionality change.

llvm-svn: 191352
2013-09-25 00:34:42 +00:00
Akira Hatanaka 30f97cfa82 [mips] Define getTargetNode as a template function.
No intended functionality change.

llvm-svn: 191350
2013-09-25 00:30:25 +00:00
Quentin Colombet fa403ab3fb [PR16882] Ignore noreturn definitions when setting isPhysRegUsed.
PEI inserts a save/restore sequence for the link register, according to the
information it gets from the MachineRegisterInfo.
MachineRegisterInfo is populated by the VirtRegMap pass.
This pass was not aware of noreturn calls and was registering the definitions of
these calls the same way as regular operations.

Modify VirtRegPass so that it does not set the isPhysRegUsed information for
registers only defined by noreturn calls.
The rational is that a noreturn call is the "last instruction" of the program
(if it returns the behavior is undefined), so everything that is defined by it
cannot be used and will not interfere with anything else. Therefore, it is
pointless to account for then.

llvm-svn: 191349
2013-09-25 00:26:17 +00:00
Andrew Trick d24698c8ef CriticalAntiDepBreaker is no longer needed for armv7 scheduling.
This is being disabled because it is no longer needed for
performance. It is only used by postRAscheduler which is also planned
for removal, and it is implemented with an out-dated view of register
liveness. It consideres aliases instead of register units, assumes
valid kill flags, and assumes implicit uses on partial register
defs. Kill flags and implicit operands are error prone and impossible
to verify. We should gradually eliminate dependence on them in the
postRA phases.

Targets that still benefit from this should move to the MI
scheduler. If that doesn't solve the problem, then we should add a
hook to regalloc to optimize reload placement.

llvm-svn: 191348
2013-09-25 00:26:16 +00:00